JPS57147351A - Timing extractor - Google Patents
Timing extractorInfo
- Publication number
- JPS57147351A JPS57147351A JP56031202A JP3120281A JPS57147351A JP S57147351 A JPS57147351 A JP S57147351A JP 56031202 A JP56031202 A JP 56031202A JP 3120281 A JP3120281 A JP 3120281A JP S57147351 A JPS57147351 A JP S57147351A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- monostable
- pulse
- tau
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To emphasize a timing component by passing a multilevel signal (period; T) through a monostable circuit which outputs a pulse with pulse width tau (tau<T). CONSTITUTION:When an input signal Si crosses V0 successively to V1, the output (h) of a comparing circuit 25 is as shown by (A), the output (d) of an FF circuit 25 by (B), the output (b) of an FF circuit 23 by (C), the output (d) of the FF circuit 25 by (D), and the output (e) of a monostable circuit 26 by (E), thereby outputting a pulse with pulse width tau. When an input signal S1 crosses the V0 successively to V2, the output (h) of the comparing circuit 22 is as shown by (F), the output (d) of the FF circuit 25 by (G), and the output (c) of the FF circuit 23 by (H); and the FF circuit 25 is reset to generate its output (d) as shown by (I). Then, the monostable circuit 26 generates the output (e) of a pulse with the pulse width tau as shown by (J). Further, the monostable circuit 26 disregards the output (h) of the comparing circuit 22 at a P1, so a timing component is emphasized. The output of the monostable circuit 26 is applied to a phase synchronizing circuit 28 through a tuning circuit 27.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031202A JPS57147351A (en) | 1981-03-06 | 1981-03-06 | Timing extractor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56031202A JPS57147351A (en) | 1981-03-06 | 1981-03-06 | Timing extractor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57147351A true JPS57147351A (en) | 1982-09-11 |
Family
ID=12324823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56031202A Pending JPS57147351A (en) | 1981-03-06 | 1981-03-06 | Timing extractor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57147351A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270994A (en) * | 2007-04-18 | 2008-11-06 | Oki Electric Ind Co Ltd | Clock regeneration circuit |
-
1981
- 1981-03-06 JP JP56031202A patent/JPS57147351A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270994A (en) * | 2007-04-18 | 2008-11-06 | Oki Electric Ind Co Ltd | Clock regeneration circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6439185A (en) | Enhancing circuit | |
JPS54104230A (en) | Processing circuit for vertical synchronizing signal | |
JPS54104236A (en) | Synchronizing-signal-phase coupled circuit | |
JPS57147351A (en) | Timing extractor | |
JPS5714259A (en) | Vertical synchronizing signal separation circuit | |
SU677093A1 (en) | Signal delay time- to-dc voltage converter | |
SU1553990A1 (en) | Functional generator | |
JPS6419821A (en) | Reset synchronization delay circuit | |
JPS51140513A (en) | Color burst signal extracting circuit | |
JPS5227250A (en) | Oscillating circuit | |
JPS57106286A (en) | Reproducer for picture data signal | |
SU1172045A1 (en) | Device for generating bipulse signal | |
JPS56103560A (en) | Demodulating circuit | |
JPS5288744A (en) | Load concentrating control type receiver | |
JPS5471929A (en) | Video signal level display method | |
JPS57211823A (en) | Clock pulse generator | |
JPS57160246A (en) | Asynchronous binary signal pnm system | |
JPS53124024A (en) | Shaping circuit | |
JPS5389318A (en) | Index type color television receiver | |
JPS5558646A (en) | Conversion system of phase division code to nrz code | |
JPS56128470A (en) | Display device for processing video signal | |
JPS547849A (en) | Drift compensation circuit for sample hold circuit | |
JPS6482722A (en) | Timing clock regeneration system using delay element | |
JPS5596726A (en) | Phase shifter | |
JPS5640384A (en) | Separating circuit of video signal |