JPS56128470A - Display device for processing video signal - Google Patents
Display device for processing video signalInfo
- Publication number
- JPS56128470A JPS56128470A JP3187780A JP3187780A JPS56128470A JP S56128470 A JPS56128470 A JP S56128470A JP 3187780 A JP3187780 A JP 3187780A JP 3187780 A JP3187780 A JP 3187780A JP S56128470 A JPS56128470 A JP S56128470A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- produces
- video
- offset voltage
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/04—Display arrangements
- G01S7/06—Cathode-ray tube displays or other two dimensional or three-dimensional displays
Abstract
PURPOSE:To increase the resolution, by using a single A/D converter to obtain the video signals from plural units of video data frames with the sampling timing clock that shifts successively from the frame period starting point of the video data. CONSTITUTION:The timing generating circuit 4 produces the signal P that is used for a switch of the offset voltage to be added to the video signal, and also produces the data code conversion control signal S. The voltage generating circuit 18 receives an input of the signal P and then produces the offset voltage output Q. The video signal A is added with the offset voltage Q at an adder circuit 19, and the output R of addition is applied to the A/D converter 1. The decoder 20 converts the output given from the memory 2 into a code by the code conversion control signal supplied from the circuit 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3187780A JPS56128470A (en) | 1980-03-13 | 1980-03-13 | Display device for processing video signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3187780A JPS56128470A (en) | 1980-03-13 | 1980-03-13 | Display device for processing video signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56128470A true JPS56128470A (en) | 1981-10-07 |
Family
ID=12343259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3187780A Pending JPS56128470A (en) | 1980-03-13 | 1980-03-13 | Display device for processing video signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56128470A (en) |
-
1980
- 1980-03-13 JP JP3187780A patent/JPS56128470A/en active Pending
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