ES2090037T3 - Aparato y tecnica de programacion de rafagas. - Google Patents

Aparato y tecnica de programacion de rafagas.

Info

Publication number
ES2090037T3
ES2090037T3 ES89306134T ES89306134T ES2090037T3 ES 2090037 T3 ES2090037 T3 ES 2090037T3 ES 89306134 T ES89306134 T ES 89306134T ES 89306134 T ES89306134 T ES 89306134T ES 2090037 T3 ES2090037 T3 ES 2090037T3
Authority
ES
Spain
Prior art keywords
column latch
burst
counter
memory
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89306134T
Other languages
English (en)
Inventor
Percy P Aria
David W Stoenner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2090037T3 publication Critical patent/ES2090037T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Processing Of Color Television Signals (AREA)
  • Programmable Controllers (AREA)

Abstract

SISTEMA DE PROCESO DE DATOS QUE TIENE UN PROCESADOR, CAPAZ DE INICIAR UNA PETICION DE UNA RAFAGA REPENTINA DE TRANSFERENCIA DE DATOS, Y UNA MEMORIA. UN CONTROLADOR DE MEMORIA SE HALLA CONECTADO AL PROCESADOR Y A LA MEMORIA. EL CONTROLADOR INCLUYE UN REGISTRO CONTADOR DE RAFAGAS QUE TIENE ALMACENADO UN VALOR EN EL MISMO REPRESENTATIVO DEL NUMERO MAXIMO DE TRANSFERENCIAS DE DATOS PERMITIDOS EN CADA RAFAGA. ASIMISMO, EN EL CONTROLADOR DE MEMORIA SE ENCUENTRA UN CONTADOR/ENGANCHADOR DE COLUMNA QUE TIENE ALMACENADO UN VALOR REPRESENTATIVO DE UNA DIRECCION DE ENGANCHE DE COLUMNA. EL CONTADOR/ENGANCHADOR ES CAPAZ DE INCREMENTAR LA DIRECCION. FINALMENTE, INCLUIDA EN EL CONTROLADOR DE MEMORIA, HAY UNA MASCARA PROGRAMABLE PARA ESPECIFICAR LOS BITS EN EL CONTADOR/ENGANCHADOR DE COLUMNA A COMPARAR CON LOS BITS CORRESPONDIENTES DEL REGISTRO CONTADOR DE RAFAGAS.
ES89306134T 1988-06-24 1989-06-16 Aparato y tecnica de programacion de rafagas. Expired - Lifetime ES2090037T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/211,357 US5134699A (en) 1988-06-24 1988-06-24 Programmable burst data transfer apparatus and technique

Publications (1)

Publication Number Publication Date
ES2090037T3 true ES2090037T3 (es) 1996-10-16

Family

ID=22786599

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89306134T Expired - Lifetime ES2090037T3 (es) 1988-06-24 1989-06-16 Aparato y tecnica de programacion de rafagas.

Country Status (7)

Country Link
US (1) US5134699A (es)
EP (1) EP0348113B1 (es)
JP (1) JP2992552B2 (es)
AT (1) ATE141424T1 (es)
DE (1) DE68926936T2 (es)
ES (1) ES2090037T3 (es)
GR (1) GR3020706T3 (es)

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CA2145363C (en) * 1994-03-24 1999-07-13 Anthony Mark Jones Ram interface
JP3155144B2 (ja) * 1994-03-25 2001-04-09 ローム株式会社 データ転送方法及び装置
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US5644788A (en) * 1994-10-28 1997-07-01 Cyrix Corporation Burst transfers using an ascending or descending only burst ordering
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US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
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US6611796B1 (en) * 1999-10-20 2003-08-26 Texas Instruments Incorporated Method and apparatus for combining memory blocks for in circuit emulation
US6477610B1 (en) 2000-02-04 2002-11-05 International Business Machines Corporation Reordering responses on a data bus based on size of response
US6580659B1 (en) * 2000-08-25 2003-06-17 Micron Technology, Inc. Burst read addressing in a non-volatile memory device
US6449203B1 (en) * 2001-03-08 2002-09-10 Micron Technology, Inc. Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
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US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
US6751143B2 (en) * 2002-04-11 2004-06-15 Micron Technology, Inc. Method and system for low power refresh of dynamic random access memories
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Also Published As

Publication number Publication date
DE68926936D1 (de) 1996-09-19
GR3020706T3 (en) 1996-11-30
US5134699A (en) 1992-07-28
ATE141424T1 (de) 1996-08-15
EP0348113A2 (en) 1989-12-27
JP2992552B2 (ja) 1999-12-20
DE68926936T2 (de) 1997-02-27
EP0348113B1 (en) 1996-08-14
JPH0266662A (ja) 1990-03-06
EP0348113A3 (en) 1991-09-11

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