ES2087462T3 - Metodo para fabricar un circuito integrado con contacto autoalineado entre caracteristicas situadas a corta distancia. - Google Patents
Metodo para fabricar un circuito integrado con contacto autoalineado entre caracteristicas situadas a corta distancia.Info
- Publication number
- ES2087462T3 ES2087462T3 ES92310147T ES92310147T ES2087462T3 ES 2087462 T3 ES2087462 T3 ES 2087462T3 ES 92310147 T ES92310147 T ES 92310147T ES 92310147 T ES92310147 T ES 92310147T ES 2087462 T3 ES2087462 T3 ES 2087462T3
- Authority
- ES
- Spain
- Prior art keywords
- self
- manufacture
- integrated circuit
- short distance
- aligned contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
SE FORMAN CONTACTOS AUTOALIENADOS PARA REGIONES (3) ENTRE CARACTERISTICAS ESTRECHAMENTE SEPARADAS (5) MEDIANTE UN METODO QUE UTILIZA RELACIONES DE DECAPADO DIFERENCIALES ENTRE DIELECTRICOS PRIMERO Y SEGUNDO (15,17) DEPOSITADOS SOBRE CARACTERISTICAS ESTRECHAMENTE SEPARADAS (5).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/793,070 US5200358A (en) | 1991-11-15 | 1991-11-15 | Integrated circuit with planar dielectric layer |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2087462T3 true ES2087462T3 (es) | 1996-07-16 |
Family
ID=25158998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES92310147T Expired - Lifetime ES2087462T3 (es) | 1991-11-15 | 1992-11-05 | Metodo para fabricar un circuito integrado con contacto autoalineado entre caracteristicas situadas a corta distancia. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5200358A (es) |
EP (1) | EP0542477B1 (es) |
JP (1) | JP2622059B2 (es) |
DE (1) | DE69211093T2 (es) |
ES (1) | ES2087462T3 (es) |
HK (1) | HK180096A (es) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5296400A (en) * | 1991-12-14 | 1994-03-22 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a contact of a highly integrated semiconductor device |
US5880022A (en) * | 1991-12-30 | 1999-03-09 | Lucent Technologies Inc. | Self-aligned contact window |
KR960002073B1 (ko) * | 1992-06-10 | 1996-02-10 | 삼성전자주식회사 | 반도체 장치의 제조방법 |
US5880036A (en) * | 1992-06-15 | 1999-03-09 | Micron Technology, Inc. | Method for enhancing oxide to nitride selectivity through the use of independent heat control |
US5322805A (en) * | 1992-10-16 | 1994-06-21 | Ncr Corporation | Method for forming a bipolar emitter using doped SOG |
JP2925416B2 (ja) * | 1992-11-09 | 1999-07-28 | 株式会社東芝 | 半導体集積回路装置の製造方法 |
US5340774A (en) * | 1993-02-04 | 1994-08-23 | Paradigm Technology, Inc. | Semiconductor fabrication technique using local planarization with self-aligned transistors |
US5385866A (en) * | 1994-06-22 | 1995-01-31 | International Business Machines Corporation | Polish planarizing using oxidized boron nitride as a polish stop |
US5480837A (en) * | 1994-06-27 | 1996-01-02 | Industrial Technology Research Institute | Process of making an integrated circuit having a planar conductive layer |
US5482894A (en) * | 1994-08-23 | 1996-01-09 | Texas Instruments Incorporated | Method of fabricating a self-aligned contact using organic dielectric materials |
JP3277103B2 (ja) * | 1995-09-18 | 2002-04-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP3703885B2 (ja) * | 1995-09-29 | 2005-10-05 | 株式会社東芝 | 半導体記憶装置とその製造方法 |
US5668037A (en) * | 1995-10-06 | 1997-09-16 | Micron Technology, Inc. | Method of forming a resistor and integrated circuitry having a resistor construction |
WO1997014185A1 (en) * | 1995-10-11 | 1997-04-17 | Paradigm Technology, Inc. | Semiconductor device with a planarized interconnect with poly-plug and self-aligned contacts |
US6489213B1 (en) * | 1996-01-05 | 2002-12-03 | Integrated Device Technology, Inc. | Method for manufacturing semiconductor device containing a silicon-rich layer |
DE19655076B4 (de) * | 1996-01-26 | 2005-03-10 | Mitsubishi Electric Corp | Halbleitereinrichtung und Herstellungsverfahren einer Halbleitereinrichtung |
JPH09205185A (ja) | 1996-01-26 | 1997-08-05 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
US5960304A (en) * | 1996-05-20 | 1999-09-28 | Texas Instruments Incorporated | Method for forming a contact to a substrate |
US5672531A (en) * | 1996-07-17 | 1997-09-30 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5874340A (en) * | 1996-07-17 | 1999-02-23 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls |
US5877050A (en) * | 1996-09-03 | 1999-03-02 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals |
US5677224A (en) * | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
US6051471A (en) * | 1996-09-03 | 2000-04-18 | Advanced Micro Devices, Inc. | Method for making asymmetrical N-channel and symmetrical P-channel devices |
US5648286A (en) * | 1996-09-03 | 1997-07-15 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region |
US5909622A (en) * | 1996-10-01 | 1999-06-01 | Advanced Micro Devices, Inc. | Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant |
US5985724A (en) * | 1996-10-01 | 1999-11-16 | Advanced Micro Devices, Inc. | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer |
US5783458A (en) * | 1996-10-01 | 1998-07-21 | Advanced Micro Devices, Inc. | Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer |
US5893739A (en) * | 1996-10-01 | 1999-04-13 | Advanced Micro Devices, Inc. | Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer |
US5930592A (en) * | 1996-10-01 | 1999-07-27 | Advanced Micro Devices, Inc. | Asymmetrical n-channel transistor having LDD implant only in the drain region |
US6027978A (en) * | 1997-01-28 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a non-uniform lateral doping profile in the channel region |
US5923982A (en) * | 1997-04-21 | 1999-07-13 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps |
US5963809A (en) * | 1997-06-26 | 1999-10-05 | Advanced Micro Devices, Inc. | Asymmetrical MOSFET with gate pattern after source/drain formation |
US6004849A (en) * | 1997-08-15 | 1999-12-21 | Advanced Micro Devices, Inc. | Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source |
US5776821A (en) * | 1997-08-22 | 1998-07-07 | Vlsi Technology, Inc. | Method for forming a reduced width gate electrode |
US5904529A (en) * | 1997-08-25 | 1999-05-18 | Advanced Micro Devices, Inc. | Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate |
US6130137A (en) * | 1997-10-20 | 2000-10-10 | Micron Technology, Inc. | Method of forming a resistor and integrated circuitry having a resistor construction |
US6096588A (en) * | 1997-11-01 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of making transistor with selectively doped channel region for threshold voltage control |
US5883006A (en) * | 1997-12-12 | 1999-03-16 | Kabushiki Kaisha Toshiba | Method for making a semiconductor device using a flowable oxide film |
US6303496B1 (en) * | 1999-04-27 | 2001-10-16 | Cypress Semiconductor Corporation | Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit |
US6303043B1 (en) * | 1999-07-07 | 2001-10-16 | United Microelectronics Corp. | Method of fabricating preserve layer |
US6730619B2 (en) * | 2000-06-15 | 2004-05-04 | Samsung Electronics Co., Ltd. | Method of manufacturing insulating layer and semiconductor device including insulating layer |
KR100604555B1 (ko) * | 2001-06-21 | 2006-07-28 | 주식회사 하이닉스반도체 | 반도체 소자의 커패시터 제조 방법 |
DE102007030058B3 (de) * | 2007-06-29 | 2008-12-24 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung eines dielektrischen Zwischenschichtmaterials mit erhöhter Zuverlässigkeit über einer Struktur, die dichtliegende Leitungen aufweist |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS566452A (en) * | 1979-06-27 | 1981-01-23 | Toshiba Corp | Production of semiconductor device |
EP0280276B1 (en) * | 1987-02-27 | 1993-05-19 | Kabushiki Kaisha Toshiba | Ultraviolet erasable nonvolatile semiconductor memory device and manufacturing method therefor |
JP2562609B2 (ja) * | 1987-08-07 | 1996-12-11 | 三洋電機株式会社 | 半導体装置の製造方法 |
JPH0227717A (ja) * | 1988-07-15 | 1990-01-30 | Toshiba Corp | 半導体装置の製造方法 |
IT1225624B (it) * | 1988-10-20 | 1990-11-22 | Sgs Thomson Microelectronics | Procedimento per formare contatti metallo-semiconduttore autoallineatiin dispositivi integrati contenenti strutture misfet |
US5037777A (en) * | 1990-07-02 | 1991-08-06 | Motorola Inc. | Method for forming a multi-layer semiconductor device using selective planarization |
US5069747A (en) * | 1990-12-21 | 1991-12-03 | Micron Technology, Inc. | Creation and removal of temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on exposed, permanent silicon dioxide structures |
JPH04317358A (ja) * | 1991-04-16 | 1992-11-09 | Sony Corp | 半導体装置の製造方法 |
-
1991
- 1991-11-15 US US07/793,070 patent/US5200358A/en not_active Expired - Lifetime
-
1992
- 1992-11-05 ES ES92310147T patent/ES2087462T3/es not_active Expired - Lifetime
- 1992-11-05 EP EP92310147A patent/EP0542477B1/en not_active Expired - Lifetime
- 1992-11-05 DE DE69211093T patent/DE69211093T2/de not_active Expired - Lifetime
- 1992-11-13 JP JP4327544A patent/JP2622059B2/ja not_active Expired - Lifetime
-
1996
- 1996-09-26 HK HK180096A patent/HK180096A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5200358A (en) | 1993-04-06 |
DE69211093D1 (de) | 1996-07-04 |
EP0542477B1 (en) | 1996-05-29 |
HK180096A (en) | 1996-10-04 |
JP2622059B2 (ja) | 1997-06-18 |
EP0542477A1 (en) | 1993-05-19 |
JPH0669193A (ja) | 1994-03-11 |
DE69211093T2 (de) | 1996-10-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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