DE19655076B4 - Halbleitereinrichtung und Herstellungsverfahren einer Halbleitereinrichtung - Google Patents

Halbleitereinrichtung und Herstellungsverfahren einer Halbleitereinrichtung Download PDF

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Publication number
DE19655076B4
DE19655076B4 DE19655076A DE19655076A DE19655076B4 DE 19655076 B4 DE19655076 B4 DE 19655076B4 DE 19655076 A DE19655076 A DE 19655076A DE 19655076 A DE19655076 A DE 19655076A DE 19655076 B4 DE19655076 B4 DE 19655076B4
Authority
DE
Germany
Prior art keywords
semiconductor device
manufacturing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19655076A
Other languages
English (en)
Inventor
Takahisa Eimori
Hiroshi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP8011624A external-priority patent/JPH09205185A/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to DE19629736A priority Critical patent/DE19629736C2/de
Priority claimed from DE19629736A external-priority patent/DE19629736C2/de
Application granted granted Critical
Publication of DE19655076B4 publication Critical patent/DE19655076B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19655076A 1996-01-26 1996-07-23 Halbleitereinrichtung und Herstellungsverfahren einer Halbleitereinrichtung Expired - Fee Related DE19655076B4 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19629736A DE19629736C2 (de) 1996-01-26 1996-07-23 Halbleitereinrichtung mit selbstjustierendem Kontakt und Herstellungsverfahren dafür

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8011624A JPH09205185A (ja) 1996-01-26 1996-01-26 半導体装置および半導体装置の製造方法
DE19629736A DE19629736C2 (de) 1996-01-26 1996-07-23 Halbleitereinrichtung mit selbstjustierendem Kontakt und Herstellungsverfahren dafür

Publications (1)

Publication Number Publication Date
DE19655076B4 true DE19655076B4 (de) 2005-03-10

Family

ID=26027759

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19655076A Expired - Fee Related DE19655076B4 (de) 1996-01-26 1996-07-23 Halbleitereinrichtung und Herstellungsverfahren einer Halbleitereinrichtung
DE19655075A Expired - Fee Related DE19655075C2 (de) 1996-01-26 1996-07-23 Halbleitereinrichtung mit Kontaktlöchern und Herstellungsverfahren einer Halbleitereinrichtung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19655075A Expired - Fee Related DE19655075C2 (de) 1996-01-26 1996-07-23 Halbleitereinrichtung mit Kontaktlöchern und Herstellungsverfahren einer Halbleitereinrichtung

Country Status (1)

Country Link
DE (2) DE19655076B4 (de)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US5206187A (en) * 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop
JPH05226333A (ja) * 1992-02-12 1993-09-03 Sharp Corp 半導体装置の製造方法
US5298463A (en) * 1991-08-30 1994-03-29 Micron Technology, Inc. Method of processing a semiconductor wafer using a contact etch stop
US5380680A (en) * 1992-10-20 1995-01-10 Hyundai Electronics Industries Co., Ltd. Method for forming a metal contact of a semiconductor device
US5384287A (en) * 1991-12-13 1995-01-24 Nec Corporation Method of forming a semiconductor device having self-aligned contact holes
US5578524A (en) * 1994-03-30 1996-11-26 Nec Corporation Fabrication process of a semiconductor device with a wiring structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200358A (en) * 1991-11-15 1993-04-06 At&T Bell Laboratories Integrated circuit with planar dielectric layer
KR0140646B1 (ko) * 1994-01-12 1998-07-15 문정환 반도체장치의 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US5206187A (en) * 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop
US5298463A (en) * 1991-08-30 1994-03-29 Micron Technology, Inc. Method of processing a semiconductor wafer using a contact etch stop
US5384287A (en) * 1991-12-13 1995-01-24 Nec Corporation Method of forming a semiconductor device having self-aligned contact holes
JPH05226333A (ja) * 1992-02-12 1993-09-03 Sharp Corp 半導体装置の製造方法
US5380680A (en) * 1992-10-20 1995-01-10 Hyundai Electronics Industries Co., Ltd. Method for forming a metal contact of a semiconductor device
US5578524A (en) * 1994-03-30 1996-11-26 Nec Corporation Fabrication process of a semiconductor device with a wiring structure

Also Published As

Publication number Publication date
DE19655075C2 (de) 2003-04-03

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