ES2072895T3 - Sistema de microordenador con multiples lineas de transmision con arbitraje de una linea general de transmision. - Google Patents

Sistema de microordenador con multiples lineas de transmision con arbitraje de una linea general de transmision.

Info

Publication number
ES2072895T3
ES2072895T3 ES89302162T ES89302162T ES2072895T3 ES 2072895 T3 ES2072895 T3 ES 2072895T3 ES 89302162 T ES89302162 T ES 89302162T ES 89302162 T ES89302162 T ES 89302162T ES 2072895 T3 ES2072895 T3 ES 2072895T3
Authority
ES
Spain
Prior art keywords
bus
phase
allocation
assignment
process unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89302162T
Other languages
English (en)
Inventor
Ralph Murray Begun
Patrick Maurice Bland
Mark Edward Dean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2072895T3 publication Critical patent/ES2072895T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/28—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00 for polarising
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B21/00—Projectors or projection-type viewers; Accessories therefor
    • G03B21/54—Accessories
    • G03B21/56—Projection screens
    • G03B21/60—Projection screens characterised by the nature of the surface
    • G03B21/604—Polarised screens
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Optics & Photonics (AREA)
  • Computer Security & Cryptography (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

UN MICROCOMPUTADOR MULTI-BUS INCLUYE UN SUBSISTEMA OCULTO Y UN SUPERVISOR DE ASIGNACION. UNA UNIDAD CENTRAL DE PROCESO ESTA DOTADA DE UNA FUENTE DE SEÑAL DE PRIORIDAD QUE GENERA UNA SEÑAL DE PRIORIDAD EN LOS CICLOS DE LA UNIDAD CENTRAL DE PROCESO QUE SE EXTIENDEN MAS ALLA DE UNA DURACION ESPECIFICADA. LA SEÑAL DE PRIORIDAD ES EFECTIVA EN CUALQUIER DISPOSITIVO QUE TENGA ACCESO AL BUS PARA INICIAR UNA FINALIZACION ORDENADA DEL USO DEL BUS. CUANDO ESTE DISPOSITIVO SEÑALA LA FINALIZACION DE LA UTILIZACION DEL BUS, EL SUPERVISOR DE ASIGNACION CAMBIA EL ESTADO DE UN CONDUCTOR ARB/GRANT, DE SU FASE DE CESION A SU FASE DE ASIGNACION. DURANTE LA FASE DE ASIGNACION, CADA UNO DE LOS DISPOSITIVOS (DISTINTOS DE LA UNIDAD CENTRAL DE PROCESO) COOPERA EN UN MECANISMO DE ASIGNACION PARA LA UTILIZACION DEL BUS DURANTE LA SIGUIENTE FASE DE CESION. POR OTRO LADO, LA UNIDAD CENTRAL DE PROCESO, QUE HA ESTABLECIDO LA PRIORIDAD, RESPONDE A UNA SEÑAL QUE INDICA EL INICIO DE LA FASE DE ASIGNACION PROPORCIONANDO INMEDIATAMENTE EL ACCESO AL BUS DEL SISTEMA.
ES89302162T 1988-05-26 1989-03-03 Sistema de microordenador con multiples lineas de transmision con arbitraje de una linea general de transmision. Expired - Lifetime ES2072895T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,895 US5129090A (en) 1988-05-26 1988-05-26 System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration

Publications (1)

Publication Number Publication Date
ES2072895T3 true ES2072895T3 (es) 1995-08-01

Family

ID=22735319

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89302162T Expired - Lifetime ES2072895T3 (es) 1988-05-26 1989-03-03 Sistema de microordenador con multiples lineas de transmision con arbitraje de una linea general de transmision.

Country Status (23)

Country Link
US (1) US5129090A (es)
EP (1) EP0343770B1 (es)
JP (1) JPH0623970B2 (es)
CN (1) CN1010808B (es)
AT (1) ATE123162T1 (es)
AU (1) AU611287B2 (es)
BE (1) BE1002405A4 (es)
BR (1) BR8902388A (es)
CA (1) CA1317682C (es)
DE (2) DE68922784T2 (es)
DK (1) DK189889A (es)
ES (1) ES2072895T3 (es)
FI (1) FI96145C (es)
FR (1) FR2632096B1 (es)
GB (1) GB2219176A (es)
HK (1) HK23696A (es)
IT (1) IT1230191B (es)
MX (1) MX171578B (es)
MY (1) MY111733A (es)
NL (1) NL8901282A (es)
NO (1) NO176038C (es)
NZ (1) NZ228785A (es)
SE (1) SE8901306L (es)

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US5249297A (en) * 1991-04-29 1993-09-28 Hewlett-Packard Company Methods and apparatus for carrying out transactions in a computer system
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US5537600A (en) * 1991-05-28 1996-07-16 International Business Machines Corporation Personal computer with alternate system controller
US5392417A (en) * 1991-06-05 1995-02-21 Intel Corporation Processor cycle tracking in a controller for two-way set associative cache
CA2067599A1 (en) * 1991-06-10 1992-12-11 Bruce Alan Smith Personal computer with riser connector for alternate master
US5255373A (en) * 1991-08-07 1993-10-19 Hewlett-Packard Company Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle
US5630163A (en) * 1991-08-09 1997-05-13 Vadem Corporation Computer having a single bus supporting multiple bus architectures operating with different bus parameters
US5581731A (en) * 1991-08-30 1996-12-03 King; Edward C. Method and apparatus for managing video data for faster access by selectively caching video data
CA2068010C (en) * 1991-08-30 1996-10-22 Robert Chih-Tsin Eng Alternate master bursting data rate management techniques for use in computer systems having dual bus architecture
US5430860A (en) * 1991-09-17 1995-07-04 International Business Machines Inc. Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence
US5301282A (en) * 1991-10-15 1994-04-05 International Business Machines Corp. Controlling bus allocation using arbitration hold
JPH05210977A (ja) * 1991-10-15 1993-08-20 Internatl Business Mach Corp <Ibm> メモリ・リフレッシュ制御装置
US5371872A (en) * 1991-10-28 1994-12-06 International Business Machines Corporation Method and apparatus for controlling operation of a cache memory during an interrupt
US5237695A (en) * 1991-11-01 1993-08-17 Hewlett-Packard Company Bus contention resolution method for network devices on a computer network having network segments connected by an interconnection medium over an extended distance
US5548762A (en) * 1992-01-30 1996-08-20 Digital Equipment Corporation Implementation efficient interrupt select mechanism
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JP3057934B2 (ja) * 1992-10-30 2000-07-04 日本電気株式会社 共有バス調停機構
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Also Published As

Publication number Publication date
JPH0218657A (ja) 1990-01-22
CN1010808B (zh) 1990-12-12
ATE123162T1 (de) 1995-06-15
DE68922784D1 (de) 1995-06-29
NO891585D0 (no) 1989-04-18
FI96145B (fi) 1996-01-31
BR8902388A (pt) 1990-01-16
EP0343770A3 (en) 1990-11-22
EP0343770A2 (en) 1989-11-29
US5129090A (en) 1992-07-07
AU611287B2 (en) 1991-06-06
FR2632096B1 (fr) 1991-09-20
MX171578B (es) 1993-11-08
IT1230191B (it) 1991-10-18
DK189889D0 (da) 1989-04-19
GB2219176A (en) 1989-11-29
NO176038B (no) 1994-10-10
DK189889A (da) 1989-11-27
FR2632096A1 (fr) 1989-12-01
DE3909948A1 (de) 1989-11-30
IT8920626A0 (it) 1989-05-24
NO891585L (no) 1989-11-27
BE1002405A4 (fr) 1991-01-29
SE8901306D0 (sv) 1989-04-11
HK23696A (en) 1996-02-16
JPH0623970B2 (ja) 1994-03-30
FI96145C (fi) 1996-05-10
NO176038C (no) 1995-01-18
NZ228785A (en) 1991-04-26
DE3909948C2 (es) 1990-05-31
CN1037982A (zh) 1989-12-13
DE68922784T2 (de) 1995-11-30
EP0343770B1 (en) 1995-05-24
GB8904919D0 (en) 1989-04-12
NL8901282A (nl) 1989-12-18
SE8901306L (sv) 1989-11-27
AU3409789A (en) 1989-11-30
FI891786A7 (fi) 1989-11-27
CA1317682C (en) 1993-05-11
FI891786A0 (fi) 1989-04-14
MY111733A (en) 2000-12-30

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