KR940017435A - 프로세서간 직렬버스통신 방법 및 장치 - Google Patents

프로세서간 직렬버스통신 방법 및 장치 Download PDF

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Publication number
KR940017435A
KR940017435A KR1019920027493A KR920027493A KR940017435A KR 940017435 A KR940017435 A KR 940017435A KR 1019920027493 A KR1019920027493 A KR 1019920027493A KR 920027493 A KR920027493 A KR 920027493A KR 940017435 A KR940017435 A KR 940017435A
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KR
South Korea
Prior art keywords
processors
serial communication
serial bus
bus communication
processor
Prior art date
Application number
KR1019920027493A
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English (en)
Other versions
KR0150011B1 (ko
Inventor
이현철
Original Assignee
정장호
금성정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정장호, 금성정보통신 주식회사 filed Critical 정장호
Priority to KR1019920027493A priority Critical patent/KR0150011B1/ko
Publication of KR940017435A publication Critical patent/KR940017435A/ko
Application granted granted Critical
Publication of KR0150011B1 publication Critical patent/KR0150011B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 프로세서간 직렬버스 통신 방식에 관한 것으로, 다수의 프로세서가 버스 중재 수단을 통해 직렬 통신 채널을 공유하여 사용하는 경우 직렬 통신 채널의 사용 효율을 증가 시킬 수 있도록한 프로세서간 직렬 통신 방법 및 장치에 관한 것이다.

Description

프로세서간 직렬버스통신 방법 및 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 프로세서간 직렬 버스통신 장치 구성도, 제4도는 제3도에 도시된 프로세서간 직렬 버스 통신 장치의 동작 타이밍도.

Claims (2)

  1. SIO등의 직렬 통신소자나 등가품을 사용하는 복수 프로세서간 통신에 있어서 종료 flag를 감지하여 프로세서의 전송채널 점유를 종료하는 프로세서간 직렬 통신 방법.
  2. 제3도에 도시된 바와 같은 구성으로 이루어진 것을 특징으로 하는 프로세서간 직렬 통신 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920027493A 1992-12-31 1992-12-31 프로세서간 직렬버스통신 장치 KR0150011B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027493A KR0150011B1 (ko) 1992-12-31 1992-12-31 프로세서간 직렬버스통신 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027493A KR0150011B1 (ko) 1992-12-31 1992-12-31 프로세서간 직렬버스통신 장치

Publications (2)

Publication Number Publication Date
KR940017435A true KR940017435A (ko) 1994-07-26
KR0150011B1 KR0150011B1 (ko) 1998-10-15

Family

ID=19348681

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027493A KR0150011B1 (ko) 1992-12-31 1992-12-31 프로세서간 직렬버스통신 장치

Country Status (1)

Country Link
KR (1) KR0150011B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9301608B2 (en) 2013-07-16 2016-04-05 Samsung Electronics Co., Ltd. Storage having pair of drawers drawn in opposite directions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9301608B2 (en) 2013-07-16 2016-04-05 Samsung Electronics Co., Ltd. Storage having pair of drawers drawn in opposite directions

Also Published As

Publication number Publication date
KR0150011B1 (ko) 1998-10-15

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