ES2046172T3 - Maquinas de calculo de crc. - Google Patents

Maquinas de calculo de crc.

Info

Publication number
ES2046172T3
ES2046172T3 ES198686309177T ES86309177T ES2046172T3 ES 2046172 T3 ES2046172 T3 ES 2046172T3 ES 198686309177 T ES198686309177 T ES 198686309177T ES 86309177 T ES86309177 T ES 86309177T ES 2046172 T3 ES2046172 T3 ES 2046172T3
Authority
ES
Spain
Prior art keywords
crc
bits
data
byte
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198686309177T
Other languages
English (en)
Inventor
Sunil P. Joshi
Venkatraman Iyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2046172T3 publication Critical patent/ES2046172T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Heat Sensitive Colour Forming Recording (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

SE DESCRIBE UN CIRCUITO DE CALCULO CRC QUE PUEDE CALCULAR BITS DE CONTROL CRC EN 8 BITS DE DATOS DE ENTRADA POR BYTE DE RELOJ. EL APARATO DE CALCULO EMPLEA 8 FILAS DE ENLACES MOVILES, CON LAS ENTRADAS DE CADA FILA ACOPLADAS A LAS SALIDAS DE DATOS DE LA FILA PRECEDENTE. CADA ENLACE MOVIL MUEVE SU BIT DE ENTRADA UN BIT HACIA EL BIT MAS SIGNIFICATIVO, Y ENLACES MOVILES SELECCIONADOS LLEVAN A CABO UNA OPERACION DE O EXCLUYENTE ENTRE SUS BITS DE ENTRADA Y EL RESULTADO DE UNA PUERTA DE ENTRADA DE O EXCLUYENTE. SE UTILIZA UN BUS DE SALIDA DE UN BYTE PARA ACCEDER A LOS BITS DE CONTROL FINALES DESDE EL REGISTRO DE SUMA, ANULANDO EL CONJUNTO DE LOS ENLACES MOVILES DURANTE LOS CICLOS DE SALIDA, DE MANERA QUE LOS BYTES DE LOS DATOS CRC PUEDEN MOVERSE A POSICION EN EL CONJUNTO, UN BYTE POR CADA CICLO DE BYTE DE RELOJ. SE INCLUYE LA LOGICA PREFIJADA PARA FORZAR TODOS LOS PRIMEROS LOGICOS EN LAS ENTRADAS DE DATOS DE LA PRIMERA FILA DE ENLACES MOVILES, DE FORMA QUE LA MAQUINA PUEDE PREFIJARSE DURANTE LOSPRIMEROS CICLOS DE RELOJ DEL CALCULO CRC. SE DESCRIBEN DIFERENTES ARQUITECTURAS PARA PERMITIR EL CALCULO SEPARADO DE BITS CRC EN UN PAQUETE DE ENCABEZAMIENTO Y UN PAQUETE DE DATOS, EN EL CUAL LOS BITS CRC PUEDEN CALCULARSE UNICAMENTE SOBRE LOS DATOS O CON LOS DATOS MAS EL PAQUETE DE ENCABEZAMIENTO Y LOS BITS CRC DE ESTE. SE DESCRIBE IGUALMENTE LA LOGICA PARA POSIBILITAR EL CALCULO CRC EN TODOS LOS BYTES DE UN MENSAJE A LA VEZ QUE SE EXCLUYE UN NUMERO SELECCIONADO DE BITS EN EL PRIMER BYTE.
ES198686309177T 1985-12-02 1986-11-25 Maquinas de calculo de crc. Expired - Lifetime ES2046172T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/803,367 US4712215A (en) 1985-12-02 1985-12-02 CRC calculation machine for separate calculation of checkbits for the header packet and data packet

Publications (1)

Publication Number Publication Date
ES2046172T3 true ES2046172T3 (es) 1994-02-01

Family

ID=25186354

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198686309177T Expired - Lifetime ES2046172T3 (es) 1985-12-02 1986-11-25 Maquinas de calculo de crc.

Country Status (6)

Country Link
US (1) US4712215A (es)
EP (1) EP0230730B1 (es)
JP (1) JPH0831802B2 (es)
AT (1) ATE97276T1 (es)
DE (1) DE3689285T2 (es)
ES (1) ES2046172T3 (es)

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DE69217930T2 (de) * 1992-07-14 1997-09-25 Alcatel Bell Nv Teiler zur Division eines ersten Polynoms durch ein zweites
DE69217931T2 (de) * 1992-07-14 1997-09-25 Alcatel Bell Nv Fehlererkennungs- und Fehlerkorrektureinrichtung
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US5390196A (en) * 1992-11-12 1995-02-14 Bull Hn Information Systems Inc. Byte-wise determination of a checksum from a CRC-32 polynomial
SE470544B (sv) * 1992-11-24 1994-07-25 Ellemtel Utvecklings Ab För en bitfelsövervakning i en väljarutrustning avsedd anordning
EP0631703A4 (en) * 1992-12-29 1996-03-20 Codex Corp DEVICE AND METHOD FOR THE POWERFUL GENERATION AND TESTING OF CRC REMAINS.
EP0614294A1 (en) * 1993-03-03 1994-09-07 International Business Machines Corporation Method for generating a frame check sequence
JP2814918B2 (ja) * 1994-07-07 1998-10-27 株式会社デンソー マイクロコンピュータ
US5592498A (en) * 1994-09-16 1997-01-07 Cirrus Logic, Inc. CRC/EDC checker system
FR2759796B1 (fr) * 1997-02-19 2001-12-07 Bull Sa Dispositif et procede de detection d'erreurs sur un circuit integre comportant un port parallele serie
US5951707A (en) * 1997-06-27 1999-09-14 International Business Machines Corporation Method of partitioning CRC calculation for a low-cost ATM adapter
US6075774A (en) * 1997-11-18 2000-06-13 3Com Corporation Method and device for generating a frame check sequence
US6681203B1 (en) * 1999-02-26 2004-01-20 Lucent Technologies Inc. Coupled error code protection for multi-mode vocoders
US6320501B1 (en) 1999-05-25 2001-11-20 Pittway Corporation Multiple sensor system for alarm determination with device-to-device communications
US6681364B1 (en) 1999-09-24 2004-01-20 International Business Machines Corporation Cyclic redundancy check for partitioned frames
US6530061B1 (en) * 1999-12-23 2003-03-04 Intel Corporation Method and apparatus for offloading checksum
US6848072B1 (en) * 2000-09-19 2005-01-25 Bbn Solutions Llc Network processor having cyclic redundancy check implemented in hardware
US6643821B2 (en) * 2000-11-30 2003-11-04 Stmicroelectronics, Inc. Method and device for computing incremental checksums
US20040015771A1 (en) * 2002-07-16 2004-01-22 Menahem Lasser Error correction for non-volatile memory
US7607070B2 (en) * 2004-09-13 2009-10-20 National Instruments Corporation System and method for in-line consistency checking of packetized data
US20060253768A1 (en) * 2005-05-03 2006-11-09 Intel Corporation Techniques to speculatively determine network protocol unit integrity
DE102005029515A1 (de) * 2005-06-25 2006-12-28 Bosch Rexroth Aktiengesellschaft Verfahren zur Berechnung von CRC-Prüfwerten und Logikschaltung
KR101224591B1 (ko) * 2006-02-23 2013-01-22 삼성전자주식회사 네트워크 중계 장치 및 그 방법
GB0607976D0 (en) * 2006-04-22 2006-05-31 Univ Belfast Apparatus and method for computing an error detection code
US7823043B2 (en) * 2006-05-10 2010-10-26 Sandisk Il Ltd. Corruption-resistant data porting with multiple error correction schemes
US8234539B2 (en) * 2007-12-06 2012-07-31 Sandisk Il Ltd. Correction of errors in a memory array
US9891985B1 (en) * 2014-11-01 2018-02-13 Netronome Systems, Inc. 256-bit parallel parser and checksum circuit with 1-hot state information bus
TWI698750B (zh) * 2018-03-20 2020-07-11 慧榮科技股份有限公司 存取快閃記憶體模組的方法及相關的快閃記憶體控制器與電子裝置
TWI658364B (zh) * 2018-03-20 2019-05-01 慧榮科技股份有限公司 存取快閃記憶體模組的方法及相關的快閃記憶體控制器與電子裝置
CN113300716A (zh) * 2020-07-14 2021-08-24 阿里巴巴集团控股有限公司 循环冗余校验码的生成方法、设备以及计算机可读介质

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Also Published As

Publication number Publication date
ATE97276T1 (de) 1993-11-15
JPH0831802B2 (ja) 1996-03-27
JPS62133825A (ja) 1987-06-17
DE3689285D1 (de) 1993-12-16
DE3689285T2 (de) 1994-05-11
EP0230730A2 (en) 1987-08-05
US4712215A (en) 1987-12-08
EP0230730B1 (en) 1993-11-10
EP0230730A3 (en) 1990-03-14

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