ES2029833T3 - Sistena de visualizacion de video con microprocesador. - Google Patents

Sistena de visualizacion de video con microprocesador.

Info

Publication number
ES2029833T3
ES2029833T3 ES87303096T ES87303096T ES2029833T3 ES 2029833 T3 ES2029833 T3 ES 2029833T3 ES 87303096 T ES87303096 T ES 87303096T ES 87303096 T ES87303096 T ES 87303096T ES 2029833 T3 ES2029833 T3 ES 2029833T3
Authority
ES
Spain
Prior art keywords
video
cpu
access
video display
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES87303096T
Other languages
English (en)
Inventor
John Flare Technology Mathieson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amstrad PLC
Original Assignee
Amstrad PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amstrad PLC filed Critical Amstrad PLC
Application granted granted Critical
Publication of ES2029833T3 publication Critical patent/ES2029833T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Digital Computer Display Output (AREA)

Abstract

EN UN SISTEMA DE DISPLAY DE VIDEO DE UN MICROPROCESADOR, SE PUEDE ACCEDER A LA MEMORIA QUE CONTIENE EL MAPA DE PIXELES (10), TANTO POR LA CPU (12), COMO POR EL LOGICAL DE DISPLAY DE VIDEO (14), EL CUAL COMUNICA LOS DATOS DEL VIDEO AL DISPLAY. CONTRARIAMENTE A LA PRACTICA MAS ACEPTADA, EL DEBATE ENTRE PETICIONES DE ACCESO SIMULTANEAS DESDE LA CPU Y EL LOGICAL DE DISPLAY DE VIDEO, SE EVITAN POR EL LOGICAL DE DISPLAY DE VIDEO, APLAZANDO SU PETICION DE ACCESO PARA UN PERIODO DE ACCESO DE MEMORIA DE VIDEO. ESTO ES ACEPTABLE PORQUE EL LOGICAL DE CONTROL DE VIDEO, PUEDE ACCEDER A LOS DATOS EN UNA PROPORCION DOBLE DE LA REQUERIDA POR EL DISPLAY, EL RANGO DE ACCESO DE LA MEMORIA DE VIDEO ES EL MISMO QUE EL RANGO DE RELOJ DE LA CPU, Y EL MICROPROCESADOR ACCEDE A LA MEMORIA PARA UN SOLO PERIODO DE RELOJ, DURANTE LOS CICLOS DE OPERACION, TARDANDO TRES O CUATRO PULSOS DE RELOJ. LA OPERACION DE LA CPU ES MANTENIDA DE ESTA FORMA A SU MAXIMA VELOCIDAD, SIN QUE LOS DATOS DE VIDEO DILATEN SU TIEMPO DE MANERA ADVERSA.
ES87303096T 1986-04-10 1987-04-09 Sistena de visualizacion de video con microprocesador. Expired - Lifetime ES2029833T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB868608776A GB8608776D0 (en) 1986-04-10 1986-04-10 Video memory contention mechanism

Publications (1)

Publication Number Publication Date
ES2029833T3 true ES2029833T3 (es) 1992-10-01

Family

ID=10595998

Family Applications (1)

Application Number Title Priority Date Filing Date
ES87303096T Expired - Lifetime ES2029833T3 (es) 1986-04-10 1987-04-09 Sistena de visualizacion de video con microprocesador.

Country Status (4)

Country Link
EP (1) EP0241288B1 (es)
DE (1) DE3776940D1 (es)
ES (1) ES2029833T3 (es)
GB (2) GB8608776D0 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001652A (en) * 1987-03-20 1991-03-19 International Business Machines Corporation Memory arbitration for video subsystems
EP0283565B1 (en) * 1987-03-20 1992-12-30 International Business Machines Corporation Computer system with video subsystem
JP2557077B2 (ja) * 1987-12-21 1996-11-27 エイ・ティ・アンド・ティ グローバル インフォメーション ソルーションズ インターナショナル インコーポレイテッド 同期アクセス方式のキヤラクタ表示システム
GB9027678D0 (en) * 1990-12-20 1991-02-13 Ncr Co Videographics display system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263648A (en) * 1978-12-26 1981-04-21 Honeywell Information Systems Inc. Split system bus cycle for direct memory access of peripherals in a cathode ray tube display system
JPS55127656A (en) * 1979-03-26 1980-10-02 Agency Of Ind Science & Technol Picture memory unit
JPS588348A (ja) * 1981-07-07 1983-01-18 Sony Corp 出力表示用メモリの制御回路
JPS58192148A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 演算処理装置

Also Published As

Publication number Publication date
GB8608776D0 (en) 1986-05-14
GB2189632B (en) 1990-03-14
GB2189632A (en) 1987-10-28
EP0241288B1 (en) 1992-03-04
GB8708478D0 (en) 1987-05-13
EP0241288A2 (en) 1987-10-14
DE3776940D1 (de) 1992-04-09
EP0241288A3 (en) 1989-02-08

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