GB2189632A

GB2189632A - Microprocessor video display system

Info

Publication number: GB2189632A
Application number: GB08708478A
Authority: GB
Inventors: John Mathieson
Original assignee: Amstrad PLC
Current assignee: Amstrad PLC
Priority date: 1986-04-10
Filing date: 1987-04-09
Publication date: 1987-10-28
Anticipated expiration: 2007-04-09
Also published as: GB8608776D0; DE3776940D1; EP0241288B1; EP0241288A2; GB8708478D0; ES2029833T3; GB2189632B; EP0241288A3

Abstract

In a microprocessor video display system a pixel-mapped video memory (10) can be accessed both by the CPU (12) and by video display logic (14) which delivers video data to the display. Contrary to accepted practice, contention between simultaneous access requests from the CPU and video display logic is avoided by the video display logic deferring its access request for one video memory access period. This is acceptable because: the video control logic can access data at a rate twice that required by the display, the video memory access cycle rate is the same as the CPU clock rate, and the microprocessor accesses the memory for one clock period during operation cycles lasting three or four clock periods. The CPU operation is thus kept at its maximum speed without the video data being adversely delayed. <IMAGE>

Description

1 GB2189632A 1 SPECIFICATION opcode fetch cycle and the data read or write

cycle. The opcode fetch cycle is four clock Microprocessor video display system periods long, and the memory read or write cycle is three clock periods long. Therefore, This invention relates to a microprocessor vi70 the shortest possible interval is between two deo display system of the type in which a consecutive memory read or write cycles, microprocessor CPU (central processor unit) which will be three cycle times apart.

and video control logic for producing the vi- Thus in accordance with this invention in deo image signal for display share a common such a system the contention mechanism op- video memory. 75 erates on the basis that during the first of the A Z80 microprocessor can be used in such two video memory cycles available to the VCL an arrangement, with the video memory di- for each pixel the video data ready cycle will rectly accessible by both the microprocessor occur, unless the CPU wishes to perform a CPU and the video control logic (VCL). In this video memory cycle, in which case the video situation, it is necessary to provide an arbitra- 80 data ready cycle is deferred until the second tion scheme to cope with the situation where of the cycles times in its interval. If a video simultaneous memory accesses are attempted memory read cycle has taken place in the first by both the CPU and the VCL. This situation of these two cycles then a CPU cycle may is termed -contention-. freely take place in the second. Therefore The standard solution to the problem of 85 both the video display mechanism and the providing a piece of memory accessable by CPU have what is effectively non-delayed ac both the CPU and the VCL is to prevent ac- cess to the video memory.

cess by the CPU to the video memory during An example of the invention will now be video data read operations by the VCL. This described in more detail by way of example is normally done with a signal called WAIT, 90 with reference to the accompanying drawing, which forces the CPU to suspend memory ac- in which:

cess cycles and go into an inactive state, and Figure 1 is a block diagram of the relevant so prevents contention. However, this reduces part of a known microprocessor video display the performance of the CPU because it must system, and then spend part of its time inactive, with the 95 Figure 2 is a block diagram of the corre result that the programs running on it run sponding part of a microprocessor video dis more slowly. play system embodying the invention.

The present inventor has however appreci- Both figures illustrate a pixelmapped video ated that this inactivity can be avoided in nor- memory 10 accessible both by a Z80 CPU 12 mal circumstances. The invention is defined in 100 and by video control logic (VCL) 14 which the appended claims to which reference supplies data on an output 16 to a video dis should now be made. play device (not shown) incorporating a cath In a microcomputer system such as for ode ray tube screen.

example one based on the Z80 microproces- In the known arrangement of Fig. 1, when sor and with a pixel-mapped video display, it 105 the VCL 14 calls for a data item from the is necessary for the video control logic to memory 10 it also sends a WAIT command read data regularly from the video memory to 18 to the CPU, if the CPU is also attempting convert it into the signals to drive the display to address the video memory, to render the device, which may be, for example, a televi- CPU inactive for one video memory access sion set. It is not possible for the VCL to 110 cycle so as to avoid any danger of contention.

delay data read operations, or there would be This is logical enough because the display de gaps visible in the displayed picture. The disvice has to be fed an uninterrupted supply of play system is therefore organised so that the data otherwise the display will have gaps in it.

time necessary for the given video data read In accordance with this invention the VCL operation, i.e. the time it takes for that data 115 does not send a WAIT command to the CPU to be displayed on the video display device, but, as shown in Fig. 2, the VCL makes an corresponds to the time it takes for twice that enquiry IVIREO, of the CPU as to whether the amount of data to be read from the video CPU is attempting to addrerss video memory, memory. The inventor has appreciated there- and if it is the VCL defers its video memory fore, that it may be considered that a given 120 read operation by one video memory cycle video data read cycle has an interval of two period. This goes contrary to the accepted video memory cycle times during which the practice because it introduces delay into the video data read cycle may take place. video data for the display.

The inventor has also appreciated that it can However, because the video data can in fact be assumed that the CPU will not perform 125 be read from the video memory twice as fast two video memory access cycles in a row, as is necessary to supply the display, the pre providing the video memory.access rate and sent inventor has appeciated that a delay of the CPU clock rate are substantially the same. just one video memory cycle period can be This assumption is valid because the Z80 per- tolerated. Furthermore, because the video forms two basic types of memory cycle, the 130 memory access rate is equal to the CPU clock 2 GB2189632A 2 rate, and each CPU operation cycle takes at least two CPU clock periods, only one of which will ever involve a video memory access, the CPU will never call for video mem- ory access on two successive CPU clock periods.

Deferring of a VCL video memory read cycle will thus never arise on two successive video memory access cycles and the VCL will thus always be able to maintain delivery of video data at the required rate to the display.

In summary, therefore, the mechanism described and illustrated is used in a microcomputer application to allow the memory which holds the video display data to be read by both the microprocessor and the video display hardware. This it does in a manner which causes no reduction in the performance of the microprocessor, by interleaving the video read cycles between the microprocessor memory cycles in such a manner that a video read cycle may be shifted to allow the microprocessor immediate access to the memory. The standard mechanism to perform this would delay the microprocessor cycle, and therefore reduce the performance of the microprocessor. In the present system the microprocessor CPU can have the maximum possible performance as it is not degraded by the video con- trol logic.

Claims

1. A microprocessor video display system comprising a video memory, a CPU capable of accessing the video memory for one clock period during operation cycles each lasting two or more CPU clock periods, video control logic for accessing the video memory during selected video memory read cycles to provide data to a video display device, the video control logic being capable of accessing the video memory at a rate twice as fast as the rate at which data is required to be delivered to the video display device, and the video memory read cycle rate being substantially equal to the CPU clock rate, and in which when both the CPU and the video display device desire access to the video memory the operation of the video control logic is deferred by one vi- deo memory access period.

2. A microprocessor video display system according to claim 1, in which the CPU is comprised by a Z80 microprocessor.

3. A microprocessor video display system according to claim 1 or 2 in which the video memory is a pixel-mapped video memory.

4. A microprocessor video display system substantially as herein described with reference to and as shown in Fig. 2 of the draw- ing.

Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd, Did 8991685, 1987. Published at The Patent Office, 25 Southampton Buildings, London. WC2A 1 AY, from which copies may be obtained.