EP0241288A2 - Microprocessor video display system - Google Patents

Microprocessor video display system Download PDF

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Publication number
EP0241288A2
EP0241288A2 EP87303096A EP87303096A EP0241288A2 EP 0241288 A2 EP0241288 A2 EP 0241288A2 EP 87303096 A EP87303096 A EP 87303096A EP 87303096 A EP87303096 A EP 87303096A EP 0241288 A2 EP0241288 A2 EP 0241288A2
Authority
EP
European Patent Office
Prior art keywords
video
cpu
microprocessor
memory
video memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87303096A
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German (de)
French (fr)
Other versions
EP0241288B1 (en
EP0241288A3 (en
Inventor
John Flare Technology Mathieson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amstrad PLC
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Amstrad PLC
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Publication date
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Publication of EP0241288A2 publication Critical patent/EP0241288A2/en
Publication of EP0241288A3 publication Critical patent/EP0241288A3/en
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Publication of EP0241288B1 publication Critical patent/EP0241288B1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Definitions

  • This invention relates to a microprocessor video display system of the type in which a microprocessor CPU (central processor unit) and video control logic for producing the video image signal for display share a common video memory.
  • a microprocessor CPU central processor unit
  • video control logic for producing the video image signal for display share a common video memory.
  • a Z80 microprocessor can be used in such an arrangement, with the video memory directly accessible by both the microprocessor CPU and the video control logic (VCL).
  • VCL video control logic
  • the standard solution to the problem of providing a piece of memory accessable by both the CPU and the VCL is to prevent access by the CPU to the video memory during video data read operations by the VCL. This is normally done with a signal called WAIT, which forces the CPU to suspend memory access cycles and go into an inactive state, and so prevents contention. However, this reduces the performance of the CPU because it must then spend part of its time inactive, with the result that the programs running on it run more slowly.
  • WAIT a signal
  • a microcomputer system such as for example one based on the Z80 microprocessor and with a pixel-mapped video display
  • the video control logic it is necessary for the video control logic to read data regularly from the video memory to convert it into the signals to drive the display device, which may be, for example, a television set.
  • the VCL it is not possible for the VCL to delay data read operations, or there would be gaps visible in the displayed picture.
  • the display system is therefore organised so that the time necessary for the given video data read operation, i.e. the time it takes for that data to be displayed on the video display device, corresponds to the time it takes for twice that amount of data to be read from the video memory.
  • the inventor has appreciated therefore, that it may be considered that a given video data read cycle has an interval of two video memory cycle times during which the video data read cycle may take place.
  • the inventor has also appreciated that it can be assumed that the CPU will not perform two video memory access cycles in a row, providing the video memory access rate and the CPU clock rate are substantially the same. This assumption is valid because the Z80 performs two basic types of memory cycle, the opcode fetch cycle and the data read or write cycle.
  • the opcode fetch cycle is four clock periods long, and the memory read or write cycle is three clock periods long. Therefore, the shortest possible interval is between two consecutive memory read or write cycles, which will be three cycle times apart.
  • the contention mechanism operates on the basis that during the first of the two video memory cycles available to the VCL for each pixel the video data ready cycle will occur, unless the CPU wishes to perform a video memory cycle, in which case the video data ready cycle is deferred until the second of the cycles times in its interval. If a video memory read cycle has taken place in the first of these two cycles then a CPU cycle may freely take place in the second. Therefore both the video display mechanism and the CPU have what is effectively non-delayed access to the video memory.
  • Both figures illustrate 8 pixel-mapped video memory 10 accessible both by a Z80 CPU 12 and by video control logic (VCL) 14 which supplies data on an output 16 to a video display device (not shown) incorporating a cathode ray tube screen.
  • VCL video control logic
  • the VCL does not send a WAIT command to the CPU but, as shown in Figure 2, the VCL makes an enquiry MREQ of the CPU as to whether the CPU is attempting to addrerss video memory, and if it is the VCL defers its video memory read operation by one video memory cycle period. This goes contrary to the accepted practice because it introduces delay into the video data for the display.
  • the present inventor has appreciated that a delay of just one video memory cycle period can be tolerated.
  • the video memory access rate is equal to the CPU clock rate, and each CPU operation cycle takes at least two CPU clock periods, only one of which will ever involve a video memory access, the CPU will never call for video memory access on two successive CPU clock periods.
  • VCL VCL
  • the mechanism described and illustrated is used in a microcomputer application to allow the memory which holds the video display data to be read by both the microprocessor and the video display hardware. This it does in a manner which causes no reduction in the performance of the microprocessor, by interleaving the video read cycles between the microprocessor memory cycles in such a manner that a video read cycle may be shifted to allow the microprocessor immediate access to the memory.
  • the standard mechanism to perform this would delay the microprocessor cycle, and therefore reduce the performance of the microprocessor.
  • the microprocessor CPU can have the maximum possible performance as it is not degraded by the video control logic.

Abstract

In a microprocessor video display system a pixel-mapped video memory (10) can be accessed both by the CPU (12) and by video display logic (14) which delivers video data to the display. Contrary to accepted practice, contention between simultaneous access requests from the CPU and video display logic is avoided by the video display logic deferring its access request for one video memory access period. This is acceptable because: the video control logic can access data at a rate twice that required by the display, the video memory access cycle rate is the same as the CPU clock rate, and the microprocessor accesses the memory for one clock period during operation cycles lasting three orfourclock pulses. The CPU operation is thus kept at its maximum speed without the video data being adversely delayed.

Description

  • This invention relates to a microprocessor video display system of the type in which a microprocessor CPU (central processor unit) and video control logic for producing the video image signal for display share a common video memory.
  • A Z80 microprocessor can be used in such an arrangement, with the video memory directly accessible by both the microprocessor CPU and the video control logic (VCL). In this situation, it is necessary to provide an arbitration scheme to cope with the situation where simultaneous memory accesses are attempted by both the CPU and the VCL. This situation is termed "contention".
  • The standard solution to the problem of providing a piece of memory accessable by both the CPU and the VCL is to prevent access by the CPU to the video memory during video data read operations by the VCL. This is normally done with a signal called WAIT, which forces the CPU to suspend memory access cycles and go into an inactive state, and so prevents contention. However, this reduces the performance of the CPU because it must then spend part of its time inactive, with the result that the programs running on it run more slowly.
  • The present inventor has however appreciated that this inactivity can be avoided in normal circumstances. The invention is defined in the appended claims to which reference should now be made.
  • In a microcomputer system such as for example one based on the Z80 microprocessor and with a pixel-mapped video display, it is necessary for the video control logic to read data regularly from the video memory to convert it into the signals to drive the display device, which may be, for example, a television set. It is not possible for the VCL to delay data read operations, or there would be gaps visible in the displayed picture. The display system is therefore organised so that the time necessary for the given video data read operation, i.e. the time it takes for that data to be displayed on the video display device, corresponds to the time it takes for twice that amount of data to be read from the video memory. The inventor has appreciated therefore, that it may be considered that a given video data read cycle has an interval of two video memory cycle times during which the video data read cycle may take place.
  • The inventor has also appreciated that it can be assumed that the CPU will not perform two video memory access cycles in a row, providing the video memory access rate and the CPU clock rate are substantially the same. This assumption is valid because the Z80 performs two basic types of memory cycle, the opcode fetch cycle and the data read or write cycle. The opcode fetch cycle is four clock periods long, and the memory read or write cycle is three clock periods long. Therefore, the shortest possible interval is between two consecutive memory read or write cycles, which will be three cycle times apart.
  • Thus in accordance with this invention in such a system the contention mechanism operates on the basis that during the first of the two video memory cycles available to the VCL for each pixel the video data ready cycle will occur, unless the CPU wishes to perform a video memory cycle, in which case the video data ready cycle is deferred until the second of the cycles times in its interval. If a video memory read cycle has taken place in the first of these two cycles then a CPU cycle may freely take place in the second. Therefore both the video display mechanism and the CPU have what is effectively non-delayed access to the video memory.
  • An example of the invention will now be described in more detail by way of example with reference to the accompanying drawing, in which:
    • Figure 1 is a block diagram of the relevant part of a known .microprocessor video display system, and
    • Figure 2 is a block diagram of the corresponding part of a microprocessor video display system embodying the invention.
  • Both figures illustrate 8 pixel-mapped video memory 10 accessible both by a Z80 CPU 12 and by video control logic (VCL) 14 which supplies data on an output 16 to a video display device (not shown) incorporating a cathode ray tube screen.
  • In the known arrangement of Figure 1, when the VCL 14 calls for a data item from the memory 10 it also sends a WAIT command 18 to the CPU, if the CPU is also attempting to address the video memory, to render the CPU inactive for one video memory access cycle so as to avoid any danger of contention. This is logical enough because the display device has to be fed an uninterrupted supply of data otherwise the display will have gaps in it.
  • In accordance with this invention the VCL does not send a WAIT command to the CPU but, as shown in Figure 2, the VCL makes an enquiry MREQ of the CPU as to whether the CPU is attempting to addrerss video memory, and if it is the VCL defers its video memory read operation by one video memory cycle period. This goes contrary to the accepted practice because it introduces delay into the video data for the display.
  • However, because the video data can in fact be read from the video memory twice as fast as is necessary to supply the display, the present inventor has appreciated that a delay of just one video memory cycle period can be tolerated. Furthermore, because the video memory access rate is equal to the CPU clock rate, and each CPU operation cycle takes at least two CPU clock periods, only one of which will ever involve a video memory access, the CPU will never call for video memory access on two successive CPU clock periods.
  • Deferring of a VCL video memory read cycle will thus never arise on two successive video memory access cycles and the VCL will thus always be able to maintain delivery of video data at the required rate to the display.
  • In summary, therefore, the mechanism described and illustrated is used in a microcomputer application to allow the memory which holds the video display data to be read by both the microprocessor and the video display hardware. This it does in a manner which causes no reduction in the performance of the microprocessor, by interleaving the video read cycles between the microprocessor memory cycles in such a manner that a video read cycle may be shifted to allow the microprocessor immediate access to the memory. The standard mechanism to perform this would delay the microprocessor cycle, and therefore reduce the performance of the microprocessor. In the present system the microprocessor CPU can have the maximum possible performance as it is not degraded by the video control logic.

Claims (4)

1. A microprocessor video display system comprising a video memory, a CPU capable of accessing the video memory for one clock period during operation cycles each lasting two or more CPU clock periods, video control logic for accessing the video memory during selected video memory read cycles to provide data to a video display device, the video control logic being capable of accessing the video memory at a rate twice as fast as the rate at which data is required to be delivered to the video display device, and the video memory read cycle rate being substantially equal to the CPU clock rate, and in which when both the CPU and the video display device desire access to the video memory the operation of the video control logic is deferred by one video memory access period.
2. A microprocessor video display system according to claim 1, in which the CPU is comprised by a Z80 microprocessor.
3. A microprocessor video display system according to claim 1 or 2 in which the video memory is a pixel-mapped video memory.
4. A microprocessor video display system substantially as herein described with reference to and as shown in Figure 2 of the drawing.
EP87303096A 1986-04-10 1987-04-09 Microprocessor video display system Expired - Lifetime EP0241288B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB868608776A GB8608776D0 (en) 1986-04-10 1986-04-10 Video memory contention mechanism
GB8608776 1986-04-10

Publications (3)

Publication Number Publication Date
EP0241288A2 true EP0241288A2 (en) 1987-10-14
EP0241288A3 EP0241288A3 (en) 1989-02-08
EP0241288B1 EP0241288B1 (en) 1992-03-04

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EP87303096A Expired - Lifetime EP0241288B1 (en) 1986-04-10 1987-04-09 Microprocessor video display system

Country Status (4)

Country Link
EP (1) EP0241288B1 (en)
DE (1) DE3776940D1 (en)
ES (1) ES2029833T3 (en)
GB (2) GB8608776D0 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2612662A1 (en) * 1987-03-20 1988-09-23 Ibm MEMORY ARBITRATION FOR VIDEO SUBSYSTEMS
WO1989006032A1 (en) * 1987-12-21 1989-06-29 Ncr Corporation Timing control for display system
US5001652A (en) * 1987-03-20 1991-03-19 International Business Machines Corporation Memory arbitration for video subsystems
US5231383A (en) * 1990-12-20 1993-07-27 Ncr Corporation Videographics display system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263648A (en) * 1978-12-26 1981-04-21 Honeywell Information Systems Inc. Split system bus cycle for direct memory access of peripherals in a cathode ray tube display system
US4326202A (en) * 1979-03-26 1982-04-20 The President Of The Agency Of Industrial Science & Technology Image memory device
FR2509492A1 (en) * 1981-07-07 1983-01-14 Sony Corp MEMORY ACCESS CONTROL APPARATUS FOR MICROCALCULATOR
EP0094042A2 (en) * 1982-05-07 1983-11-16 Hitachi, Ltd. Data processing apparatus wherein a system bus is shared by two or more circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263648A (en) * 1978-12-26 1981-04-21 Honeywell Information Systems Inc. Split system bus cycle for direct memory access of peripherals in a cathode ray tube display system
US4326202A (en) * 1979-03-26 1982-04-20 The President Of The Agency Of Industrial Science & Technology Image memory device
FR2509492A1 (en) * 1981-07-07 1983-01-14 Sony Corp MEMORY ACCESS CONTROL APPARATUS FOR MICROCALCULATOR
EP0094042A2 (en) * 1982-05-07 1983-11-16 Hitachi, Ltd. Data processing apparatus wherein a system bus is shared by two or more circuits

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN *
ELECTRONIC DESIGN volume 27, no.16, 2nd August 1979, pages 90-93; C. Boisvert: "Simplify CRT-system design with transparent adressing - it comes on a controller chip" *
ELECTRONICS *
ELECTRONICS volume 52, no.14, 5th July 1979, pages 136-139; L. Trottier et al.: "Transparent memory ends conflicts over CRT control" *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2612662A1 (en) * 1987-03-20 1988-09-23 Ibm MEMORY ARBITRATION FOR VIDEO SUBSYSTEMS
EP0283565A2 (en) * 1987-03-20 1988-09-28 International Business Machines Corporation Computer system with video subsystem
EP0283565A3 (en) * 1987-03-20 1989-06-21 International Business Machines Corporation Computer system with video subsystem
BE1001181A3 (en) * 1987-03-20 1989-08-08 Ibm Memory arbitration subsystems video.
US5001652A (en) * 1987-03-20 1991-03-19 International Business Machines Corporation Memory arbitration for video subsystems
WO1989006032A1 (en) * 1987-12-21 1989-06-29 Ncr Corporation Timing control for display system
US5231383A (en) * 1990-12-20 1993-07-27 Ncr Corporation Videographics display system

Also Published As

Publication number Publication date
GB2189632A (en) 1987-10-28
DE3776940D1 (en) 1992-04-09
GB8708478D0 (en) 1987-05-13
GB2189632B (en) 1990-03-14
GB8608776D0 (en) 1986-05-14
EP0241288B1 (en) 1992-03-04
ES2029833T3 (en) 1992-10-01
EP0241288A3 (en) 1989-02-08

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