KR0165229B1 - Real time processing system having vsb interfacing graphic board - Google Patents

Abstract

The present invention relates to a real-time processing system, and more particularly, to a real-time processing system equipped with a graphics board of a computer system for factory automation, in which a plurality of CPU boards are commonly connected via a VME bus, wherein each CPU The board includes a VME bus interface unit and a VSB interface unit, and is connected to a graphics board through a VSB connected to the VSB interface unit to control a graphic display independently of the VME bus.

As described above, in the present invention, in the multi-master real-time processing system using the VME bus, the connection of the graphics board on the VME bus can be eliminated by adopting the VSB interfacing graphic board using VSB in the CPU board used as each multimaster. Therefore, there are problems such as bus traffic problem of VME bus, margin of slot expansion on VME bus, and improvement of graphic resolution in multi-tunnel.

Description

Real time processing system with VSB interfacing graphic board

1 is a schematic diagram of a real-time processing system using a conventional VME bus.

2 is a block diagram of a real-time processing system equipped with a graphics board using a VSB according to the present invention.

The present invention relates to a real time processing system, and more particularly, to a real time processing system equipped with a graphics board of an improved computer system for factory automation.

In general, the computer system for factory automation interconnects a main CPU and a plurality of target SUB-CPUs on a common bus for simultaneous operation and real time processing. In addition, several I / O boards and expansion memory boards are connected to the systems via a common bus. In this real-time processing system, each function is divided into modules, and each function is modularized by a board, and a common bus standard is standardized for interconnection between boards. Typical standard buses are the VME (Versa Module Europe) bus, PC bus and STD bus. VME buses have features such as compact size and reliability improvement by adopting DIN connector compared to Versa bus or STD bus. In addition, various sizes of data bus and address bus can be selected, data can be transferred by asynchronous interlock method, and high-performance system can be created by multi master function. (See Electronic Sciences 87. April)

However, because of the limited number of boards that can be connected to these superior VME buses, the system must be designed to meet the limited specifications. 1 is a schematic diagram of a VME bus interfacing real-time processing system. In Figure 1, if it is in CPU board or VME bus slot 1, it acts as a mod bus master and an interrupt handler. The VME bus master license for each CPU board is controlled by the Arbiter of the CPU board in slot 1. Also, bus adjustments are made when another CPU board receives an interrupt request from an I / O board while the bus is busy. If the VME bus can access up to eight boards in Figure 1, the system in Figure 1 can afford to add other functions, but the system's functionality may be degraded. In addition, since the interfacing method of the system is a first bus method, when using a multi-channel graphic board, bus traffic problems occur because eight boards commonly use VME buses by arbitration or priority among interrupt handlers. In the case of multi-channel graphic display using the VME bus, the graphic resolution is lower than that of the mono graphic display due to the characteristics of the VME bus.

An object of the present invention is to solve the problems of the bus traffic of the VME bus by connecting each graphics board using VSB (VME subbus) to each CPU board in the real-time processing system in order to solve the problems of the prior art as described above. It is to provide a graphics board using VSB that can prevent the degradation.

Another object of the present invention is to provide a real-time processing system equipped with a VSB interfacing graphics board.

In order to achieve the above object, the VSB interfacing graphic board of the present invention includes a VSB interface unit for interfacing a VSB bus and an internal local bus by a VSB interrupt request; A local control unit connected to the VSB interface unit through the internal local bus, and configured to decompose the high level command of the VSB master transferred through the VSB bus into a low-cost source; A graphic controller connected to the local controller through the internal local bus and controlling a video memory by decoding the low-level raw material transmitted through the internal local bus and controlling a display function; And a display transmission unit for forming video data supplied from the graphic controller as a video signal and issuing the video data to at least one monitor.

In order to achieve the above object, the real time processing system of the present invention is a real time processing system in which a plurality of CPU boards are commonly connected through a VME bus, wherein each CPU board includes a VME bus interface unit and a VSB interface unit. Independently from the bus is connected to the graphics board through a VSB connected to the VSB interface unit, characterized in that for controlling the graphics display.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 shows a real time processing system equipped with a VSB interfacing graphics board according to the present invention. In FIG. 13, the host CPU board 100 has a VME bus connected to the VME bus connector P1 and a graphics board 200 connected to the VSB connector P2 defined by the user through VSB. The CPU board is connected to each other via the VME bus and the graphics board 200 is connected to each CPU board through the VSB is different from the real-time system using a conventional VME bus. As described above, in the present invention, the graphics board is connected to each CPU board by using a VSB which is used under the user definition instead of using the VME bus, so that there is a bus traffic problem, a margin of slot expansion on the VME bus, the total throughput of the system ( There are advantages such as improved total throughput and graphics resolution when using multichannel.

The host CPU 100 includes an arithmetic processing unit consisting of a micro arithmetic processing unit 10, a buffer 11, a local resource controller (LRC) 12, a DURAT 13, a ROM 14, and a DRAM 15, and a VME. A VME interface section comprising a chip 16 and a sleeve decoder 17, and a VSB interface section consisting of a VSB chip 18 and a sleeve decoder 19 are provided. Such host CPU board 100 is commercialized and sold, such as Motorola's MVME167.

The graphics board 200 is roughly provided with a VSB interface 20, a local controller 30, a graphics controller 40, and a display transmission unit 50.

The VSB interface unit 20 includes a VSB interrupter 21, a VSB control status register 22, a VSB dual port RAM 23, and a buffer 24.

The local controller 30 includes a local CPU 31, a local control status register 32, a RAM 33, a ROM 34, and a graphics dual port memory 35.

The graphic controller 40 is composed of a graphic system processor 41 and a graphic display / graphic program memory 42.

The display transmission unit 50 includes a video oscillator 51, a video controller 52, a plurality of lookup tables 53, 54, and the like. Monitors M1 and M2 are connected to the plurality of lookup tables 53 and 54, respectively.

Graphic commands or data transmitted from the host CPU board 100 are stored in the VSB dual port memory 23, and the VSB interrupter 21 responds with seven VSB interrupts when the VSB interrupt handler responds with a valid interrupt confirmation cycle. Generates interrupts provided by levels and 16-bit vectors. The VSB control status register indicates the VSB control status as shown in Table 1 below.

The ROM 14 of the host CPU board 100 is addressed to decode a command read from the ROM 14 in the MPU 10 to perform a graphic operation. The interface control signal is supplied to the VSB chip 18 during the graphic operation, and the signal is transmitted to the graphic display I / O board 200 through the VSB. The transmitted signal is transmitted to the graphic controller 49 through the VSB interface 20 so that the graphic controller 40 performs graphic drawing. The local controller 30 converts the transmitted high-level commands into a low-level source and transmits them to the graphics controller 40 through the internal local bus and operates as a master to the graphics controller 40. The GSP of the graphic controller 40 has a graphic display, a host processor and a local memory bus interface, and the host interface determines whether the GSP operates independently or as a sleeve. When operating as a slave, the GSP's host interface transfers program data and graphic display lists between host memory and the GSP's local memory. The data transmission unit 50 displays the video of the color lookup tables 53 and 54 in response to the horizontal and vertical synchronization signals and the blanking signals generated by the video oscillator 51 and the graphic display list supplied through the video controller 52. Generate a signal. The generated video signal is supplied to and displayed on the monitors M1 and M2. The display transmission unit 50 can be expanded to 2 channels, 4 channels, 8 channels, etc. in a multi-channel manner.

As described above, in the present invention, the VSB interfacing graphics board is adopted as the CPU board used as each multimaster in the multi-master real system using the VME bus, thereby eliminating the connection of the graphics board on the VME bus. Therefore, there are some problems such as bus traffic problem of VME bus, margin of slot expansion on VME bus, and improvement of graphic resolution in multi channel.

Claims (5)

A real time processing system in which a plurality of CPU boards are commonly connected through a VME bus, wherein each CPU board includes a VME bus interface unit and a VSB interface unit, and is connected to a graphics board through a VSB connected to the VSB interface unit. Real-time processing system with VSB interfacing graphics board, which controls the graphics display independently of the VME bus. 2. The real-time processing system according to claim 1, wherein the graphic board is a multi-channel graphic display. The apparatus of claim 1, wherein the graphic board comprises: a VSB interface unit for interfacing the VSB bus and the internal local bus by a VSB interrupt request; A local control unit connected to the VSB interface unit through the internal local bus, and configured to decompose the high level command of the VSB master transferred through the VSB bus into a lower source; A graphic controller connected to the local controller through the internal local bus and controlling a video memory by decoding the low-level raw material transmitted through the internal local bus and controlling a display function; And a display transmission unit for forming the video data supplied from the graphic control unit as a video signal and issuing the video data to at least one or more monitors. The apparatus of claim 3, wherein the VSB interface unit comprises: a VSB interrupter for generating the VSB interrupt; A VSB control state register for storing information of the control state of the VSB; A VSB dual port memory for storing data on the VSB and an internal local bus; And a VSB buffer for directly connecting the VSB and an internal local bus. 4. The system of claim 3, wherein the local controller comprises: a microprocessor for controlling data traffic of the internal local bus; A nonvolatile memory for storing an operation program of the microprocessor; A volatile memory for storing data processed by the microprocessor; A local control status register for storing information for indicating a control status of an internal local bus under the control of the microprocessor; And a graphics dual port memory for storing graphics data on the graphics bus of the internal local bus and the graphics control unit.