GB2329985A - Shared memory control method - Google Patents

Abstract

A method of control for a memory block 11 accessed by both a processor and a graphic controller with a display buffer comprises allowing the graphic controller to access the memory block with a high priority request 21 when an amount of data in the display buffer is less than a first value, preventing the processor from accessing the memory block and, when the amount of data in the display buffer is greater than a second value, using a low priority request 22, allowing the processor to access the memory block.

Description

SHARED MEMORY CONTROL METHOD Background of the Invention The present invention relates, in general, to memory control techniques, and more particularly, to a method of controlling shared memory systems.

In the past, control techniques for mixing video signals and graphics signals together on a single video display generally utilize a system that is partitioned to have one memory dedicated to the video display and a separate memory dedicated to storing information such as graphics data that will be displayed on the video display.

Another technique utilizes a single large memory to store graphics information to be displayed by a graphics controller and also for text that is to be displayed by a microprocessor or CPU or other computer controller.

Typically, the microprocessor accesses the memory whenever needed to create display information and the graphics controller is inhibited from accessing the memory during all such accesses by the CPU. One problem with this implementation is that the graphics controller is blocked from accessing the memory while the CPU is utilizing the memory to obtain information. Generally, this results in flickering of the display or difficult to read data being displayed on the video display.

Accordingly, it is desirable to have a memory control technique that does not prevent the graphics controller from accessing the memory while the microprocessor or CPU is accessing the memory.

Brief Description of the Drawings FIG. 1 is a block diagram illustrating components of a video display system in accordance with the present invention; FIG. 2 is a block diagram illustrating components of a graphics controller portion of the video display system of FIG. 1 in accordance with the present invention; FIG. 3 is a block diagram illustrating a portion of a memory controller of the video display system of FIG. 2 in accordance with the present invention; and FIG.s 4-6 represent flow charts illustrating operational states of the video display system of FIG. 1 in accordance with the present invention.

Detailed Description of the Drawings FIG. 1 is a block diagram illustrating a video display system that includes a shared memory control system 10 that utilizes a single memory block or memory 11 to store display information for a video display unit 28. A processor 13 and a graphics controller 14 access memory 11 to obtain data to display on video display unit 28. Processor 13 often is within a cable control box 29 that is used to select channels of a cable television transmission system.

Processor 13 and graphics controller 14 typically access memory 11 through a memory controller 12. System 10 may also include a Motion Picture Expert Group (MPEG) controller 16 that also accesses memory 11 through controller 12 in order to retrieve television or other audio and visual display information to be displayed on video display unit 28. Typically, processor 13 supplies control and address information, such as a processor memory access request 19, to allow processor 13 to access memory 11. Data typically is thirty two bits wide and is provided back to processor 13 on processor data lines or processor data 24. Similarly, graphics controller 14 also provides control and address signals to controller 11, and receives graphics data signals or graphics data 26 from memory controller 12. Graphics controller 14 provides a graphics controller high priority request 21 and a graphics controller low priority request 22 to controller 12 to facilitate determining the access priority to memory 11. MPEG controller 16 also presents control information, including MPEG request 23 to memory controller 12 and receives data signals or MPEG data 27 from controller 12.

Because processor 13, graphics controller 14, and MPEG controller 16 must all access memory 11 in order to obtain data to display on video display unit 28, it is important to have a priority that determines which of processor 13 or controllers 14 and 16 access memory 11, and a control scheme for controlling such accesses. MPEG controller 16 generally has a large, at least two thousand byte, buffer and can also access up to two million bytes in order to provide immediate access and service for video display unit 28. Information in the memory of MPEG controller 16 typically is video information from a cable transmission system, thus, the number of memory accesses required by MPEG 16 is small compared to the number required by processor 13 and controller 14. Typically, processor 13 is utilized to control a cable television or other set top box that has a keyboard to interface with users. Information obtained by processor 13, such as channel number, etc., may be required to be displayed on unit 28 by graphics controller 14. Typically, graphics controller 14 obtains digital information from memory 11 and displays such digital information on video display unit 28. This type of information can be date, time, channel VCR programming information or other digital information to be displayed on video display unit 28. Consequently, it is important to determine which of processor 13, controller 14, or controller 16 has access to memory 11 when either of the other three devices also request access to memory 11.

Memory controller 12 accepts the control and address signals from processor 13, controller 14, and controller 16 and arbitrates between request for memory access to provide a suitable display on unit 28. Controller 12 then provides memory address, control signals, and timing signals 17 to memory 11 and receives memory data 18 back from memory 11. Controller 12 utilizes the control information to steer information from memory data 18 to data 24, 26, or 27 as appropriate. Memory controller 12 prioritizes the memory access request according to a priority from highest to lowest of graphics controller high priority request, MPEG request, processor request, and graphics controller low priority request. Other priority schemes could also be used.

FIG. 2 is a block diagram illustrating a portion of controller 14 shown in FIG. 1. Similar elements in FIG.

1 and FIG. 2 have the same element numbers. Controller 14 has a display buffer or asynchronous dual ported buffer memory 31 that can write data from memory 11 into memory 31 and, asynchronously to the write operation, read data from memory 31 in order to provide data to be displayed.

As will be seen hereinafter, a state machine 38 controls the operation of graphics controller 14. Typically, machine 38 is formed from random logic connected to perform the functions herein as would be well known by one skilled in the art.

Data read from memory 31 is coupled by pixel data lines 47 to a pixel generator 34 within a pixel control unit 32. Pixel generator 34 typically accesses memory 31 for every character to be displayed. Generator 34 converts the digital data from memory 31 to pixel elements and sends it to display unit 28 on a display output 35. Generator 34 also requests new data by asserting a display memory request 46. State machine 38 receives display memory requests on request 46, and provides control signals to enable reading data from memory 31. State machine 38 increments a read address register 36 to indicate the proper address to read data from and a write address register 37 to indicate addresses to write data into. State machine 38 provides control signals to memory 31 and to register 37 to ensure that the write operation is performed successfully.

The amount of data stored in memory 31 is used for determining the priority level of the request generated by controller 14. When the amount of data in memory 31 is less than a first value or a value stored in a low tide register 41, state machine 38 sets high priority request 21 to enable prioritizing graphics controller 14 accesses to memory 11 higher than accesses by processor 13(FIG. 1). When request 21 is asserted, controller 14 assesses memory 11 and processor 13 is prevented from accessing memory 11. When the amount of data stored in memory 31 is greater than a second value or a value stored in a high tide register 42, state machine 38 asserts low priority request line 22 so that memory controller 12 will allow accesses to memory 11 by processor 13 to have a higher priority than access requests by graphics controller 14. Thus, processor 13 can access memory 11 and controller 14 is prevented from initiating a memory access once processor 13 has asserted request 19. Controller 14 can also access memory 11 when processor 13 is not requesting a memory access such as when request 19 is not asserted.

This priority determination is made by comparing the value of a buffer contents register 39 to the value of high tide register 42 and low tide register 41. Buffer contents register 39 contains a value that indicates the amount of data currently stored in memory 31. Register 39 is incremented each time data is written into memory 31 and decremented each time data is read out of memory 31, thus, register 39 contains a value that indicates the amount of data currently stored in memory 31. A comparator 43 compares the value of the contents of register 39 to the value of the contents of high tide register 42. The output of comparator 43 is asserted when the value of buffer contents register 39 is greater than the value stored in high tide register 42. State machine 38 then disables high priority request 21 as will be seen hereinafter in a discussion of the operational flow of controller 14. Similarly, a comparator 44 compares the value of buffer contents register 39 to the value of low tide register 41. The output of comparator 44 is asserted when the value of buffer contents register 39 is less than the value stored in low tide register 41 to indicate that buffer memory 31 needs additional data to be displayed. State machine 38 then enables high priority request 21 as will be seen hereinafter in a discussion of the operational flow of controller 14.

When memory 31 has sufficient data to form a display on display unit 28, state machine 38 disables high priority request 21 and low priority request 22 for the purpose of suspending memory accesses. When the amount of data in memory 31 is not sufficient for a full display line, state machine 38 continues operation as will be seen herein after in the operation discussion. To determine if there is sufficient data for a full display line a maximum number of memory accesses that are required to fill buffer memory 31 is determined and stored in a maximum access register 51. The maximum number of accesses is determined by evaluating display unit 28 parameters such as the screen size which is stored in a screen size register 54, the color resolution which is stored in a color resolution register 56, and other display perimeters, not shown. A data arithmetic block 53 calculates the maximum number of accesses or maximum number of data words or memory 11 accesses required from the contents of registers 54 and 56. This value is stored in maximum access register 51. The total amount of data required for a display line is maintained in a total data register 52. State machine 38 increments total data register 52 each time data is written into memory 31 and decrements total data register 52 each time data is read out of memory 31. A buffer access comparator 59 compares the values in registers 51 and 52.

The output of comparator 59 is high if the value in maximum access register 51 equals the value stored in total data register 52.

When buffer memory 31 is full, state machine 38 disables high priority request 21 and low priority request 22 for preventing controller 14 from accessing memory 11. This condition can occur if the size of memory 31 is larger that the amount of data required to full a display screen. In order to determine if buffer memory 31 is full, the size of memory 31 is stored in a buffer size register 48. The value of register 48 is compared to the value in register 39 by a comparator 61.

An output of a comparator 61 is asserted when the value in register 39 is greater than the value in register 48.

When the amount of data in buffer memory 31 is below a minimum value, such as a value that would result in insufficient data for a full display line, machine 38 an asserts error signal 63 to provide an error condition.

Typically, signal 63 is provided to processor 13 in order to form an error signal. The error condition is detected by comparing the value in register 39 to the value in a minimum value register 49. The value in register 49 typically is hardwired or loaded during the manufacturing process.

FIG. 3 schematically illustrates a portion of memory controller 12. Similar elements in FIG.s 1, 2, and 3 have the same element numbers. Memory controller 12 has an arbitration unit 57 that receives high priority request 21 and low priority request 22 from controller 14, processor request 19 from processor 13, and MPEG request 23 from MPEG controller 16. Arbitration unit 57 receives the memory access requests and determines the priority of the request in order to generate memory access timing in a memory access generation and timing control block 58. Arbitration unit 57 also steers the data received from memory 11 to one of processor data 24, graphics data 26, or MPEG data 27. This steering typically is provided by multiplexing the information on memory data 18 to one of the three data lines based on which memory request has been given the highest priority.

FIG. 4 is a flow chart schematically illustrating a portion of the operation of controller 14. Similar elements in FIG.s 1, 2, 3, and 4 have the same element numbers. Controller 14 starts by delaying operation until the start of a video blanking interval. Typically controller 14 delays operation until the start of a horizontal blanking interval. During blanking, state machine 38 clears the value or the contents of total data register 52 and either in parallel or sequentially calculates the value to be stored in maximum access register 51. Because a new video display interval will follow the end of the blanking interval, state machine 38 asserts high priority request 21 in order to begin filling buffer memory 31 from memory 11 thereby preparing buffer memory 31 for the next video display interval.

For each write into buffer memory 31, state machine 38 increments the value in buffer contents register 39, increments the value in write address register 37, and increments the value stored in total data register 52.

After each write to buffer memory 31, if buffer memory 31 has sufficient data for forming a display line, state machine 38 negates requests 21 and 22, and delays until the start of the next blanking interval. To determine if buffer memory 31 has sufficient data, the value in total data register 52 is compared to the value of maximum access register 51. If the value in total data register 52 is equal to the value in maximum access register 51, buffer memory 31 has sufficient data for a display. If there is not enough data, controller 14 must continue operations.

Optionally, controller 14 can determine if buffer memory 31 is full so that machine 38 can continually monitor the status of buffer memory 31 until buffer memory 31 is not full and then continue operations. To determined if buffer memory 31 is full, the value of buffer contents register 39 is compared to the value in buffer size register 48. If buffer memory 31 is not full, state machine 38 continues to access memory 11.

To continue operations, machine 38 continues to assert high priority request 21 and continues to write data from memory 11 into buffer memory 31 until buffer memory 31 has sufficient data to change the priority of the access request to memory 11. The high priority memory requests continue to be performed until the amount of data in buffer memory 31 is greater than a first value or the value of the contents of high tide register 42.

This is determined by comparing the value of buffer contents register 39 to the value in high tide register 42.

If the buffer contents register value is higher than the high tide register value, then state machine 38 disables high priority request 21, asserts low priority request 22, and continues accessing memory 11, writing data into buffer memory 31 at a lower priority value, incrementing the value in buffer contents register 39, incrementing write address register 37, and incrementing total data register 52 for each access to memory 11.

If there is sufficient data stored in buffer memory 31 to display a complete line, controller 14 negates requests 21 and 22 to stop accesses to memory 11, and returns to the initial status of delaying until the beginning of the next blanking interval. This determination is performed by comparing the value in total data register 52 to the value in maximum access register 51. If the value in total data register 52 is less, state machine 38 continues operation and determines if buffer memory 31 is full.

If buffer memory 31 is full, machine 38 negates requests 21 and 22 to stop accesses to memory 11 until sufficient data is removed from buffer memory 31 by pixel generator 34 to cause buffer memory 31 to be not full.

This condition is detected by comparing the value in buffer contents register 39 to the value in buffer size register 48. If the value in buffer contents register 39 is less, then operation continues until the amount of data stored in buffer memory 31 is less than the value stored in low tide register 41. When the amount of data stored in buffer memory 31 is less than the second value or the value stored in low tide register 41, state machine 38 reasserts high priority request line 21 and continues making high priority memory accesses to memory 11 in order to store data in buffer memory 31.

In parallel with the accesses to memory 11 and write operations of data into buffer memory 31, pixel generator 34 reads data from memory 31 in order to form pixels to display on the video display. Pixel generator 34 requests data from memory 31 by pixel data request 46.

For each pixel request, state machine 38 enables data from memory 31 to pixel generator 34, increments the contents of read address register 36, and decrements the value of buffer contents register 39. This continues until all of the data in buffer memory 31 has been displayed. After all data is displayed, controller 14 returns to the state of waiting for the next blanking interval.

By now it should be appreciated that there has been provided a novel shared memory control method that uses a single memory block as a memory for at least a processor and a graphics controller. Prioritizing memory controller accesses to the memory block higher than processor accesses when the amount of data in the graphics controller is low ensures that the graphics controller has sufficient data for forming a display and does not produce flicker or interference in the display.

Prioritizing memory controller accesses to the memory block lower than processor accesses when the amount of data in the graphics controller is high ensures that the processor has sufficient time for forming a display and does not produce flicker or interference in the display.

Claims (12)

1. A shared memory control method comprising: using a single memory block as memory for both a processor and a graphic controller; and allowing the graphic controller to access the memory block and preventing the processor from accessing the memory block when an amount of data in a display buffer is less than a first value and allowing the processor to access the memory block when an amount of data in the display buffer is greater than a second value.

2. The method of claim 1 wherein the step of allowing the graphic controller to access the memory block includes allowing the processor to access the memory block and preventing an initiation of a memory access by the graphic controller during a memory access request by the processor when an amount of data in the display buffer is greater than the second value.

3. The method of claim 1 wherein allowing the graphic controller to access the memory block and preventing the processor from accessing the memory block when the amount of data in the display buffer is less than the first value includes: determining an amount of data in the display buffer; comparing the amount of data to a high tide value and allowing the processor to access the memory block if the amount of data is at least the high tide value; and comparing the amount of data to a low tide value and preventing the processor from accessing the memory block if the amount of data in the display buffer is no greater than the low tide value.

4. The method of claim 3 wherein comparing the amount of data includes: comparing a buffer contents register value to both a first register value and to a second register value; and asserting a graphics controller high priority request when the buffer contents register value is no greater than the first register value and deactivating the graphics controller high priority request when the buffer contents register value is at least the second register value, wherein asserting the graphics controller high priority request enables graphics controller access to the memory before processor access to the memory, and wherein deactivating the graphics controller high priority request value includes inhibiting graphics controller access to the memory while the processor has requested access to the memory.

5. The method of claim 1 further including suspending memory accesses by the graphic controller when the display buffer is full.

6. The method of claim 5 wherein suspending memory accesses by the graphics controller includes determining a number of memory accesses required to obtain data for the display buffer.

7. A graphics memory control method comprising: providing a graphics memory system having a memory coupled to a processor and to a graphics controller through a memory controller; providing a display buffer within the graphics controller; calculating in the graphics controller a number of memory access required to obtain a line of data for the display buffer; comparing a buffer contents register value to a first register value and to a second register value; and setting a graphics controller priority to a high value when the buffer contents register value is at least the first register value and to a low value when the buffer contents register value is at least the second register value, the high value enabling graphics controller access to the memory before processor access to the memory and the low value enabling graphics controller access to the memory after processor access to the memory.

8. The method of claim 7 further including repeating the steps of comparing the buffer contents register value to the first register value and to the second register value, and setting the graphics controller priority.

9. The method of claim 7 further including suspending memory access by the graphics controller when a total data register value reaches a maximum value.

10. The method of claim 7 further including comparing the buffer contents register value to a minimum value and forming an error signal to the processor when the buffer contents register value is not greater than the minimum value.

11. A shared memory control method substantially as hereinbefore described with reference to the accompanying drawings.

12. A graphics memory control method substantially as hereinbefore described with reference to the accompanying drawings.