DE3782335D1 - Speichersteuersystem. - Google Patents

Speichersteuersystem.

Info

Publication number
DE3782335D1
DE3782335D1 DE8787430014T DE3782335T DE3782335D1 DE 3782335 D1 DE3782335 D1 DE 3782335D1 DE 8787430014 T DE8787430014 T DE 8787430014T DE 3782335 T DE3782335 T DE 3782335T DE 3782335 D1 DE3782335 D1 DE 3782335D1
Authority
DE
Germany
Prior art keywords
processor
controller
request
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787430014T
Other languages
English (en)
Other versions
DE3782335T2 (de
Inventor
Alain Gach
Yves Hartmann
Michel Peyronnenc
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3782335D1 publication Critical patent/DE3782335D1/de
Application granted granted Critical
Publication of DE3782335T2 publication Critical patent/DE3782335T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
DE8787430014T 1987-04-22 1987-04-22 Speichersteuersystem. Expired - Fee Related DE3782335T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP87430014A EP0288649B1 (de) 1987-04-22 1987-04-22 Speichersteuersystem

Publications (2)

Publication Number Publication Date
DE3782335D1 true DE3782335D1 (de) 1992-11-26
DE3782335T2 DE3782335T2 (de) 1993-05-06

Family

ID=8198304

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787430014T Expired - Fee Related DE3782335T2 (de) 1987-04-22 1987-04-22 Speichersteuersystem.

Country Status (4)

Country Link
US (1) US4912632A (de)
EP (1) EP0288649B1 (de)
JP (1) JPH0724045B2 (de)
DE (1) DE3782335T2 (de)

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US5297242A (en) * 1989-12-15 1994-03-22 Nec Corporation DMA controller performing data transfer by 2-bus cycle transfer manner
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US5265218A (en) * 1992-05-19 1993-11-23 Sun Microsystems, Inc. Bus architecture for integrated data and video memory
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US5513374A (en) * 1993-09-27 1996-04-30 Hitachi America, Inc. On-chip interface and DMA controller with interrupt functions for digital signal processor
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US5535352A (en) * 1994-03-24 1996-07-09 Hewlett-Packard Company Access hints for input/output address translation mechanisms
US5524208A (en) * 1994-06-09 1996-06-04 Dell Usa, L.P. Method and apparatus for performing cache snoop testing using DMA cycles in a computer system
DE69529250T2 (de) * 1994-07-01 2003-10-30 Sun Microsystems Inc Rechnersystem mit einem multiplexierten Adressenbus und Pipeline-Schreiboperationen
FR2724243B1 (fr) * 1994-09-06 1997-08-14 Sgs Thomson Microelectronics Systeme de traitement multitaches
US5630094A (en) * 1995-01-20 1997-05-13 Intel Corporation Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
US6044441A (en) * 1995-09-29 2000-03-28 Intel Corporation Method and apparatus for encoding valid and invalid states in a cache with an invalid pattern
US5765195A (en) * 1995-12-08 1998-06-09 Ncr Corporation Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms
KR0160193B1 (ko) * 1995-12-30 1998-12-15 김광호 직접메모리접근 제어장치
US6122699A (en) * 1996-06-03 2000-09-19 Canon Kabushiki Kaisha Data processing apparatus with bus intervention means for controlling interconnection of plural busses
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US5901291A (en) * 1996-10-21 1999-05-04 International Business Machines Corporation Method and apparatus for maintaining message order in multi-user FIFO stacks
GB2331379A (en) * 1997-11-13 1999-05-19 Advanced Telecommunications Mo Controlling access to a shared memory by dual mapping
KR100287366B1 (ko) * 1997-11-24 2001-04-16 윤순조 엠피이지 방식을 이용한 휴대용 음향 재생장치 및 방법
US6108743A (en) * 1998-02-10 2000-08-22 Intel Corporation Technique for performing DMA including arbitration between a chained low priority DMA and high priority DMA occurring between two links in the chained low priority
JP3420091B2 (ja) 1998-11-30 2003-06-23 Ｎｅｃエレクトロニクス株式会社 マイクロプロセッサ
US6633926B1 (en) 1998-11-30 2003-10-14 Matsushita Electric Industrial Co., Ltd. DMA transfer device capable of high-speed consecutive access to pages in a memory
US6438628B1 (en) * 1999-05-28 2002-08-20 3Com Corporation System and method for data pacing
US6449665B1 (en) 1999-10-14 2002-09-10 Lexmark International, Inc. Means for reducing direct memory access
WO2001033374A1 (de) * 1999-11-02 2001-05-10 Siemens Aktiengesellschaft Burst-konzentrator zur effektiven unterstützung eines burstfähigen bussystems bei sequentiellen einzelwort-zugriffen
US6523098B1 (en) * 1999-12-22 2003-02-18 Intel Corporation Mechanism for efficient low priority write draining
US6785759B1 (en) 2000-05-10 2004-08-31 International Business Machines Corporation System and method for sharing I/O address translation caching across multiple host bridges
US20020029354A1 (en) * 2000-08-23 2002-03-07 Seagate Technology Llc Non-volatile write cache, in a disc drive, using an alternate power source
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
JP2003050774A (ja) * 2001-08-08 2003-02-21 Matsushita Electric Ind Co Ltd データ処理装置およびデータ転送方法
US7013357B2 (en) * 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Arbiter having programmable arbitration points for undefined length burst accesses and method
JP2005209163A (ja) * 2003-12-22 2005-08-04 Matsushita Electric Ind Co Ltd メモリシステム制御方法
US7424553B1 (en) 2004-04-15 2008-09-09 Xilinx, Inc. Method and apparatus for communicating data between a network transceiver and memory circuitry
US7225278B1 (en) 2004-04-15 2007-05-29 Xilinx, Inc. Method and apparatus for controlling direct access to memory circuitry
US7260688B1 (en) * 2004-04-15 2007-08-21 Xilinx, Inc. Method and apparatus for controlling access to memory circuitry
US7617338B2 (en) * 2005-02-03 2009-11-10 International Business Machines Corporation Memory with combined line and word access
US7720636B1 (en) 2007-02-14 2010-05-18 Xilinx, Inc. Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed
US7913022B1 (en) 2007-02-14 2011-03-22 Xilinx, Inc. Port interface modules (PIMs) in a multi-port memory controller (MPMC)
US8479124B1 (en) 2007-02-14 2013-07-02 Xilinx, Inc. Graphical user interface (GUI) including input files with information that determines representation of subsequent content displayed by the GUI
US7711907B1 (en) * 2007-02-14 2010-05-04 Xilinx, Inc. Self aligning state machine
US8392761B2 (en) * 2010-03-31 2013-03-05 Hewlett-Packard Development Company, L.P. Memory checkpointing using a co-located processor and service processor
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US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller

Also Published As

Publication number Publication date
JPS63269247A (ja) 1988-11-07
EP0288649B1 (de) 1992-10-21
JPH0724045B2 (ja) 1995-03-15
US4912632A (en) 1990-03-27
EP0288649A1 (de) 1988-11-02
DE3782335T2 (de) 1993-05-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee