Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
  • C30B25/02—Epitaxial-layer growth
  • C30B25/18—Epitaxial-layer growth characterised by the substrate
  • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/36—Carbides
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
  • C30B29/403—AIII-nitrides
  • C30B29/406—Gallium nitride
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
  • C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
  • C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02378—Silicon carbide
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02538—Group 13/15 materials
  • H01L21/0254—Nitrides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
  • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02656—Special treatments
  • H01L21/02658—Pretreatments
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

• the present invention relates to a method for manufacturing a substrate for the epitaxial growth of a layer of gallium nitride, as well as a method for manufacturing such a layer of gallium nitride and a method for manufacturing a transistor with high electron mobility (HEMT) in such a gallium nitride layer.
• HEMT high electron mobility
• III-N semiconductor materials in particular gallium nitride (GaN), aluminum gallium nitride (AIGaN) or gallium indium nitride (InGaN), appear particularly promising, especially for the formation high-power light-emitting diodes (LEDs) and high-frequency electronic devices, such as high-electron-mobility transistors (HEMTs) or other field-effect transistors (FETs).
• GaN gallium nitride
• AIGaN aluminum gallium nitride
• InGaN gallium indium nitride
• LEDs high-power light-emitting diodes
• HEMTs high-electron-mobility transistors
• FETs field-effect transistors
• III-N alloys are difficult to find in the form of large bulk substrates, they are generally formed by heteroepitaxy, i.e. by epitaxy on a substrate made of a different material.
• the choice of such a substrate takes into account in particular the difference in lattice parameter and the difference in thermal expansion coefficient between the material of the substrate and the III-N alloy. Indeed, the greater these differences, the greater the risks of formation in the III-N alloy layer of crystalline defects, such as dislocations, and the generation of significant mechanical stresses, likely to cause excessive deformations.
• III-N alloys The materials most frequently considered for the heteroepitaxy of III-N alloys are sapphire and silicon carbide (SiC).
• silicon carbide is particularly preferred for high-power electronic applications due to its thermal conductivity which is significantly higher than that of sapphire and which therefore makes it possible to dissipate more easily the thermal energy generated during the operation of the components.
• the aim is to use semi-insulating silicon carbide, i.e. typically having an electrical resistivity greater than or equal to 10 5 Q.cm, in order to minimize parasitic losses (generally called RF losses) in the substrate.
• silicon carbide i.e. typically having an electrical resistivity greater than or equal to 10 5 Q.cm
• this material is particularly expensive and is currently found only in the form of substrates of limited size. Silicon would drastically reduce manufacturing costs and provide access to large-size substrates, but structures of the III-N alloy type on silicon are penalized by RF losses and low heat dissipation.
• Composite structures such as SopSiC or SiCopSiC structures, have also been investigated [1] but do not prove to be entirely satisfactory. These structures respectively comprise a monocrystalline silicon layer or a monocrystalline SiC layer (intended to form a seed layer for the epitaxial growth of gallium nitride) on a polycrystalline SiC substrate.
• polycrystalline SiC is an inexpensive material, available in the form of large size substrates and providing good heat dissipation, these composite structures are penalized by the presence of a layer of silicon oxide at the interface between the single crystal silicon or SiC layer and the polycrystalline SiC substrate, which forms a thermal barrier impeding heat dissipation from the III-N alloy layer to the polycrystalline SiC substrate.
• An object of the invention is therefore to remedy the aforementioned drawbacks and in particular the limitations related to the size and cost of semi-insulating SiC substrates.
• the object of the invention is therefore to design a process for the manufacture of a substrate for the epitaxial growth of an III-N alloy based on gallium, in particular with a view to the formation of HEMT transistors or other electronic devices with high frequency and high power in which RF losses are minimized and heat dissipation is maximized.
• the invention proposes a process for manufacturing a substrate for the epitaxial growth of a layer of gallium nitride (GaN), of gallium nitride and aluminum (AIGaN) or of gallium nitride and indium (InGaN), comprising the following successive steps:
• high frequency is meant in the present text a frequency greater than 3 kHz.
• high power is meant in the present text a power density greater than 0.5 W/mm injected at the gate of the transistor.
• high electrical resistivity is meant in the present text an electrical resistivity greater than or equal to 100 Q.cm.
• Si-insulating SiC silicon carbide having an electrical resistivity greater than or equal to 10 5 ⁇ .cm.
• This process makes it possible to form a substrate based on silicon, diamond or ceramic, having a high electrical resistivity and a high thermal conductivity, at low cost and available in large dimensions, comprising a layer of semi-insulating SiC giving the structure end result of its good heat dissipation and RF loss limiting properties. Since the semi-insulating SiC layer is in direct contact with the receiver substrate, the structure does not contain any thermal barrier.
• a process which would consist in forming the layer of semi-insulating SiC by epitaxy directly on a silicon substrate of high electrical resistivity would lead to the formation of a large number of dislocations in the semi-insulating SiC due to the difference in lattice parameter between the silicon and silicon carbide.
• the method according to the invention makes it possible to use as seed for the subsequent growth of the III-N alloy based on gallium a layer of monocrystalline semi-insulating SiC of optimal quality because obtained by transfer of the donor substrate.
• the remainder of the semi-insulating SiC layer, namely the additional layer deposited on the transferred layer, which is located on the side of the transferred layer opposite to the III-N alloy layer, is not necessarily monocrystalline.
• the use of the first receiving substrate which fulfills the function of temporary support, makes it possible to orient the silicon face of the semi-insulating SiC in an optimal manner in the various stages of the process.
• the first receiver substrate and the donor substrate have a difference in coefficient of thermal expansion less than or equal to 3 ⁇ 10′ 6 K′ 1 ;
• the first receiver substrate is an SiC substrate having a crystalline quality lower than that of the donor substrate; - the thickness of the thin layer of monocrystalline semi-insulating SiC transferred onto the first receiver substrate has a thickness of less than 1 ⁇ m;
• the bonding layer is formed from a thermally stable material during the formation of the semi-insulating SiC layer and able to be removed from the interface between the transferred monocrystalline semi-insulating SiC layer and the first receiving substrate;
• the bonding layer is a layer of silicon nitride or gallium nitride
• the removal of at least part of the bonding layer comprises chemical etching, laser delamination and/or the application of mechanical stress;
• the additional layer of semi-insulating SiC is formed by simultaneous deposition of silicon, carbon and vanadium;
• the second receiver substrate is a silicon substrate having an electrical resistivity greater than or equal to 100 Q.cm;
• the additional layer of semi-insulating SiC has a thickness of between 1 and 5 ⁇ m;
• the second receiver substrate is a polycrystalline SiC substrate, a diamond substrate or a polycrystalline AlN substrate;
• the additional layer of semi-insulating SiC has a thickness less than or equal to 80 ⁇ m:
• the implantation of the ionic species is carried out through the silicon face of the donor substrate, and the silicon face of the donor substrate is bonded to the first receiver substrate, so that, after removal of the bonding layer, the silicon face of the transferred monocrystalline semi-insulating SiC layer is exposed;
• the method further comprises a step of recycling the portion of the donor substrate detached from the transferred layer, with a view to forming a new donor substrate.
• Another object of the invention relates to a process for manufacturing a layer of gallium-based III-N alloy on a substrate obtained by the process which has just been described.
• Said method comprises:
• the gallium nitride layer typically has a thickness of between 1 and 2 ⁇ m.
• Another object of the invention relates to a method of manufacturing a high electron mobility transistor (HEMT) in such a layer of III-N alloy.
• HEMT high electron mobility transistor
• Said method comprises:
• Figure 1 is a cross-sectional schematic view of a single-crystal semi-insulating SiC donor substrate
• FIG. 2 is a schematic sectional view of the donor substrate of FIG. 1 in which an embrittlement zone is formed by implantation of ionic species to delimit a thin layer to be transferred;
• Figure 3 is a schematic sectional view of a temporary support covered with a removable bonding layer
• Figure 4 is a schematic sectional view of the assembly of the temporary support of Figure 3 and the donor substrate of Figure 2 through the removable bonding layer;
• FIG. 5 is a schematic sectional view of the detachment of the donor substrate along the embrittlement zone to transfer the thin layer of monocrystalline semi-insulating SiC onto the temporary support;
• Figure 6 is a schematic sectional view of the thin layer of monocrystalline SiC transferred to the temporary support after polishing its free surface
• FIG. 7 is a schematic sectional view of the formation of an additional layer of semi-insulating SiC on the thin layer of transferred monocrystalline semi-insulating SiC;
• FIG. 8 is a schematic sectional view of the assembly of the structure of FIG. 7 and of a receiving substrate via the additional layer of semi-insulating SiC;
• FIG. 9 is a schematic cross-sectional view of the removal of the temporary support from the structure of FIG. 8 by chemical etching of the removable bonding layer so as to expose the silicon face of the transferred semi-insulating SiC layer;
• Figure 10 is a schematic sectional view of the formation by epitaxy of a GaN layer on the silicon face of the transferred semi-insulating SiC layer;
• Figure 11 is a schematic sectional view of the formation of a heterojunction by epitaxy of a layer of an III-N alloy different from GaN on the GaN layer.
• the invention proposes a process for manufacturing substrates for the epitaxial growth of binary or ternary III-N alloys based on gallium.
• Said alloys include gallium nitride (GaN), aluminum gallium nitride (Al x Gai- x N, where 0 ⁇ x ⁇ 1, hereinafter abbreviated as AIGaN) and gallium nitride and indium (In x Gal x N, where 0 ⁇ x ⁇ 1, hereinafter abbreviated as InGaN).
• the process uses a monocrystalline semi-insulating silicon carbide (SiC) donor substrate, of which a thin layer, transferred by the Smart CutTM process onto a first receiver substrate, will serve as a seed for the growth of an additional layer of semi-insulating SiC.
• SiC silicon carbide
• -insulating not necessarily monocrystalline.
• the additional layer of semi-insulating SiC will make it possible to provide the final structure with a sufficiently large thickness of semi-insulating SiC to significantly reduce RF losses, for an optimized cost insofar as only the portion of said layer intended for the growth of the GaN layer is monocrystalline.
• the donor substrate may be a bulk single crystal semi-insulating SiC substrate.
• the donor substrate may be a composite substrate, comprising a surface layer of monocrystalline semi-insulating SiC and at least one other layer of another material.
• the monocrystalline semi-insulating SiC layer has a thickness greater than or equal to 0.5 ⁇ m.
• crystal forms also called polytypes
• the most common are the 4H, 6H and 3C forms.
• the monocrystalline semi-insulating silicon carbide is chosen from the 4H and 6H polytypes, but all the polytypes can be envisaged to implement the present invention.
• a solid substrate 10 of monocrystalline semi-insulating SiC has been shown. In a manner known per se, as illustrated in FIG. 1, such a substrate has a silicon 10-Si face and a carbon 10-C face.
• GaN epitaxy processes are mainly implemented on the silicon face of semi-insulating SiC. However, it is not excluded to succeed in growing GaN on the carbon face of the semi-insulating SiC.
• the orientation of the donor substrate (silicon face/carbon face) during the implementation of the process is chosen according to the face of the semi-insulating SiC intended for the growth of the GaN layer.
• an implantation of ionic species is carried out in the donor substrate 10, so as to form a zone of weakness 12 delimiting a thin layer 11 of monocrystalline semi-insulating SiC.
• the implanted species typically include hydrogen and/or helium. A person skilled in the art is able to define the energy and the implantation dose required.
• the implantation is carried out in the superficial layer of monocrystalline semi-insulating SiC of said substrate.
• the implantation of the ionic species is carried out through the silicon 10-Si face of the donor substrate.
• this orientation of the donor substrate makes it possible to obtain, on the surface of the final substrate intended for the growth of the GaN layer, the silicon face of the semi-insulating SiC, which is more favorable.
• the implantation of the ionic species must be carried out through the 10-C carbon face of the donor substrate.
• the thin layer 11 of monocrystalline semi-insulating SiC has a thickness of less than 1 ⁇ m.
• a thickness is indeed accessible on an industrial scale with the Smart CutTM process.
• the implantation devices available in industrial manufacturing lines make it possible to achieve such an implantation depth.
• a first receiver substrate 20 is also provided.
• the main function of said first receiver substrate is to temporarily support the layer 11 of monocrystalline semi-insulating SiC between its transfer from the donor substrate and the growth of the additional layer of semi-insulating SiC on the layer of monocrystalline semi-insulating SiC.
• the first receiving substrate is chosen to have a coefficient of thermal expansion substantially equal to that of the semi-insulating SiC, so as not to induce stresses or deformations during the formation of the additional layer of semi-insulating SiC .
• the first receiver substrate and the donor substrate have a difference in coefficient of thermal expansion less than or equal to 3 ⁇ 10′ 6 K' 1 in absolute value.
• the first receiving substrate is also made of SiC so as to minimize the difference in coefficient of thermal expansion.
• the first receiver substrate 20 is an SiC substrate having a crystalline quality lower than that of the donor substrate.
• the first receiver substrate can be a polycrystalline SiC substrate, or else a monocrystalline SiC substrate but which can include dislocations of all types (unlike the monocrystalline semi-insulating SiC of the donor substrate which is chosen of excellent crystal quality to ensure the quality of the GaN epitaxial layer).
• Such a substrate of lower crystalline quality has the advantage of being less expensive than a substrate of the same quality as the donor substrate, while being perfectly suited to the temporary support function.
• the donor substrate 10 comprising the thin layer 11 of monocrystalline SiC is bonded to the first receiver substrate 20.
• a bonding layer 21 is formed at the interface between said substrates.
• the bonding layer 21 is formed on the first receiver substrate 20, but, in other embodiments not illustrated, the bonding layer can be formed on the donor substrate (on the side of the thin layer 11 ), or partly on the donor substrate and partly on the first recipient substrate.
• the bonding layer is formed in a thermally stable material during the subsequent formation of the additional layer of semi-insulating SiC on the thin layer 11.
• the epitaxy of 4H or 6H-SiC being carried out at a temperature typically greater than 1500°C, the material of the bonding layer is chosen so as not to degrade or dissociate at such a temperature if the additional layer of semi-insulating SiC is formed by epitaxy.
• the additional layer of semi-insulating SiC it is not imperative to resort to an epitaxy process.
• a faster deposition process and at a lower temperature, resulting in an additional polycrystalline layer or layer comprising dislocations, can therefore be implemented, which makes it possible to reduce the duration and cost of manufacturing the substrate.
• the material of the bonding layer is capable of being removed from the interface between the transferred monocrystalline semi-insulating SiC layer and the first receiving substrate 20, for example by means of selective etching, possibly assisted by plasma .
• the bonding layer is a layer of silicon nitride or gallium nitride. The thickness of said layer is typically between 10 nm and a few hundred nanometers.
• the donor substrate is detached along the zone of weakness 12.
• the detachment can be caused by a heat treatment, a mechanical action, or a combination of these means. This detachment has the effect of transferring the thin layer 11 of monocrystalline semi-insulating SiC onto the first receiver substrate 20.
• the remainder 10' of the donor substrate can optionally be recycled for another use.
• the free face of the transferred monocrystalline semi-insulating SiC layer 11 is the carbon face 11-C (the silicon face 11 -Si being on the side of the paste interface).
• This face is polished, for example by chemical-mechanical polishing (CMP, acronym of the Anglo-Saxon term "Chemical Mechanical Polishing") to remove the defects linked to the implantation of the ionic species and to reduce the roughness of Layer 11.
• CMP chemical-mechanical polishing
• an additional layer 13 of semi-insulating SiC is formed on the thin layer 11 of monocrystalline semi-insulating SiC.
• the polytype of the SiC of the additional layer is advantageously identical to that of the transferred layer.
• the additional layer 13 is not necessarily monocrystalline but can be polycrystalline, which makes it possible to implement deposition at a lower temperature than epitaxy. In any event, given the small difference in thermal expansion coefficient between the material of the first receiving substrate and the SiC, the mechanical stresses generated in the stack are minimized.
• the SiC layer is doped with vanadium during its epitaxial growth.
• silicon, carbon and vanadium are simultaneously deposited, using suitable precursors in an epitaxy frame.
• the additional layer of semi-insulating SiC advantageously has a thickness greater than 1 ⁇ m, so as to contribute significantly to heat dissipation within the final structure. This thickness is higher than the thickness directly accessible by the Smart CutTM process with industrially available equipment. Moreover, this additional layer can be formed by a less expensive process than the layer transferred from the donor substrate.
• the process consisting in transferring a layer of monocrystalline semi-insulating SiC with a thickness of less than 1 ⁇ m then in forming a layer of semi-insulating SiC not necessarily monocrystalline by epitaxy on said transferred layer makes it possible to circumvent the technical limits of the equipment of implantation available industrially for the implementation of the Smart CutTM process and to reduce the cost of the manufacturing process.
• a second receiver substrate 40 which has a high electrical resistivity, and it is bonded to the layer 13 of semi-insulating SiC.
• the second receiver substrate can be a silicon substrate having an electrical resistivity greater than or equal to 100 ⁇ .cm, or, preferably, a polycrystalline SiC substrate, a polycrystalline AlN substrate or a diamond substrate.
• the thickness of the additional layer 13 of semi-insulating SiC can be adapted.
• the additional layer 13 of semi-insulating SiC will advantageously have a thickness of between 1 and 5 ⁇ m.
• the second receiver substrate is a polycrystalline SIC, diamond or polycrystalline AlN substrate
• the bonding layer 21 is removed, so as to detach the first receiving substrate from the rest of the structure. During this removal, the layer 21 must be sufficiently damaged to allow a dissociation of the structure. Any suitable means can be used. For example, but in a non-limiting manner, the removal of the bonding layer can be achieved by chemical etching, laser delamination and/or the application of mechanical stress.
• the exposed face of the transferred layer 11 is the silicon face of the monocrystalline semi-insulating SiC, which is favorable to the epitaxial growth of GaN.
• a suitable substrate for the epitaxial growth of III-N alloys was thus formed.
• a layer 50 of GaN (or, as mentioned above, of AlGaN or InGaN) is grown on the free face of layer 11 of semi-insulating SiC.
• the thickness of layer 50 is typically between 1 and 2 ⁇ m.
• a heterojunction is formed by growing by epitaxy, on layer 50, a layer 60 of an III-N alloy different from that of layer 50.
• transistors in particular HEMT transistors, from this heterojunction, by methods known to those skilled in the art, the channel of the transistor being formed at the level of the heterojunction, and the source, the drain and the gate of the transistor being formed on the channel.
• the structure thus obtained is particularly advantageous in that it comprises a relatively thick layer of semi-insulating SiC, of which only a part serving as a seed for the epitaxial growth of the III-N alloy layer must be monocrystalline, and which d on the other hand provides good heat dissipation and limitation of RF losses. Furthermore, the second receiver substrate, which supports the semi-insulating SiC layer, is directly in contact with said layer, so that the structure does not include a thermal barrier. Thus, a HEMT transistor or other high-frequency, high-power electronic device formed in an 11-N alloy layer epitaxially formed on such a structure exhibits minimized RF losses and maximized heat dissipation.

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