EP4220733A1 - Halbleiterzellstruktur, igbt-zellstruktur und herstellungsverfahren dafür und halbleiterstruktur - Google Patents

Halbleiterzellstruktur, igbt-zellstruktur und herstellungsverfahren dafür und halbleiterstruktur Download PDF

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EP4220733A1
EP4220733A1 EP21871579.5A EP21871579A EP4220733A1 EP 4220733 A1 EP4220733 A1 EP 4220733A1 EP 21871579 A EP21871579 A EP 21871579A EP 4220733 A1 EP4220733 A1 EP 4220733A1
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Prior art keywords
trench
layer
oxide layer
polysilicon
region
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English (en)
French (fr)
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EP4220733A4 (de
Inventor
Baowei HUANG
Haiping Wu
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BYD Semiconductor Co Ltd
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BYD Semiconductor Co Ltd
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Publication of EP4220733A1 publication Critical patent/EP4220733A1/de
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/66234—Bipolar junction transistors [BJT]
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    • H01L29/66333—Vertical insulated gate bipolar transistors
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Definitions

  • the present disclosure generally relates to the field of semiconductor manufacturing, and more specifically, to a semiconductor cell structure, an insulated gate bipolar transistor (IGBT) cell structure, a semiconductor structure, and a method for manufacturing an IGBT cell structure.
  • IGBT insulated gate bipolar transistor
  • New semiconductor power devices such as an insulated gate bipolar transistor (IGBT)
  • IGBT insulated gate bipolar transistor
  • advantages such as a low conduction loss, a high input impedance, a simple driving circuit, a low driving power, and a high turn-on speed.
  • the IGBT is developing in a low-conduction-loss and low-switching-loss direction.
  • the IGBT experienced a PT-NPT-FS development in terms of a vertical structure, and developed from a planar gate to a trench gate structure in terms of a surface structure, which greatly reduces the conduction loss and the switching loss of the IGBT.
  • the introduction of a floating P region greatly reduces a conduction drop of the trench IGBT, improves a carrier storage effect, and greatly relieves the contradiction between a forward conduction drop Vce and a turn-off time toff of a device compared with a conventional trench IGBT.
  • the Miller capacitance of the existing floating P-type trench IGBT is very large.
  • the Miller capacitance adds an additional displacement current to the gate based on a gate driving current.
  • a large Miller capacitance leads to a large displacement current in the gate of the device, which affects a voltage of the gate.
  • a large Miller capacitance leads to problems such as a large voltage change rate dv/dt, a high current peak, and electromagnetic compatibility (EMC)during reverse recovery of a freewheeling diode used in collaboration.
  • EMC electromagnetic compatibility
  • a large Miller capacitance increases the turn-on time and the turn-off time of the device, resulting in large turn-on and turn-off losses of the device.
  • a semiconductor cell structure an insulated gate bipolar transistor (IGBT) cell structure, a semiconductor structure, and a method for manufacturing an IGBT cell structure are desired.
  • IGBT insulated gate bipolar transistor
  • an embodiment of the present disclosure provides an IGBT cell structure, including an N-type drift layer, an N-type termination layer, a P-type collector layer, and a collector metal layer stacked in sequence.
  • the IGBT cell structure On a side of the N-type drift layer facing away from the P-type collector layer and in the N-type drift layer, the IGBT cell structure includes: two first trenches spaced apart from each other, a trench-shaped insulating oxide layer formed on an inner wall of each of the first trenches, a polysilicon electrode located in the trench-shaped insulating oxide layer, a second trench located in the first trench, a trench-shaped gate oxide layer located in the second trench, a polysilicon gate located in the trench-shaped gate oxide layer, a P well region located between the first trenches, and two floating P regions spaced apart from each other.
  • the trench-shaped insulating oxide layer and the polysilicon gate in the first trench are both adjacently connected with the second trench in the first trench.
  • a depth of each of the floating P regions does not exceed a depth of the first trench.
  • the floating P region is isolated from the P well region through the trench-shaped insulating oxide layer.
  • the trench-shaped gate oxide layer is isolated from the trench-shaped insulating oxide layer through the polysilicon electrode.
  • the gate oxide layers in the two trench-shaped insulating oxide layers are adjacently connected with the P well region.
  • the IGBT cell structure further includes an N+ emitter layer.
  • the N+ emitter layer is formed on sides of the floating P region and the P well region facing away from the P-type collector layer.
  • a P+ region connected with the N+ emitter layer is arranged in the P well region.
  • the IGBT cell structure further includes an insulating dielectric isolation layer and an emitter metal layer arranged in sequence in a direction of being close to the P-type collector layer to being far away from the P-type collector layer.
  • the insulating dielectric isolation layer covers the N+ emitter layer, the trench-shaped insulating oxide layer, the polysilicon electrode, the trench-shaped gate oxide layer, and the polysilicon gate.
  • the insulating dielectric isolation layer has an opening from which the polysilicon electrode and the P+ region are exposed.
  • the emitter metal layer covers the insulating dielectric isolation layer and fills the opening.
  • the depth of the first trench ranges from 4 ⁇ m to 8 ⁇ m; and a depth of the second trench ranges from 2 ⁇ m to 5 ⁇ m.
  • a width of the second trench is less than a width of the first trench by a range of 0.6 ⁇ m to 1.0 ⁇ m; the width of the first trench ranges from 1.4 ⁇ m to 2.2 ⁇ m; and the width of the second trench ranges from 0.8 ⁇ m to 1.2 ⁇ m.
  • At least one of the following doping concentration conditions is satisfied:
  • the present disclosure provides a semiconductor structure, including a plurality of IGBT cell structures in parallel described above.
  • a depth of the floating P region of the IGBT cell structure is the same as a depth of the first trench, and floating P regions of two adjacent IGBT cell structures are connected to form a floating P region.
  • the present disclosure provides a semiconductor structure, including a plurality of IGBT cell structures in parallel described above.
  • At least one intermediate trench is further arranged in the N-type drift layer; a trench insulating oxide layer is arranged in the intermediate trench; an intermediate polysilicon layer is arranged in the trench insulating oxide layer; the intermediate trench is formed on the same layer as the first trench; the trench insulating oxide layer is formed on the same layer as the trench-shaped insulating oxide layer; and the intermediate polysilicon layer is formed on the same layer as the polysilicon electrode.
  • At least two intermediate trenches are arranged in the N-type drift layer; an intermediate P floating region is arranged between the two intermediate trenches; and the intermediate P floating region is formed on the same layer as the floating P region.
  • the present disclosure provides a method for manufacturing an IGBT cell structure, including:
  • the manufacturing method further includes:
  • the forming two first trenches spaced apart from each other in the N-type substrate through deposition, photoetching, and etching processes, forming a trench-shaped insulating oxide layer in each of the first trenches, and depositing a polysilicon in the trench-shaped insulating oxide layer to form a polysilicon electrode region include:
  • the forming a second trench in the first trench through deposition, photoetching, and etching processes, forming a trench-shaped gate oxide layer in the second trench, and depositing polysilicon in the trench-shaped gate oxide layer to form a polysilicon gate include:
  • the present disclosure provides a semiconductor cell structure, including an N-type drift layer, an N-type termination layer, a P-type collector layer, and a collector metal layer stacked in sequence.
  • the semiconductor cell structure On a side of the N-type drift layer facing away from the P-type collector layer and in the N-type drift layer, the semiconductor cell structure includes: two first trenches spaced apart from each other, a trench-shaped insulating oxide layer formed on an inner wall of each of the first trenches, a polysilicon electrode located in the trench-shaped insulating oxide layer, a second trench formed on the inner wall of the first trench, a trench-shaped gate oxide layer located in the second trench, a polysilicon gate located in the trench-shaped gate oxide layer, a P well region located between the first trenches, and two floating P regions spaced apart from each other.
  • the trench-shaped insulating oxide layer and the polysilicon gate in the first trench are both adjacently connected with the second trench in the first trench; the trench-shaped gate oxide layer is isolated from the trench-shaped insulating oxide layer through the polysilicon electrode. A depth of each of the floating P regions does not exceed a depth of the first trench. The floating P region is isolated from the P well region through the trench-shaped insulating oxide layer. The gate oxide layers in the two second trenches are adjacently connected with the P well region.
  • the first trench is a dummy trench (that is, a pseudo trench)
  • the second trench is a gate trench
  • the two second trenches are adjacently connected with the P well region. Since a majority of the second trench falls in the first trench, and only a small part of the second trench is adjacently connected with the N-type drift layer to form a Miller capacitance, the semiconductor cell structure has a very small Miller capacitance, which improves the turn-on efficiency of the device and reduce the switching loss of the device.
  • An embodiment of the present disclosure provides a semiconductor cell structure, including an N-type drift layer, an N-type termination layer, a P-type collector layer, and a collector metal layer stacked in sequence.
  • the semiconductor cell structure On a side of the N-type drift layer facing away from the P-type collector layer and in the N-type drift layer, the semiconductor cell structure includes: two first trenches spaced apart from each other, a trench-shaped insulating oxide layer formed on an inner wall of each of the first trenches, a polysilicon electrode located in the trench-shaped insulating oxide layer, a second trench formed on the inner wall of the first trench, a trench-shaped gate oxide layer located in the second trench, a polysilicon gate located in the trench-shaped gate oxide layer, a P well region located between the first trenches, and two floating P regions spaced apart from each other.
  • the trench-shaped insulating oxide layer and the polysilicon gate in the first trench are both adjacently connected with the second trench in the first trench.
  • the trench-shaped gate oxide layer is isolated from the trench-shaped insulating oxide layer through the polysilicon electrode. A depth of each of the floating P regions does not exceed a depth of the first trench.
  • the floating P region is isolated from the P well region through the trench-shaped insulating oxide layer.
  • the gate oxide layers in the two second trenches are adjacently connected with the P well region.
  • the semiconductor cell structure may be an IGBT semiconductor cell structure, or may be a metal oxide semiconductor (MOS) semiconductor cell structure.
  • MOS metal oxide semiconductor
  • a main difference between the MOS semiconductor cell structure and the IGBT semiconductor cell structure is a back side of a substrate.
  • the back side of the substrate of the IGBT semiconductor cell structure has an additional P-type substrate compared with the back side of the substrate of the MOS semiconductor cell structure.
  • Front structures of the IGBT semiconductor cell structure and the MOS semiconductor cell structure are the same.
  • the semiconductor cell structure in this embodiment of the present disclosure may be the IGBT semiconductor cell structure or the MOS semiconductor cell structure.
  • the semiconductor cell structure is the IGBT semiconductor cell structure, for example.
  • the present disclosure provides a semiconductor cell structure, an IGBT cell structure, a semiconductor structure, and a method for manufacturing an IGBT cell structure.
  • an embodiment of the present disclosure provides an IGBT cell structure, including an N-type drift layer 101, an N-type termination layer 116, a P-type collector layer 117, and a collector metal layer 118 stacked in sequence.
  • the IGBT cell structure On a side of the N-type drift layer 101 facing away from the P-type collector layer 117 and in the N-type drift layer 101, the IGBT cell structure includes: two first trenches 102 spaced apart from each other, a trench-shaped insulating oxide layer 103 formed on an inner wall of each of the first trenches 102, a polysilicon electrode 104 located in the trench-shaped insulating oxide layer 103, a second trench 105 located on the inner wall of the first trench 102, a trench-shaped gate oxide layer 106 located on an inner wall of the second trench 105, a polysilicon gate 107 located in the trench-shaped gate oxide layer 106, a P well region 108 located between the first trenches 102, two floating P regions 109 spaced apart from each other, and an N+ emitter layer 110.
  • the N+ emitter layer 110 is formed on sides of the floating P region 109 and the P well region 108 facing away from the P-type collector layer 117.
  • the IGBT cell structure further includes an insulating dielectric isolation layer 112 and an emitter metal layer 113 arranged in sequence in a direction of being close to the P-type collector layer 117 to being far away from the P-type collector layer 117.
  • the insulating dielectric isolation layer 112 covers the N+ emitter layer 110, the trench-shaped insulating oxide layer 103, the polysilicon electrode 104, the trench-shaped gate oxide layer 106, and the polysilicon gate 107.
  • the insulating dielectric isolation layer 112 has an opening 114 from which the polysilicon electrode 104 and the P+ region 111 are exposed.
  • the emitter metal layer 113 covers the insulating dielectric isolation layer 112 and fills the opening 114.
  • the trench-shaped insulating oxide layer 103 and the polysilicon electrode 104 in the first trench are both adjacently connected with the second trench in the first trench.
  • the trench-shaped gate oxide layer 106 is isolated from the trench-shaped insulating oxide layer 103 through the polysilicon electrode 104.
  • a depth of each of the floating P regions 109 does not exceed a depth of the first trench 102.
  • the floating P region 109 is isolated from the P well region 108 through the trench-shaped insulating oxide layer 103.
  • the gate oxide layers 106 in the two second trenches 105 are adjacently connected with the P well region 108.
  • the first trench is a dummy trench (a pseudo trench)
  • the second trench is a gate trench
  • the P well region is located between the two second trenches (that is, two gate trenches). Since the second trench is located in the first trench, and only a small part of the second trench is adjacently connected with the N-type drift layer to form a Miller capacitance, for example, a length of the contact position between the second trench and the N-type drift layer is 200 nm, or even 100 nm, the IGBT cell structure has a very small Miller capacitance, which improves the turn-on efficiency of the device and reduce the switching loss of the device.
  • the capacitance Cgc is also referred to as the Miller capacitance.
  • the polysilicon electrode is a polysilicon emitter, a region inside the second trench is a gate region, a surrounding region of the second trench is substantially adjacently connected to the emitter.
  • the IGBT cell structure provided in this embodiment has a large input capacitance, which can further reduce the impact of a displacement current caused by a feedback capacitance on a voltage of the gate, and the gate of the device is not easily affected by a current change.
  • a semiconductor material includes polysilicon, monocrystalline silicon, silicon carbide, gallium nitride, zinc oxide, or the like.
  • the depth of the first trench 102 ranges from 4 ⁇ m to 8 ⁇ m, and a depth of the second trench 105 ranges from 2 ⁇ m to 5 ⁇ m.
  • the first trench is deeper than the second trench.
  • each first trench has the second trench formed therein, the two second trenches are adjacently connected to the P well region, and the second trench falls in the first trench, which ensures that only a small contact area is formed between the gate region and the N-type drift region, so that the device has a small Miller capacitance.
  • the first trench is in contact with the N-type drift region, the first trench is made deeper, and the floating P region is formed on an outer side of the first trench.
  • the first trench and the floating P region can reduce an electric field at a bottom of the trench and improve a reverse voltage withstanding capability of the device.
  • the first trench and the floating P region enable a surface of the device to store a large number of minority carriers, which reduces a conduction drop of the device.
  • a width of the second trench 105 is less than a width of the first trench 102 by a range of 0.6 ⁇ m to 1.0 ⁇ m, the width of the first trench 102 ranges from 1.4 ⁇ m to 2.2 ⁇ m, and the width of the second trench 105 ranges from 0.8 ⁇ m to 1.2 ⁇ m, to ensure that the first trench can surround the second trench.
  • a doping concentration of the P well region 108 ranges from 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 19 cm -3 ;
  • an embodiment of the present disclosure provides a semiconductor structure, including a plurality of IGBT cell structures shown in FIG. 1 in parallel.
  • a depth of the floating P region of the IGBT cell structure is the same as a depth of the first trench 102, and floating P regions 109 of two adjacent IGBT cell structures are connected to form a floating P region 201.
  • a depth of the floating P region 201 in the semiconductor structure provided in this embodiment is the same as or approximates the depth of the first trench.
  • the floating P region can withstand a main electric field, so that the electric field does not concentrate at the bottom of the first trench, which improves the voltage withstand capability of the device, and prevents the device from being easily damaged by an overvoltage during application.
  • an embodiment of the present disclosure provides another semiconductor structure, including a plurality of IGBT cell structures shown in FIG. 1 in parallel.
  • At least one intermediate trench 301 is further arranged in the N-type drift layer 101; a trench insulating oxide layer 302 is arranged in the intermediate trench 301; an intermediate polysilicon layer 303 is arranged in the trench insulating oxide layer 302; the intermediate trench 301 is formed on the same layer as the first trench 102; the trench insulating oxide layer 302 is formed on the same layer as the trench-shaped insulating oxide layer 103; and the intermediate polysilicon layer 303 is formed on the same layer as the polysilicon electrode 104; the insulating dielectric isolation layer 112 further covers the intermediate trench 301, the trench insulating oxide layer 302, and the intermediate polysilicon layer 303; the insulating dielectric isolation layer 112 further has an opening 304 from which the intermediate polysilicon layer 303 is exposed, and the N+ emitter metal layer 113 fills the opening 304.
  • At least two intermediate trenches 301 are further arranged in the N-type drift layer 101; an intermediate P floating region is arranged between the two intermediate trenches 301; the intermediate P floating region is formed on the same layer as the floating P region 109; and the N+ emitter layer 110 is connected with the intermediate P floating region.
  • At least one trench portion is arranged between adjacent IGBT cell structures.
  • a depth and a width of the trench portion are the same as those of the first trench.
  • the trench portion and the first trench are implemented simultaneously, which does not increase the process complexity.
  • the high-density deep trench can reduce the electric field at the bottom of the trench and improve the reverse voltage withstanding capability of the device.
  • the deep trench and the floating P region can realize the same effect, which enables a surface of the device to store a large number of minority carriers, thereby reducing a conduction drop of the device.
  • the intermediate polysilicon electrode in the trench and the polysilicon electrode in the first trench are both connected with the emitter metal layer, which adds a large collector-emitter capacitance.
  • the capacitance can absorb noise generated during the switching of the device to a certain extent.
  • the present disclosure provides a method for manufacturing the IGBT cell structure.
  • an N+ emitter layer 110 connected with the floating P region 109 and the P well region 108 is formed.
  • a P+ region 111 connected with the N+ emitter in the P well region 108 through an ion implantation process is a P+ region 111 connected with the N+ emitter in the P well region 108 through an ion implantation process.
  • An insulating dielectric isolation layer 112 is deposited on a front side of the N-type substrate, where the insulating dielectric isolation layer 112 covers the N+ emitter layer 110, the trench-shaped insulating oxide layer 103, the polysilicon electrode 104, the trench-shaped gate oxide layer 106, and the polysilicon gate 107; and the insulating dielectric isolation layer 112 has an opening 114 from which the polysilicon electrode 104 and the P+ region 111 are exposed.
  • an emitter metal layer 113 is formed by sputtering metal on a side of the insulating dielectric isolation layer 112 facing sway from a back side of the N-type substrate 115, where the emitter metal layer 113 fills the opening 114.
  • the back side of the N-type substrate 115 is thinned to form an N-type drift layer 101.
  • An N-type termination layer 116 is formed on a back side of the N-type drift layer 101 through ion implantation.
  • a P-type collector layer 117 is formed on a side of the N-type termination layer 116 facing away from the N-type drift layer 101.
  • a collector metal layer 118 is formed by sputtering metal on a side of the P-type collector facing away from the N-type drift layer 101, as shown in FIG. 15 .
  • the formation of the two first trenches 102 spaced apart from each other in the N-type substrate 115 through the photoetching and etching processes, the formation of the trench-shaped insulating oxide layer 103 in each of the first trenches 102, and the deposition of the polysilicon in the trench-shaped insulating oxide layer 103 to form the polysilicon electrode region 123 include:
  • the formation of the second trench 105 in the first trench 102 through the deposition, photoetching, and etching processes, the formation of the trench-shaped gate oxide layer 106 in the second trench 105, and the deposition of the polysilicon in the trench-shaped gate oxide layer 106 to form the polysilicon gate 107 include:
  • the second trench falls in the first trench, and the second trench is a gate trench, only a small contact area is formed between the gate region and the N-type drift layer, so that the IGBT has a small Miller capacitance, which improves the turn-on efficiency of the device and reduce the switching loss of the device.
  • a semiconductor cell structure with excellent performance can be obtained.
  • the semiconductor cell structure and the semiconductor cell structure obtained through the method have very small Miller capacitances, which improves the turn-on efficiency of the device and reduce the switching loss of the device. Therefore, the present disclosure has strong practicability.

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EP21871579.5A 2020-09-24 2021-09-24 Halbleiterzellstruktur, igbt-zellstruktur und herstellungsverfahren dafür und halbleiterstruktur Pending EP4220733A4 (de)

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