EP4154483A1 - Étage de transmission et procédé de génération d'une tension différentielle entre des lignes de bus - Google Patents

Étage de transmission et procédé de génération d'une tension différentielle entre des lignes de bus

Info

Publication number
EP4154483A1
EP4154483A1 EP21720747.1A EP21720747A EP4154483A1 EP 4154483 A1 EP4154483 A1 EP 4154483A1 EP 21720747 A EP21720747 A EP 21720747A EP 4154483 A1 EP4154483 A1 EP 4154483A1
Authority
EP
European Patent Office
Prior art keywords
current paths
elements
transmission
bus
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21720747.1A
Other languages
German (de)
English (en)
Inventor
Steffen Walker
Sebastian STEGEMANN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP4154483A1 publication Critical patent/EP4154483A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0286—Provision of wave shaping within the driver

Definitions

  • the present invention relates to a transmission stage and a method for generating a differential voltage between a first and a second Buslei device of a bus of a bus system based on differential voltage signals, in particular a CAN bus system.
  • the timing behavior or timing is an essential factor that limits the bit rate that can be used in practice.
  • requirements are placed on the length of a bit as well as on the transition in the voltage signal between the voltage states that represent the two possible values of a bit. For example, as the bit rate increases, the length of a bit must be within ever narrower limits and accordingly the transition between the voltage states takes place faster, so that steeper edges in the voltage signal are required, which in turn can lead to an increase in conducted electromagnetic emissions, which are negative affect the achievable bit rate.
  • bus lines In which the signals are transmitted in the form of voltage differences between two conductive wires, the so-called bus lines, because there, on the one hand, two voltage signals have to be precisely timed and, in addition, the two voltages applied to the bus lines are changed at the same time must, ie the voltage curves on both bus lines must be symmetrical.
  • CAN bus CAN stands for Con- troller Area Network
  • a usable bit rate of 5 Mbit / s is aimed for, ie a typical bit length of 200 ns, with a variation of the bit length in the range should be from -10 ns to +10 ns.
  • the invention makes use of the measure of gradually switching the voltage level on a bus line by means of iterative connection of several parallel-connected current paths in each of which a resistor or resistor element is angeord net. According to the invention, it is possible to precisely control the timing of the slope of the differential voltage, so that timing requirements can be met. The currents flowing through the individual current paths are precisely defined by the resistors. A high bit rate is thus achieved with low conducted emissions at the same time.
  • the transmission stage for generating a differential voltage between a first and a second bus line of a bus of a bus system based on differential voltage signals, in particular for a controller area network bus system comprises a first transmission block for generating a voltage signal on the first bus line corresponding to a transmission signal, and a second transmission block for generating a voltage signal on the second bus line corresponding to the transmission signal (that is, in other words, a first transmission block for transmitting a transmission signal to a first bus line of the bus and a second transmission block for transmitting the transmission signal to a second bus line of the bus).
  • the first transmission block has several between one Connection to a first reference potential and a connection to the first bus line, first current paths connected in parallel, each having a first resistance element and each switchable between a conductive and a non-conductive state (more precisely, switchable in both directions, i.e. back and forth switchable).
  • the second transmission block has a plurality of second current paths connected in parallel between a connection to a second reference potential and a connection to the second bus line, each of which has a second resistance element and which can be switched between a conductive and a non-conductive state.
  • a control circuit is provided which is set up to switch each of the first and second current paths at a predetermined point in time within a switching time period beginning with a change in the transmission signal, the first and second current paths depending on a direction of the change Transmit signal can be switched from the conductive to the non-conductive or from the non-conductive to the conductive state.
  • a first current path and a second current path each preferably form a pair, the electrical resistance of the first current path and the second current path of a pair deviating from one another by a maximum of 2%, preferably by a maximum of 1%, more preferably by a maximum of 0.5%.
  • This adjustment of the electrical resistance can essentially be done by adjusting the resistance elements, i.e. the ratio of the resistance values of the two resistance elements in a (current path) pair must be within predetermined, as narrow as possible limits. Preferably, however, the electrical resistances of other elements in the current path, such as switching elements, etc., are also taken into account. Due to the equalization of the first and second current paths in each pair, the voltages on the two bus lines can be generated symmetrically to one another, which leads to a further reduction in conducted emissions.
  • the current paths of a pair are preferably also matched to one another in terms of their electromagnetic properties. Furthermore, the circuit layout can be designed accordingly, with the two resistance elements of a pair of current paths lying next to one another, for example. be arranged, overall this results in a nested arrangement of the resistance elements in which the first and second resistance elements alternate.
  • the resistance elements of a pair also preferably have the same temperature dependency.
  • the control circuit is preferably set up in such a way that the times at which the first current paths are switched are each different from one another, and that the times at which the second current paths are switched are each different from one another.
  • control circuit is preferably set up to switch the first and the second current path, which form the respective pair, at the same point in time for at least one pair. This is more preferably the case for all couples.
  • Each of the pairs is switched over, so to speak, at a respective predetermined point in time.
  • the times for the first and second current paths in different pairs can be different from one another, i.e. different pairs have different switching times. In this way, in particular together with matched resistance elements, mutually symmetrical edges of the two voltages on the first and second bus lines can be achieved.
  • Each first current path preferably comprises a first switching element which is connected in series with the first resistance element and is configured to switch the current path between the conductive and the non-conductive state, and every second current path a second switching element which is connected in series with the second resistance element and is set up to switch the current path between the conductive and the non-conductive state.
  • the first and the second switching elements transistors in particular special metal oxide field effect transistors (MOSFETs), the first switching elements being most preferably p-channel MOSFETs of the enhancement type and the second switching elements n-channel MOSFETs of the enhancement type.
  • MOSFETs metal oxide field effect transistors
  • the switching elements in particular the transistors or MOSFETs, a pair of current paths in their electromagnetic properties are also matched to one another, that is, to be aligned with one another.
  • the control circuit preferably comprises first control elements which control the first switching elements to switch over according to the predetermined times of the first current paths, and second control elements which control the second switching elements to switch over according to the predetermined times of the second current paths; wherein the predetermined times are preferably determined by time constants of the first and second control elements.
  • the first control elements are preferably each connected to one of the first switching elements and the second control elements are each connected to one of the second switching elements.
  • This is especially designed so that a first and second control element is assigned to each of the first and second switching elements, i.e. there is a 1: 1 assignment.
  • the first control elements are connected in series, so that an output signal of a control element serves as an input signal for the first control element following in the series and as a control signal for the first switching element to which it is connected, and the second control elements are used connected in series, so that an output signal of a second control element serves as an input signal for the second control element following in the series and as a control signal for the second switching element to which it is connected.
  • the output signal of the last control element in the respective row clearly only serves as a control signal for the corresponding switching element.
  • the input signal for the first control elements in the row is the transmission signal or a transmission signal modified by a transmission signal control element in such a way that it is suitable for activating the control elements, i.e. the respective first control element in the row, if this is not directly possible, for example.
  • the first current path that is switched first In connection with the goal of reducing emissions on the bus lines, it is preferable to switch between (with regard to the order in which the first current paths are switched) the first current path that is switched first. and the first current path, which is switched last, has a first current path, the first resistance element of which has a lowest resistance value, the course (according to the order in which the first current paths are switched) of the resistance values of the first current paths is monotonous, in particular strictly monotonic, ie between the first current path, which is switched first, and the first current path, the first resistance element of which has the lowest resistance value, the resistance values fall (strictly) monotonic, and between the first current path, its first resistance element is one Has the smallest resistance value, and the first current path, which is switched last, the resistance values increase (strictly) monotonically.
  • the second current paths In connection with the goal of reducing emissions on the bus lines, it is preferable to switch between (with regard to the order in which the first current paths are switched) the first current path that is switched
  • a smallest first and a smallest second resistance element are located in the first and second current paths that are switched at times that are in a middle third of the switching period; wherein preferably a largest first and a largest second resistance element of those resistance elements that lie in first and second current paths that are switched in a temporally first third of the switching period, and / or a largest first and largest second resistance element of those resistance elements that lie in first and second current paths, which are switched in the last third of the switching time span, each being greater by a factor k than the smallest first and the smallest second resistance element, the factor k being at least 2, preferably at least 4 .
  • the transmission blocks and / or the control circuit are preferably set up in such a way that a size of the first and second resistance elements, in accordance with their sequence determined by the predetermined points in time, initially decreases down to the smallest first and the smallest second resistance element and then increases again.
  • the decrease and the increase preferably taking place monotonically, more preferably strictly monotonically.
  • the decrease and / or the increase can take place linearly.
  • the resistance values of the resistance elements can follow the course of a cosine function from 0 to 2p, which is suitably normalized, scaled and shifted in the value range, with the function ons values are taken at regularly spaced support points corresponding to the number of first and second current paths.
  • Figure 1 shows the basic structure of a bus system
  • FIG. 2 shows the course of a transmission signal and a corresponding bus differential voltage signal
  • FIG. 3 shows a transmission stage according to a preferred embodiment of the invention.
  • FIG. 4 shows an illustration of current levels of several current stages. Embodiments of the invention
  • FIG. 1 shows the structure of a bus system based on differential voltage signals, in particular a CAN bus system.
  • the bus system 6 comprises several bus users 8_1, 8_2, ..., 8_m, which are connected to two bus lines 22, 24 of a bus 20 of the bus system are connected and communicate with each other via the bus.
  • the bus users use differential voltages for this purpose between the two bus lines that are generated and read out by means of transceivers.
  • one of the bus users 8_1, more precisely its transceiver comprises, for example, a transmission stage 10 according to the present invention; however, several or all bus users can also comprise a transmission stage according to the present invention.
  • the bus lines 22, 24 are connected to one another via terminating resistors 26a, 26b, which represent the central impedance of the bus system.
  • a transmission signal 2 and a corresponding differential voltage signal 4 for a CAN bus are shown by way of example.
  • both the profile of the voltage V T * D of the transmission signal and the profile of the differential voltage V Diff of the corresponding differential voltage signal 4 on the bus, ie the profile of the voltage difference between two lines of the bus, are plotted against time t.
  • Individual bits in the transmission signal are coded by corresponding voltage levels, e.g. a logic "1" corresponds to a positive voltage level 2a other than zero and a logic "0" corresponds to a voltage level 2b of 0 V.
  • the differential voltage signal on the bus is therefore 1: 1 Relationship, ie the signal on the bus also has two different differential voltage levels which correspond to the levels of the transmission signal, a high bus differential voltage level not necessarily having to correspond to a high transmission signal voltage level.
  • the differential voltage can be obtained in a symmetrical manner by voltages on the bus line, ie the voltage on one bus line increases and the voltage on the other bus line decreases in a symmetrical manner.
  • the two bus lines are at the same voltage level (nominally 2.5 V relative to ground), ie the differential voltage is 0 V, while in the dominant 4b state there is a differential voltage of 2 V (nominally as CAN_H designated first bus line a voltage of 3.5 V and on the second bus line designated as CAN_L a voltage of 1.5 V).
  • CAN_H designated first bus line a voltage of 3.5 V
  • CAN_L a voltage of 1.5 V.
  • a recessive state corresponds to a logical "1"
  • a dominant state corresponds to a logical "0". Due to the delay until a transmission stage provides the voltages on the two bus lines, the differential voltage signal 4 is shifted in time relative to the transmission signal 2
  • FIG. 3 shows a circuit for a transmission stage or transmitter stage according to a preferred embodiment of the invention.
  • the circuit or the sensor stage 10 has a connection 12 for a transmission signal TxD and, based on the transmission signal, generates a differential voltage signal for a bus 20.
  • the circuit comprises a first transmission block 40 and a second transmission block 60, with which a differential voltage between a first bus line 22 and a second bus line 24 of the bus 20 can be generated in accordance with the transmission signal TxD.
  • the transmission blocks are arranged between reference potentials and the bus lines.
  • the first transmission block 40 has a connection 42 for (or to) a first reference potential and a connection 44 for the first bus line 22
  • the second transmission block 40 has a connection 62 for a second reference potential and a connection 64 for the second bus line tion 24 on.
  • the first reference potential is a voltage source or supply voltage (e.g. CAN_SUPPLY) of the bus system and the second reference potential is a ground or a ground potential (e.g. CAN_GND).
  • the transmission stage can be supplied with a current via these connections at a voltage corresponding to the reference potentials.
  • the connections 42, 62 for the reference potentials and the connections to the bus lines 44, 64 are connected in both transmission blocks by a plurality of current paths connected in parallel or arranged in parallel.
  • the first transmission block 40 here comprises several parallel-connected first current paths 46_1, 46_2, ... 46_n, which connect the connection 42 for the first reference potential and the connection 44 for the first bus line 22 and the first resistance elements or resistors, 48_1 , 48_2, ..., 48_n, ie there is a resistance element in each current path.
  • the second transmission block 60 comprises several parallel-connected second current paths 66_1, 66_2, ...
  • connection 66_n which connect the connection 62 for the second reference potential and the connection 64 for the second bus line 24 and the second resistance elements 68_1, 68_2, ..., 68_n have.
  • three current paths are drawn in each case and any further current paths are indicated by dots ""; In general, any number greater than or equal to 2 is possible on the first or second current paths. The same number of current paths is provided in both transmission blocks.
  • a first and a second current path form or define a pair.
  • the two current paths are expediently matched or matched to one another, with at least the resistance elements being matched to one another in terms of their resistance values, so what is known as "matching" of the resistances takes place.
  • the relative deviation of the resistance values of the two resistance elements of a pair of current paths is preferably less than a predetermined limit value.
  • the current paths of a pair can be adjusted in that they are arranged side by side in the circuit layout (not shown in the figure), so that disturbances (e.g. electromagnetic or thermal fluctuations) affect both current paths in the same way.
  • the first and the second current paths are set up in such a way that they can be switched, i.e. switched back and forth, between a conductive and a non-conductive state.
  • first switching elements 50_1, 50_2, ..., 50_n in the first current paths
  • second switching elements 70_1, 70_2, ..., 70_n in the second current paths
  • each current path is a switching element includes in series with the respective resistance element in the current path.
  • the switching elements are designed, for example, as transistors, in particular metal oxide field effect transistors (MOSFETs). It is preferred to use the enrichment type p-channel MOSFETs in the first current paths (ie, normally-off) and the enrichment type n-channel MOSFETs in the second current paths.
  • MOSFETs metal oxide field effect transistors
  • the transistors (MOSFETs) are arranged in such a way that the respective current path is connected to the drain and source connection, i.e. the current path runs over the drain-source connection and is is controlled (operated in the saturation range) when a suitable voltage is applied to the gate.
  • the individual current paths are switched between the conductive and the non-conductive state at predetermined times, which are within a switching period, depending on the transmission signal TxD by means of a control circuit 80 provided for this purpose, which controls the current paths or the switching elements.
  • the first current paths are switched over at predetermined first times, which are preferably different from one another
  • the second current paths are switched over at predetermined second times, which are preferably different from one another.
  • the first and the second points in time are preferably the same for current paths which form a pair.
  • the first and second time points each designate points in time within the switching time span, i.e. times relative to the switching time span.
  • the switching period begins with a change in the transmission signal, i.e. the control circuit is set up accordingly.
  • the first and second points in time represent time intervals for changing the transmission signal.
  • the current paths are either switched from the non-conductive to the conductive State or switched from the conductive to the non-conductive state.
  • the relative direction of the changes in the transmission signal level and the differential voltage level depends on the correspondence between the voltage levels of the transmission signal and the differential voltage levels, which is specified by the bus system specifications.
  • the current paths are switched from the non-conductive to the conductive state when the transmission signal changes from a high to a low level, and from the conductive to the non-conductive state when the transmission signal changes from a low changes to a high level (see FIG. 2).
  • the reverse correspondence can also be implemented in another bus system.
  • control elements or driver elements 52_1, 52_2, ..., 52_n; 72_1, 72_2, ..., 72_n includes.
  • the control circuit may include components specific to either the first or the second Transmission blocks are, and which can accordingly also be understood as elements of the transmission blocks, as in Figure 3.
  • the control circuit is therefore not necessarily a separate arrangement from the transmission blocks, but elements of the transmission blocks can represent components of the control circuit. More specifically, there are first control elements 52_1, 52_2, ..., 52_n in the first transmission block 40 and second control elements 72_1, 72_2, ..., in the second transmission block 60.
  • a control element is provided for each current path or for each switching element;
  • control elements that control multiple current paths or switching elements in particular also control elements that control current paths or switching elements in both the first and the second transmission block.
  • the switching elements are designed as transistors, in particular as MOSFETs, the switching elements can be gate drivers, i.e. control elements which, depending on an input signal, generate an output signal with which a sufficient current and a sufficient voltage are provided, to switch the transistor (MOSFET), when applied to the gate of the transistor, from the blocking to the non-blocking state.
  • the resistance (between the drain and source of the transistor) should be as small as possible in the connected or controlled state (i.e. in the conductive state, especially in the saturation range).
  • the drain-source resistance should be negligibly small compared to the resistance of the resistance element in the corresponding current path, so the transistors or MOSFETs are designed accordingly. If this is not the case, the drain-source resistance should be taken into account together with the resistance element; alternatively, in the sense of an equivalent circuit diagram, the transistors can be imagined as ideal switches without resistance and a possibly given drain-source resistance at the resistance value of Consider resistance elements.
  • the first control elements (gate driver) 52_1, 52_2, ..., 52_n are connected in series in the first transmission block, so that the output signal of a control element controls both a respective switching element (MOSFET) and as an input signal for the one in the series
  • MOSFET switching element
  • the Second control elements 72_1, 72_2, 72_n are arranged analogously in the second transmission block 60. With this arrangement, the first and second points in time are determined by time constants of the control elements, ie by the time that elapses until an input signal of a control element is converted into an output signal.
  • Control elements following in the row are activated with a time delay corresponding to the sum of the time constants of the control elements present, so that the switching elements are activated one after the other with increasing time intervals from the original input signal, which essentially corresponds to the transmission signal. In other words, it takes a certain period of time until all current paths are switched over, with the individual current paths being switched in sequence at certain times within this period of time. This time span should be selected so that the edge time required for transmission in accordance with the bus specification is observed for the voltage signal generated on the bus lines.
  • the first control elements in the two rows (52_1 and 72_1) can in principle be controlled directly by the transmit signal TxD, i.e. directly connected to the connection 12 for the transmit signal.
  • the transmit signal TxD i.e. directly connected to the connection 12 for the transmit signal.
  • the second control elements 72_1, 72_2, ..., 72_n is suitable, for example, suitable voltage levels are generated. Due to the arrangement of the first and second control elements in a row, only the inputs of the first control elements in the two rows (52_1 and 72_1) are connected to the output of the transmission signal control element 14.
  • control circuit ie its specific components
  • the control circuit only needs to be set up to open the first and second current paths at predetermined times or time intervals Depending on the transmission signal, to switch between conductive and non-conductive and vice versa.
  • a polarity diode and / or a cascode can also be provided in each of the transmission blocks. These are switched in series with the current paths.
  • a first polarity diode 54 and / or a first cascode 56 preferably a p-channel cascode, can be arranged between the parallel-connected first current paths 46_1, 46_2, ..., 46_n and the connection 44 for the first bus line will.
  • a second polarity diode 74 and / or a second cascode 76 preferably an n-channel cascode , to be ordered.
  • the cascodes enable maximum nominal parameters to be adhered to (voltage at CAN_H and CAN_L from -27 V to +40 V).
  • a gate of the cascodes is connected to the first or second reference potential.
  • the transmission stage 10 The function of the transmission stage 10 is briefly described below.
  • the first and second current paths are switched one after the other, corresponding to the first and second points in time, within the switching time span from the conductive to the non-conductive state or from the non-conductive to the conductive state.
  • a current flows through each of the current paths corresponding to the resistance value of the resistance element in the respective current path.
  • the sum of the currents of the individual first and second current paths results in a total current that flows over the bus lines.
  • the first and second current paths define, so to speak, the first and second current stages in accordance with the respective resistance values of the resistance elements.
  • a (total) current stage is defined by each pair of a first and a second current path; a current stage is therefore the current that flows through a pair.
  • the sum of the current levels results in the (total) current which flows between the connections 44 and 64 to the bus lines via the bus 20, i.e. the bus lines 22, 24, and which determines the differential voltage.
  • the current paths are switched on or off in sequence at certain times, i.e. switching times, within the switching time span, so that the change in the current intensity over time and thus the change in the differential voltage over time, i.e. the slope of the difference voltage, can be precisely controlled. Due to the equalized current paths, in particular the equalized resistors, and accordingly the first and second current levels matched to one another, the edge profiles of the voltage signals on the two bus lines are symmetrical to one another.
  • the size of the current steps ie the current per step, preferably changes in accordance with the sequence of their (switching) times in the switching time period, with a largest current step at a point in time in the middle third of the switching time period.
  • the change in the size of the current levels includes an increase up to the largest current level and then a decrease.
  • the increase and / or the decrease are preferably monotonous, more preferably strictly monotonous.
  • the current of the largest current stage is preferably greater by a factor k than the current of a ner smallest current level in the first third of the switching time span and / or as the current of a smallest current level in the last third of the switching time span, where the factor k is preferably at least 2, more preferably at least 4, the factor k should not be greater than 20 be.
  • FIG. 4 Such a change is shown by way of example in FIG. 4, in which the current I, per current stage is shown as a function of the number i of the current stage.
  • 12 current levels are shown as an example, with the 6th current level being the one with the highest current.
  • the current I first increases and then from this to the 12th current stage 112, this takes place in a strictly monotonic manner.
  • the last third of the switching period are switched are preferably larger by a factor of k than a smallest first and a smallest second resistance element, which are located in current paths that are switched in the middle third of the switching period. What has been said above applies again to the factor k.
  • Statements about the size of the resistance elements are to be understood as statements about the resistance values of the resistance elements.
  • the increase and decrease in the resistance elements (or their resistance values) is preferably analogous to the increase and decrease in the current levels.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un étage de transmission pour générer une tension différentielle entre une première et une deuxième ligne de bus d'un bus d'un système de bus sur la base de signaux de tension différentielle, en particulier pour un système de bus de réseau de commande. L'étage de transmission comprend un premier et un second bloc de transmission pour générer des signaux de tension sur la première et la seconde ligne de bus ; dans lequel le premier bloc de transmission a de multiples premiers chemins de courant disposés en parallèle qui ont des premiers éléments de résistance, et dans lequel le second bloc de transmission a de multiples seconds chemins de courant disposés en parallèle qui ont des seconds éléments de résistance. Les trajets de courant sont chacun commutable entre un état conducteur et un état non conducteur. Il est prévu un circuit de commande qui est conçu pour commuter chacun des premier et second trajets de courant dans une période de commutation, qui commence avec un changement dans le signal de transmission, à des moments prédéterminés respectifs. En outre, un procédé correspondant est présenté.
EP21720747.1A 2020-05-22 2021-04-21 Étage de transmission et procédé de génération d'une tension différentielle entre des lignes de bus Pending EP4154483A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102020206410.5A DE102020206410A1 (de) 2020-05-22 2020-05-22 Sendestufe und Verfahren zur Erzeugung einer Differenzspannung zwischen Busleitungen
PCT/EP2021/060399 WO2021233638A1 (fr) 2020-05-22 2021-04-21 Étage de transmission et procédé de génération d'une tension différentielle entre des lignes de bus

Publications (1)

Publication Number Publication Date
EP4154483A1 true EP4154483A1 (fr) 2023-03-29

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EP21720747.1A Pending EP4154483A1 (fr) 2020-05-22 2021-04-21 Étage de transmission et procédé de génération d'une tension différentielle entre des lignes de bus

Country Status (4)

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EP (1) EP4154483A1 (fr)
CN (1) CN115552852A (fr)
DE (1) DE102020206410A1 (fr)
WO (1) WO2021233638A1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010041212A2 (fr) * 2008-10-09 2010-04-15 Nxp B.V. Circuit de commande de bus
US8975915B2 (en) * 2012-09-29 2015-03-10 Infineon Technologies Ag Driver circuit for a digital signal transmitting bus
US9495317B2 (en) * 2013-12-18 2016-11-15 Infineon Technologies Ag Bus driver circuit with improved transition speed
DE102015121732B4 (de) * 2015-12-14 2022-07-14 Knorr-Bremse Systeme für Nutzfahrzeuge GmbH Schaltungsanordnung für einen schaltbaren Leitungsabschluss eines seriellen Busses
DE102018202165A1 (de) * 2017-12-22 2019-06-27 Robert Bosch Gmbh Teilnehmerstation für ein serielles Bussystem und Verfahren zum Senden einer Nachricht in einem seriellen Bussystem
DE102018104732B3 (de) * 2018-03-01 2019-02-21 Infineon Technologies Ag Bus-treiberschaltung

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WO2021233638A1 (fr) 2021-11-25
DE102020206410A1 (de) 2021-11-25

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