Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
  • H01L27/1469—Assemblies, i.e. hybrid integration
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
  • H01L27/14687—Wafer level processing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
  • H01L27/14689—MOS based technologies
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
  • H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation

Definitions

• the invention relates to a method of manufacturing an image sensor.
• the manufacture of an image sensor by three-dimensional (3D) integration involves a successive stacking of different layers comprising in particular photodiodes each defining a pixel of the image sensor, components of the pixel reading circuit and interconnections between said components. and pixels.
• Figure 1 is a schematic sectional view of an image sensor.
• Said sensor comprises successively:
• each pixel comprises a doped region 12 adapted to collect the electric charges generated in each pixel; the pixels are separated from each other by electrically insulating trenches 13,
• dielectric or electrically insulating layers 14 for example silicon nitride or silicon oxide
• a silicon layer 22 which comprises components 25 of the pixel reading circuit.
• Interconnects 26 extend through layer 14 to electrically connect components 25 and pixels 11.
• a 3D integration process has significant constraints.
• the method bears the cost of consuming such a substrate.
• the thermal budget of the successive steps must be controlled so as not to damage the active zones or the components previously formed.
• too high a thermal budget is likely to generate an abnormal diffusion of the doped regions configured to collect the photo-generated electric charges in the pixel, which can affect performance. of said sensor.
• metallic connections between elements of the sensor are liable to be damaged by too high a thermal budget.
• An aim of the invention is to design a method of manufacturing an image sensor according to a 3D integration technology, in which the thickness control of the transferred layer is compatible with a substrate of the FDSOI type, which is rapidly industrializable and inexpensive while avoiding the diffusion of dopants present in the regions for collecting electric charges and in the doped layer of amorphous silicon.
• An SOI substrate (acronym for the English term “Semiconductor On Insulator”) is a substrate comprising a semiconductor layer, for example made of silicon, on a substrate, an electrically insulating layer being interposed between the semiconductor layer and the substrate .
• the semiconductor layer In an FDSOI substrate (acronym for the English term “Fully Depleted Semiconductor On Insulator”), the semiconductor layer has a sufficiently thin thickness to allow complete depletion of the conduction channel of a transistor formed in said layer. Such a layer typically has a thickness of a few tens of nanometers.
• the invention provides a method of manufacturing an image sensor, comprising:
• a receiver substrate comprising a base substrate and an active layer comprising pixels, each pixel comprising a doped region for collecting the electrical charges generated in the pixel, said receiver substrate being devoid of metal interconnections,
• finishing treatment comprising (i) thinning of the transferred layer by sacrificial oxidation followed by chemical etching and (ii) smoothing of the semiconductor layer transferred by means of at least one rapid annealing.
• rapid annealing is meant in the present text a heat treatment exhibiting a rise in temperature at a rate greater than 10 ° C per second, preferably of the order of 50 ° C per second or even more.
• the receiving substrate only comprises doped zones but no metallic interconnection makes certain heat treatments acceptable for smoothing the transferred semiconductor layer, said heat treatments having to however present a sufficiently moderate thermal budget for not to cause diffusion of the dopants present in the receiving substrate. Rapid annealing as implemented in the present invention meets this constraint.
• controlled chemical etching provides the uniformity of thickness required for the intended application.
• This thickness uniformity is similar to that of FDSOI substrates, for which the uniformity criterion can be expressed, on the one hand, by the variability of the thickness of the layer transferred within the same substrate or plate. , said intra-plate variability being typically less than or equal to 10 A, and, on the other hand, by the variability of the average thickness of the layer transferred between different plates, said plate-to-plate variability typically being of the order ⁇ 2 A maximum.
• each rapid annealing is controlled to avoid diffusion of dopants from the doped regions of the pixels.
• each rapid annealing can be carried out at a temperature of between 1100 and 1250 ° C. for a period of between 15 and 60 s.
• the sacrificial oxidation and chemical etching are controlled to thin the transferred single crystal semiconductor layer to a thickness between 10 and 100nm.
• the chemical etching of thinning of the transferred monocrystalline semiconductor layer can be carried out by means of wet etching, dry plasma etching, dry etching by ion beam, or dry etching. by ion beam in aggregates.
• the method further comprises, after finishing the transferred single crystal semiconductor layer, forming components of a pixel readout circuit in or on said transferred semiconductor layer.
• the method further comprises, after finishing the transferred single crystal semiconductor layer, forming interconnections between the pixels and said components of the pixel read circuit.
• the method includes forming the weakening layer by implanting atomic species into the donor substrate.
• the finishing treatment successively comprises:
• the donor substrate further comprises, on the monocrystalline semiconductor layer, a layer of silicon oxide, preferably deposited from tetraethyl orthosilicate (TEOS).
• TEOS tetraethyl orthosilicate
• the donor substrate may further include one or more electrically insulating or semiconducting layers (or a stack of these two types of layers) on the silicon oxide layer.
• a semiconductor layer it can be crystalline or amorphous, doped (N + or P +) or undoped.
• the silicon oxide layer is deposited on the donor substrate prior to implantation.
• the receiver substrate further comprises one or more electrically insulating or semiconducting layers (or a stack of these two types of layers) on the active layer.
• at least one electrically insulating layer is a silicon oxide layer and the semiconductor layer can be crystalline or amorphous, doped (N + or P +) or undoped.
• each rapid annealing has a temperature rise rate greater than 10 ° C. per second, preferably greater than or equal to 50 ° C. per second.
• the smoothing does not include any heat treatment having a temperature rise rate of less than 10 ° C. per second.
• the smoothing is implemented individually for each structure comprising the semiconductor layer and the receiver substrate.
• FIG. 1 is a schematic sectional view of an image sensor
• FIG. 2 is a schematic sectional view of a recipient substrate and a donor substrate used in a method of manufacturing an image sensor according to one embodiment of the invention
• FIG. 3 is a schematic sectional view of the recipient substrate and the donor substrate of Figure 2 after detachment of the donor substrate according to the weakening zone;
• FIG. 4 is a schematic sectional view of the image sensor formed from the donor and recipient substrates of FIG. 3, after finishing the transferred semiconductor layer and forming the circuit for reading the pixels and the interconnections;
• FIG. 5 is a SIMS profile of the phosphorus concentration within an SOI structure comprising a layer doped with phosphorus at the end of a rapid annealing as implemented in the present invention and of a heat treatment as implemented during the manufacture of an FDSOI substrate.
• the invention proposes to manufacture an image sensor by transferring a thin layer from a donor substrate to a recipient substrate.
• the receiver substrate includes a base substrate and an active layer comprising a plurality of pixels.
• the base substrate is generally a semiconductor substrate, for example of silicon. Said base substrate has in particular a function of mechanical support of the image sensor.
• the active layer is a monocrystalline semiconductor layer, for example of silicon or of silicon-germanium.
• the pixels are separated from each other by electrically insulating trenches. These trenches are known by the acronym DTI from the Anglo-Saxon term “Deep Trench Isolation” or CDTI from the Anglo-Saxon term “Capacitor Deep Trench Isolation”.
• Each pixel comprises a doped region adapted to collect the electrical charges generated in each pixel.
• the receiving substrate does not include any metallic interconnection between its components.
• the donor substrate comprises an embrittlement zone which delimits a monocrystalline semiconductor thin layer.
• the donor substrate can be a solid substrate, made from a single monocrystalline semiconductor material.
• the donor substrate can be a composite substrate made up of at least two layers of different materials, comprising at least one monocrystalline semiconductor layer.
• the monocrystalline thin film can be a layer of silicon, or of another semiconductor material.
• the weakening zone is advantageously formed by implantation of atomic species, such as hydrogen and / or helium, in the donor substrate. The determination of the dose and of the implantation energy to form the weakening zone at a given depth of the donor substrate is within the abilities of those skilled in the art.
• the surface of the donor substrate may optionally be protected by a dielectric layer, such as a layer of silicon oxide (S1O2). Said layer can then be removed, for example by selective etching.
• the donor substrate is then bonded to the recipient substrate.
• the bonding can be accomplished through a dielectric layer, such as a silicon oxide layer.
• a fracture of the donor substrate is initiated at the area of weakness, leading to detachment of the donor substrate along the area of weakness. After this detachment, the semiconductor thin film was transferred to the recipient substrate.
• This process is well known as the Smart Cut TM process.
• the final product comprising the receiving substrate and the thin semiconductor layer will be referred to as a wafer in the present text.
• the transferred semiconductor thin layer exhibits a certain roughness
• a finishing treatment is carried out on the plate in order to smooth said layer while ensuring the required uniformity of thickness.
• the target thickness for the transferred semiconductor layer is between 10 nm and 100 nm, with a maximum variation of ⁇ 5 ⁇ from the target value, within each wafer and between the different wafers made by the process.
• This uniformity criterion is generally required for the manufacture of FDSOI substrates, but cannot be obtained for the targeted image sensor with the usual finishing treatment for FDSOI substrates which has an excessively high thermal budget.
• the finishing treatment of FDSOI substrates typically comprises a so-called “batch anneal” process, which is a long smoothing process, at high temperature, advantageously carried out in an oven making it possible to treat a plurality of substrates at the same time (from where the term "batch").
• Such a “batch anneal” is typically carried out at a temperature of between 1150 and 1200 ° C., for a period of several minutes, generally greater than 15 minutes.
• the rise in temperature in the oven is relatively slow, with a ramp of the order of a few ° C. per minute, which contributes to increasing the thermal budget suffered by the substrate.
• This smoothing makes it possible to bring the transferred semiconductor layer to a surface roughness level compatible with the manufacture of transistors.
• the finishing treatment implemented in the invention comprises on the one hand a thinning of the layer transferred by sacrificial oxidation followed by a chemical etching and on the other hand a smoothing by means of one or more annealing ( s) fast (s) which provide a lower thermal budget than that of a “batch anneal”, said thermal budget being adapted to preserve the integrity of the pixels.
• the treatment first comprises oxidation of the transferred layer so as to form a thin oxide layer on the surface of said layer.
• This oxide is preferably formed by thermal oxidation of the material of the semiconductor layer, during which the transferred semiconductor layer is subjected to a heat treatment in an oxidizing atmosphere comprising oxygen and / or vapor. water, which has the effect of consuming a surface part of said layer.
• an oxidizing atmosphere comprising oxygen and / or vapor. water, which has the effect of consuming a surface part of said layer.
• the duration of the oxidation is chosen according to the thickness of oxide to be formed, which depends on the initial thickness of the transferred layer and on the target thickness of said layer. Such oxidation can be carried out simultaneously on one or more batches of plates.
• the thickness of the transferred layer covered with the oxide layer is then measured at a number of points distributed over the surface of the plate.
• an ellipsometric or reflectometry measurement provides the thickness of the semiconductor layer.
• a thickness map of said layer obtained by ellipsometry or reflectometry is used. From the thicknesses measured at different points on the plate, we can also determine the average thickness of the semiconductor layer.
• This thickness map and / or this average thickness make it possible to determine one or more regions of the transferred layer having excess thicknesses. relative to a target thickness and therefore to be subject to thinning in order to improve the uniformity of the thickness of the transferred semiconductor layer.
• the measured thickness is compared at each point with the target thickness of the desired end product, said target thickness being less than or equal to the average thickness.
• the region or regions to be thinned are therefore the region or regions in which the thickness of the semiconductor layer is greater than the target thickness, the extra thickness (s) corresponding to the difference between the measured thickness and the thickness. target thickness. This is therefore one or more "local" thicknesses of the plate.
• the average of the thicknesses of the semiconductor layer measured at the different measurement points is compared with a target average thickness.
• a wafer to be thinned is a wafer for which the average thickness of the semiconductor layer is greater than the target average thickness, the extra thickness corresponding to the difference between these two average thicknesses. This is therefore an "overall" extra thickness of the plate.
• a selective etching of the sacrificial oxide layer is first implemented.
• An etching agent suitable for etching the sacrificial oxide without attacking the semiconductor material of the layer is used for this purpose.
• a solution of hydrofluoric acid (HF) is used as the etchant.
• HF hydrofluoric acid
• the etching is wet etching, that is, in which the transferred semiconductor layer is exposed to an etching solution.
• the exposure can be carried out by immersing the plate in said solution, or by spraying the etching solution on the surface of the plate by means of a nozzle, which can make it possible to locate the etch at regions to be thinned out. compared to other regions of the plaque.
• This etching can be carried out at room temperature, that is to say of the order of 20 to 25 ° C, or at a higher temperature but generally less than 80 ° C.
• the etching may be dry plasma etching, dry etching by ion beam ("Reactive Ion Etching” according to English terminology), dry etching by ion beam in aggregates (GCIB, acronym of the Anglo-Saxon term “Gas Cluster Ion Beam”). These steps do not involve a significant thermal budget.
• each annealing is typically carried out at a temperature of between 1100 and 1250 ° C for a period of between 15 and 60 s, which allows a reorganization of the atoms on the surface of the transferred semiconductor layer and thus to smooth it.
• RTA rapid Thermal Annealing
• each rapid anneal is carried out with a rapid rise in temperature, of the order of a few tens of ° C per second.
• rapid annealing is carried out individually on each plate.
• the thermal budget implemented during this (these) annealing (s) is low enough to avoid diffusion of dopants within the plate.
• the process comprises two rapid anneals, in order to obtain an optimum surface condition of the transferred layer.
• the smoothing implemented in the present invention does not include any “batch anneal”. More generally, said smoothing does not include any slow heat treatment, that is to say having a temperature rise rate of less than 10 ° C per second. The integrity of the pixels is therefore preserved during smoothing.
• the method comprises two sacrificial oxidation steps, implemented respectively between the first and the second rapid annealing and after the second rapid annealing when two rapid annealing are implemented.
• the first sacrificial oxidation advantageously makes it possible to remove the defects linked to the implantation of embrittlement by oxidizing a surface region of the layer transferred and removing said oxidized region, while the second sacrificial oxidation, which is followed by chemical etching of the transferred layer, uniformly thin the transferred layer to the target thickness.
• the rapid anneals are preferably carried out before the thinning of the transferred layer, in order to preserve the stability of said layer. It would be possible to do without the first rapid annealing but at the cost of degradation of the roughness.
• Said components are moreover electrically connected to the pixels by interconnections.
• Said interconnections may be metallic but, insofar as they are formed after the finishing treatment of the transferred semiconductor layer, they are not liable to be damaged by it.
• the image sensor it may be useful to insert one or more additional semiconductor and / or electrically insulating layers between the active layer and the semiconductor layer comprising the components of the read circuit.
• said additional layers can be formed on the active layer of the recipient substrate, before the bonding of the donor substrate.
• These layers can be formed, for example, by deposition. Whatever training method is chosen, it does not involve a thermal budget likely to diffuse the dopants from the active layer.
• At least one of said additional layers can be formed by deposition on the active layer of the recipient substrate and at least another of said additional layers is formed by deposition on the monocrystalline semiconductor layer of the donor substrate, before coating. bonding of said substrates.
• the deposition of each additional layer on the active layer of the receiving substrate must be carried out with a sufficiently low thermal budget so as not to generate diffusion of the dopants.
• said additional layers are formed on the donor substrate.
• said layers are formed by deposition before implantation of the atomic species making it possible to form the weakening zone.
• the thermal budget of these deposits does not risk causing a premature fracture of the donor substrate along the weakening zone. If said additional layers are deposited after the formation of the weakening zone, the thermal budget applied will have to be limited in order to avoid such a premature fracture.
• FIG. 2 is a schematic sectional view of the donor substrate and of the recipient substrate before their bonding in one embodiment of the invention.
• the receiving substrate 1 successively comprises:
• an active layer comprising a plurality of pixels 11, each pixel comprising a doped region 12 adapted to collect the electric charges generated in each pixel; the pixels are separated from each other by electrically insulating trenches 13,
• first additional layer 15 for example semiconductor
• the donor substrate 2 comprises a weakening zone 200 delimiting a thin semiconductor layer 201.
• the layer 16, and possibly the layer 15, could be formed on the donor substrate 2 instead of the recipient substrate 1.
• each layer concerned is intended to be transferred onto the recipient substrate with the layer 201. .
• the donor substrate is bonded to the recipient substrate, then the donor substrate is detached along the weakening zone, so as to transfer the semiconductor layer 201 onto the recipient substrate 1.
• the surface S of the layer 201 after detachment is rough.
• components of the read circuit are formed in or on said layer (see Figure 4).
• Interconnections 26 are also formed between the components 25 and the pixels 11.
• FIG. 5 is an SI MS profile (acronym of the English term “Secondary ion mass spectrometry”, that is to say secondary ion mass spectrometry) of the phosphorus concentration within an SOI structure comprising successively from its surface a layer of undoped monocrystalline silicon 42 nm thick, a silicon oxide layer 190 nm thick, a layer of phosphorus doped silicon extending to a depth of 3500 nm, and an unintentionally doped silicon base substrate, after two rapid anneals at 1200 ° C for 30 seconds, as implemented in the present invention (curve a) and a heat treatment (" batch anneal ”) at 1200 ° C for 5 minutes, as used during the manufacture of an FDSOI substrate (curve b).
• SI MS profile as acronym of the English term “Secondary ion mass spectrometry”, that is to say secondary ion mass spectrometry
• the x-axis indicates the depth (in nm) from the surface of the SOI structure
• the y-axis indicates the phosphorus concentration (in at / cm 2 ).
• the clear transition (substantially vertical slope) between the doped layer and the base substrate visible on curve a shows that there was substantially no diffusion of the dopants during the rapid annealing.
• the more gradual transition visible on curve b reflects a phenomenon of diffusion of dopants from the doped layer towards the base substrate.
• Mansoorian 2009 Mansoorian, B., and D. Shaver, with Suntharalingam, V. et al.,

Landscapes

• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Electromagnetism (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Solid State Image Pick-Up Elements (AREA)
• Element Separation (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=70804696

Family Applications (1)

Country Status (8)

Family Cites Families (4)

• 2020
  • 2020-01-15 FR FR2000345A patent/FR3106236B1/fr active Active
• 2021
  • 2021-01-13 TW TW110101307A patent/TW202135146A/zh unknown
  • 2021-01-14 KR KR1020227027258A patent/KR20220127279A/ko unknown
  • 2021-01-14 JP JP2022542040A patent/JP2023510285A/ja active Pending
  • 2021-01-14 CN CN202180009224.7A patent/CN115039226A/zh active Pending
  • 2021-01-14 US US17/758,848 patent/US20230039295A1/en active Pending
  • 2021-01-14 WO PCT/FR2021/050059 patent/WO2021144534A1/fr unknown
  • 2021-01-14 EP EP21719689.8A patent/EP4091197A1/de active Pending

Also Published As

Similar Documents

Legal Events