EP3933893A4 - Speicher und herstellungsverfahren dafür - Google Patents

Speicher und herstellungsverfahren dafür Download PDF

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Publication number
EP3933893A4
EP3933893A4 EP20885464.6A EP20885464A EP3933893A4 EP 3933893 A4 EP3933893 A4 EP 3933893A4 EP 20885464 A EP20885464 A EP 20885464A EP 3933893 A4 EP3933893 A4 EP 3933893A4
Authority
EP
European Patent Office
Prior art keywords
memory
forming method
method therefor
therefor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20885464.6A
Other languages
English (en)
French (fr)
Other versions
EP3933893A1 (de
Inventor
Qiang Zhang
Zhan Ying
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Publication of EP3933893A1 publication Critical patent/EP3933893A1/de
Publication of EP3933893A4 publication Critical patent/EP3933893A4/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
EP20885464.6A 2019-11-08 2020-07-27 Speicher und herstellungsverfahren dafür Pending EP3933893A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911087493.6A CN112786444A (zh) 2019-11-08 2019-11-08 存储器及其形成方法
PCT/CN2020/104961 WO2021088430A1 (zh) 2019-11-08 2020-07-27 存储器及其形成方法

Publications (2)

Publication Number Publication Date
EP3933893A1 EP3933893A1 (de) 2022-01-05
EP3933893A4 true EP3933893A4 (de) 2022-06-22

Family

ID=75748370

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20885464.6A Pending EP3933893A4 (de) 2019-11-08 2020-07-27 Speicher und herstellungsverfahren dafür

Country Status (4)

Country Link
US (1) US11894420B2 (de)
EP (1) EP3933893A4 (de)
CN (1) CN112786444A (de)
WO (1) WO2021088430A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4220699A4 (de) 2021-05-20 2024-05-22 Changxin Memory Tech Inc Herstellungsverfahren für eine halbleiterstruktur
CN115377011A (zh) * 2021-05-20 2022-11-22 长鑫存储技术有限公司 半导体结构的制造方法
CN115360145B (zh) * 2022-10-20 2023-01-31 长鑫存储技术有限公司 一种半导体结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150091127A1 (en) * 2013-09-27 2015-04-02 Ja-Young Lee Semiconductor device and method of manufacturing the same
US20190139767A1 (en) * 2017-11-09 2019-05-09 Nanya Technology Corporation Method for preparing a semiconductor structure

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624022B1 (en) * 2000-08-29 2003-09-23 Micron Technology, Inc. Method of forming FLASH memory
KR100389031B1 (ko) * 2001-06-19 2003-06-25 삼성전자주식회사 트렌치 소자분리 구조를 가지는 반도체 소자의 제조방법
US7244680B2 (en) * 2003-11-14 2007-07-17 Macronix International Co., Ltd. Method of simultaneously fabricating isolation structures having rounded and unrounded corners
KR100731088B1 (ko) * 2005-12-22 2007-06-22 동부일렉트로닉스 주식회사 플래시 메모리 소자의 플로팅 게이트 어레이 형성 방법
CN102005404A (zh) * 2009-08-28 2011-04-06 中芯国际集成电路制造(上海)有限公司 双重深度的浅沟槽隔离制造方法
KR101132803B1 (ko) * 2010-12-30 2012-04-02 주식회사 하이닉스반도체 미세 패턴 형성 방법
JP2012146693A (ja) * 2011-01-06 2012-08-02 Toshiba Corp 半導体記憶装置及びその製造方法
JP2016149409A (ja) * 2015-02-10 2016-08-18 マイクロン テクノロジー， インク． 半導体装置
KR102280471B1 (ko) 2015-07-20 2021-07-22 삼성전자주식회사 액티브 패턴들 형성 방법, 액티브 패턴 어레이, 및 반도체 장치 제조 방법
CN107818980B (zh) * 2016-09-12 2019-07-05 联华电子股份有限公司 有源区域结构以及其形成方法
CN108665862B (zh) * 2017-03-31 2020-05-15 京东方科技集团股份有限公司 一种显示面板及其驱动方法和制作方法、显示装置
CN109148376B (zh) * 2017-06-28 2020-07-31 长鑫存储技术有限公司 存储器及其形成方法、半导体器件
CN107342263B (zh) * 2017-07-07 2018-06-26 睿力集成电路有限公司 存储器及其形成方法、半导体器件
CN207503954U (zh) * 2017-12-01 2018-06-15 睿力集成电路有限公司 浅沟槽隔离结构阵列、半导体器件结构
CN109991806B (zh) * 2017-12-29 2022-03-11 长鑫存储技术有限公司 掩膜版、存储器及存储器的制造方法
CN210607188U (zh) * 2019-11-08 2020-05-22 长鑫存储技术有限公司 存储器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150091127A1 (en) * 2013-09-27 2015-04-02 Ja-Young Lee Semiconductor device and method of manufacturing the same
US20190139767A1 (en) * 2017-11-09 2019-05-09 Nanya Technology Corporation Method for preparing a semiconductor structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2021088430A1 *

Also Published As

Publication number Publication date
WO2021088430A1 (zh) 2021-05-14
US11894420B2 (en) 2024-02-06
EP3933893A1 (de) 2022-01-05
CN112786444A (zh) 2021-05-11
US20210359084A1 (en) 2021-11-18

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