Classifications

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  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
  • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
  • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
  • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
  • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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  • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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  • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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  • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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  • H01L24/93—Batch processes
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  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
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  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
  • H01L25/074—Stacked arrangements of non-apertured devices
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  • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
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  • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • H10D88/00—Three-dimensional [3D] integrated devices
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
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  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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  • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits

Definitions

• Bruel describes implanting ions through gate structures to form a cleaving plane in a substrate and removing a portion of the substrate by cleaving along the cleave plane.
• Bruel acknowledges that ion implantation causes damage to device structures, e.g, channel regions, that can render the devices inoperable.
• Bruel describes building structures on the exposed surface of a substrate to selectively block ion implantation, thereby reducing damage to structures that are disposed directly beneath the blocking structures.
• Bruel there are several limitations to Bruel’ s proposal.
• the structures described by Bruel are relatively large, e.g. gate lengths of 0.5 microns.
• Current devices use structures that are much smaller, e.g. gate lengths of 30 nanometers or less, which are more than an order of magnitude smaller than the gate length described by Bruel.
• ions In order to accumulate sufficient hydrogen ions to perform a cleaving operation, ions must be implanted through a substantial portion of a device surface.
• modern devices are increasingly complex and include higher quantities of sensitive structures.
• Some of these structures, such as vertical transistors have vertical components that are longer than horizontal components, which presents a greater opportunity for damage from a vertically oriented ion that passes through the structure.
• a smaller structure will have fewer atoms and be more sensitive to the disruption of an atom within the structure.
• a barrier layer that has a feature size of 10 nm may have a thickness in the tens of atoms, so that disruption of a single atom may have a significant effect on the barrier property.
• the present disclosure relates generally to the manufacture of integrated circuit devices. More particularly, the present disclosure provides a method and resulting devices for stacking and interconnecting three-dimensional devices using heterogeneous and non-uniform layers, such as fully fabricated integrated circuits.
• the integrated circuits can include, among others, memory devices, processor devices, digital signal processing devices, application specific devices, controller devices, communication devices, and others.
• Embodiments of the present disclosure relate to semiconductor devices including ion cleaving technology.
• Embodiments may be employed to form three-dimensional integrated circuit (3DIC) by implanting ions through a circuit layer to form a cleave plane, repairing damage caused by the implantation, and stacking semiconductor substrates.
• the substrates may be processed at the wafer scale.
• process of forming a 3DIC includes providing a first substrate with a circuit layer that includes plurality of dielectric and conductive structures, implanting ions through the circuit layer and into the first substrate to form a cleave plane, and after implanting the ions through the circuit layer, exposing the semiconductor substrate to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions.
• a first portion of the first substrate with the plurality of dielectric and conductive structures disposed thereon is separated from a second portion of the first substrate by cleaving at the cleave plane, the first portion of the substrate is bonded to a second substrate.
• the first temperature may be from 300C to 500C, and the time may be at least one-half hour.
• the conductive and dielectric structures may include high-K dielectric structures comprising at least one material with a K of 10 or greater.
• the first and second substrates may be wafer scale substrates, and the first substrate may not be exposed temperatures above, for example, 300C, 400C, 450C or 500C after implanting the ions and before separating the first portion from the second portion.
• the hydrogen gas mixture has at least 1% hydrogen gas and a remainder of the gas mixture is one or more inert gas.
• the gas mixture may be a forming gas.
• the ions may be implanted at a temperature of less than 100C and a proton energy that is sufficient to place a majority of recoil damage and the cleave plane deeper than a depletion layer thickness of an operating transistor.
• a process for repairing damage caused by implanting ions through a circuit layer that includes conductive and dielectric structures into a semiconductor substrate is performed by exposing the semiconductor substrate to a hydrogen gas mixture for a first time at a first temperature after implanting ions through the conductive and dielectric structures of the semiconductor substrate.
• the conductive and dielectric structures may include high-K dielectric structures that include at least one of hafnium oxide (FlfCk), hafnium silicon oxide (FlfSiCk), hafnium silicate (HfSi0 4 ), tantalum oxide (TaCk), tungsten oxide (WCk), cerium oxide (CeCk), titanium oxide (TiCk), yttrium oxide (Y2Ck), strontium titanate (SrTiCk), lanthanum aluminate (LaAlCk), niobium pentoxide (NiCk), zirconium silicate (ZrSiCk) and zirconium oxide (ZrCk).
• hafnium oxide FlfCk
• hafnium silicon oxide FlfSiCk
• hafnium silicate HfSi0 4
• tantalum oxide TaCk
• tungsten oxide WCk
• CeCk cerium oxide
• TiCk titanium oxide
• the hydrogen gas mixture may have at least 1% hydrogen gas and a remainder of one or more inert gas, such as a forming gas.
• the exposure time may be at least 30 minutes, and the first temperature may be, for example, from 300C to 500C or from 350C to 450C. In an embodiment, the first time is from one half hour to five hours and the first temperature is from 350C to 450C.
• the dielectric structures may include at least one dielectric material with a K of 20 or more, the first temperature is from 300C to 500C, the hydrogen gas mixture includes at least 1% hydrogen, and the temperature is at least 30 minutes, and the ions are implanted to form a cleave plane below the circuit layer.
• a method of forming a device includes providing a first substrate, depositing a thickness of range compensating material on a first surface of the first substrate, implanting ions into the first substrate, the ions traveling through the range compensating material to define a cleave profile in the first substrate, the cleave profile including at least one contour that corresponds to the thickness of absorber material, removing the absorber material, and cleaving the first substrate at the cleave profile, thereby exposing the at least one contour.
• the at least one contour is a coolant channel.
• the range compensating material may be a photoresist material.
• the method of forming a device may include, after cleaving the first substrate, coating exposed surfaces of the coolant channel with a coating layer.
• the coating material may be a material that prevents a chemical reaction between a coolant fluid and the first substrate material.
• the coating material may be a nitride material or an oxide material.
• the thermal conductivity of the coating material may be higher than a thermal conductivity of a bulk material of the first substrate.
• the first substrate has a thermal conductivity that is greater than 130 W/m-K at a temperature of 25 degrees Celsius.
• the first substrate may include carbon, for example in embodiments in which the first substrate is a diamond or graphite material.
• the cleaved surface of the first substrate may be bonded to a second substrate having a circuit layer.
• the bond may be formed by an oxide layer deposited on a surface of the second substrate.
• a bond layer may be deposited on the first surface of the first substrate, and used to bond a third substrate comprising a circuit layer to the bonding layer on the first surface of the first substrate.
• the first, second and third substrates may be wafer scale substrates.
• hydrogen ions are implanted through one or more circuit layer that includes high-K dielectric and conductive elements.
• ion implantation may damage the dielectric and conductive elements. The damage may be repaired by exposing the substrate to an atmosphere that includes a hydrogen gas and an inert gas at a temperature of from 350 degrees Celsius to 500 degrees Celsius for at least 30 minutes to repair damage to the dielectric structures.
• a method for forming a stacked semiconductor device includes implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.
• the ions may be implanted at a temperature of 100 degrees Celsius or less. In an embodiment the ions are implanted at room temperature.
• a total thickness variation (TTV) of material cleaved from the substrate is 4% or less, 2% or less, or 1% or less.
• the first, second and third substrates may be wafer scale substrates. Furthermore, after cleaving the first substrate, the first substrate may be annealed to repair damage to the dielectric and conductive structures caused by the ions.
• an annealing process that repairs damage to the dielectric and conductive structures is performed at a temperature of 350 Celsius or greater in an environment that includes hydrogen gas. Conditions in a repair process should be sufficient to allow hydrogen to penetrate the device surface and bond to a molecule that was damaged by an implantation process.
• the repair annealing is conducted at a temperature of 400 Celsius in an atmosphere that includes from 2 to 5 percent hydrogen, with a remainder being one or more inert gas.
• the repair annealing is conducted for a period of time that is sufficient to allow the hydrogen gas to diffuse though circuit structures in a device, which may include an interconnect network of metal and low-dielectric constant dielectric material, and to occupy passivating sites at damaged dielectric bonds.
• annealing is conducted at a temperature of 400 Celsius for one hour.
• An embodiment may include depositing a dielectric material over the at least one die after bonding the at least one die to the first substrate and before bonding the third substrate over the at least one die.
• a range compensating layer may be formed over the first substrate.
• the first substrate may be bonded to a second substrate.
• the second substrate has second dielectric and conductive structures, and the second substrate is formed by implanting ions through the second dielectric and conductive structures.
• the first, second and third substrates may be wafers.
• a small die may be one of several types of devices, including an amplifier, a RF tuner, a radio tuner, a Light Emitting Diode, and an optical sensor.
• a method of forming a three-dimensional integrated circuit includes providing a first semiconductor substrate with a first circuit layer including conductive metal and dielectric materials, implanting ions through the plurality of conductive metal and dielectric materials of the first circuit layer to create a first cleave plane in the first substrate, cleaving the first substrate at the first cleave plane, providing a second semiconductor substrate with a second circuit layer including conductive metal and dielectric materials, implanting ions through the conductive metal and dielectric materials of the second circuit layer to create a second cleave plane in the second substrate, cleaving the second substrate at the second cleave plane, bonding the first substrate to the second substrate, stacking at least one die on the second substrate, the die having a width that is less than a width of the first plurality of circuit structures, depositing a
• a method of forming a semiconductor device includes forming an ion range compensating layer over a surface of a first substrate, implanting ions through the ion range compensating layer and dielectric and conductive structures of the first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate;
• planarization material depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.
• the present disclosure provides a method and resulting devices for stacking and interconnecting three-dimensional (3-D) devices using heterogeneous and non-uniform layers, such as fully fabricated integrated circuits.
• the integrated circuits can include, among others, memory devices, processor devices, application specific devices, controller devices, communication devices, and others.
• a method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.
• IC integrated circuit
• Three-dimensional stacking and interconnection of heterogeneous and non-uniform layers, such as fully fabricated integrated circuits are provided.
• Techniques are included for a substantial reduction in inter-layer separation and increase in the available inter-layer connection density, leading to increased signal bandwidth and system functionality, compared to existing chip stacking methods using interposers and through-Silicon vias (TSVs).
• TSVs through-Silicon vias
• the present techniques extend the use of high-energy proton implants for splitting and layer transfer developed for homogeneous materials, such as the fabrication of Silicon-on-Insulator (SOI) wafers, with modifications appropriate for layer transfer of heterogeneous layers and consideration for damage effects in device structures.
• SOI Silicon-on-Insulator
• the present disclosure provides techniques including a method for fabricating an integrated circuit.
• the method includes providing a semiconductor substrate comprising a surface region, a plurality of transistor devices formed overlying the surface region, an interlayer interconnect region comprising a structured metal layer and a structured dielectric layer and an inter-layer connection overlying the plurality of transistor devices, and a dielectric material overlying the interconnection region to provide a bonding interface, although there can be variations.
• the method includes forming an unpatterned photoresist material overlying the bonding interface provided from the dielectric material.
• the unpatterned photoresist material is configured to shield one or more of the plurality of transistors from electromagnetic radiation in a wavelength range of below 400 nm and to selectively adjust a depth of a subsequent implanting process.
• the method subjects the unpatterned photoresist material to the implantation process to introduce a plurality of hydrogen particles through the unpattemed photoresist material to a selected depth to a cleave region underlying the surface region of the semiconductor substrate to define a transfer device between the cleave region and a surface of the dielectric material to form a thickness of a multi-layer of a plurality of interconnected conductive metal layers and insulating dielectric having a total metal thickness of 3 to 5 microns or less.
• the method removes the unpattemed photoresist material after the hydrogen implant step.
• the method bonds the surface of the dielectric material overlying the transfer device to a transfer substrate to temporarily bond the semiconductor substrate to the transfer substrate.
• the method subjects sufficient energy to a portion of the cleave region to remove an upper portion of the semiconductor substrate from a lower bulk substrate material, while using the transfer substrate to hold the upper portion of the semiconductor substrate such that the upper portion comprises a hydrogen damaged region.
• the energy can be provided spatially or globally as described in U.S. Patent No. 6,013,563 (the‘563 patent) hereby incorporated by reference in its entirety.
• the method subjects the hydrogen damaged region overlying the transfer device to a smoothing process to remove a portion or all of the hydrogen damaged region and to form a backside surface. In an example, the method forms a thickness of dielectric material overlying the backside surface.
• the backside surface is configured with one or more provisions for formation of an inter-layer conductive path linking to a bottom landing pad in the structured metal layer of the transfer device and a landing pad for a bonded conductive path to an adjacent device layers.
• the method further comprises depositing a dielectric layer to form a suitable bonding interface on the structured metal layer, the structured metal layer comprising a 5 tolO microns thick conducting layer formed over a densely patterned metal interconnect multi-layers for provision of a device power signal, a ground signal and a frequency synchronization signal, and the dielectric layer having a plurality of conductive paths through the dielectric layer on for bonding with inter-layer conductors in an upper, transfer device layer.
• the method further comprises aligning of the transfer device layer to the semiconductor substrate to permanently bond the inter-layer conducting path.
• the method further comprises removing the temporary bonded semiconductor substrate from the transfer device.
• the method further comprises forming an internal flow path to allow coolant to traverse there through to cool the transfer device.
• the inter-layer coolant channels may be formed by use of a patterned photo resist layer added over the unpatterned photoresist layer. The thickness and/or location of the patterned photo resist layer may be chosen to adjust the local penetration depth of the proton beam to form a non-planar cleave surface in the substrate containing the top surfaces of the coolant channels, with the bottom surface provided by the lower bond plane.
• the plurality of transistor devices are selected from at least one of CMOS devices, bipolar transistors, logic devices, memory devices, digital signal processing devices, analog devices, light absorbing and imaging devices, photo-voltaic cells or micro- electrical mechanical structures (MEMS), or any combination thereof.
• the implantation process proton energy ranges from 500 kilovolts to 2 MeV.
• the cleave region is positioned 1 to 10 microns from a top surface of the dielectric material.
• the unpattemed photoresist material is selected with high absorptivity of electromagnetic radiation with a wavelength less than 400 nm.
• the semiconductor substrate comprises a silicon or other suitable material for formation of electrical, optical or electromechanical devices.
• the implantation process is provided at a dose ranging from 5E16 to 5E17 particles/centimeter 2 .
• the implantation process is provided using a beam line implanter.
• the implantation process is provided by a linear accelerator (LINAC) or other variation.
• the cleave region having a peak concentration at an edge of an implantation range.
• the cleave region comprises a plurality of hydrogen gas-filled micro- platelets.
• the cleave region is characterized by a stress sufficient to induce propagation of an approximately planar cleave region.
• the cleave region is configured as a uniform implantation region or a patterned implantation region.
• the cleave region is patterned or graded to facilitate a controlled cleaving action.
• the method comprises forming a plurality of interconnect structures between the backside surface and either the plurality of transistors or the inter-connect region.
• the method further comprises providing a second semiconductor substrate comprising a plurality of second transistor devices and an overlying second dielectric material; and bonding the second dielectric material configured with the second semiconductor substrate to form a stacked semiconductor structure.
• the method further comprises forming a patterned photoresist material overlying the unpattemed photoresist material.
• the plurality of transistor devices and the interconnect region are characterized by a thickness of three microns and less; wherein the implantation process is characterized by a range of five microns to ten microns such that a characteristic size of the plurality of transistor devices and the interconnect region does not influence the implantation process.
• the plurality of transistor devices and the interconnect region are characterized by a thickness of three microns and less; wherein the implantation process is characterized by a range of five microns to ten microns such that a characteristic spatial dimension of the range of the implantation is not interfered by the thickness of the plurality of transistor devices and the interconnect region.
• the plurality of transistor devices is provided for a memory array or a logic array.
• the energy is selected from thermal, mechanical, chemical, electrical, or combinations thereof to provide a cleave inducing energy.
• the energy is provided to cause a controlled cleaving action including an initiation of cleaving and propagation of cleaving.
• the energy is provided to form a plurality of micro-platelet bubbles in the cleave region.
• a cleave surface may connect a network of the micro-platelet bubbles
• Figure l is a schematic view of an embodiment of this disclosure.
• Figure 2 illustrates a heterogeneous structure containing a layer of transistor devices and an upper network of metal and low-dielectric constant materials, with provisions for inter-layer coolant channels provided by implantation through an additional, patterned photo resist layer in an example.
• Figures 2A-B are simplified cross-sectional views showing use of patterned oxide as an absorber.
• Figure 3 is a schematic view of the transferred device layer viewed at the point of non- uniform surface cleaving after proton implants through patterned dual-layer photoresist (PR) layers, viewed after removal of the PR layers and attachment of a temporary-bonded transfer holder in an example.
• PR photoresist
• Figure 4 sketches a to-be-transferred IC device at the point of the high-dose proton implant with a uniform PR layer in place over the device metal interconnect layers in an example.
• Figure 5 is a simplified view of the transfer device layer after the proton implant, removal of the PR layer attachment of the temporary bonded transfer holder and completion of the wafer level cleaving process in an example.
• Figure 6 shows the major steps applied to the bottom region of the transferred device layer comprising the formation of an oxide layer suitable for bonding after removal of the implant damage layer and final adjustment of the device layer substrate layer thickness and formation of the dense array of inter-layer metal connections and bonding pads in an example.
• Figure 7 shows the cleaved and prepared transferred device layer at the point of precision alignment with mating interconnect structures on the upper surface of a lower device layer in the developing 3D device stack in an example.
• Figure 8 shows a completed intimate 3D stack of a transferred IC device bonded to a lower device layer, with aligned inter-level metal lines in place and bonded at landing pads along the oxide layer bond interface in an example.
• Figure 9 shows a schematic example of two device layers stacked with thick metal interconnect layers in an example.
• Figure 10 shows one example of a process flow for preparing a separable substrate according to an embodiment.
• Figure 10A shows IC processing and/or thinning steps performed downstream of the process flow shown in Figure 10.
• Figure 11 shows a simplified view of a general IC process flow according to an embodiment.
• Figures 12-15 show simplified processing flows according to various alternative embodiments.
• Figure 16 is a simplified cross-sectional view showing a patterned high-K layer in place, incorporating coolant channels.
• Figure 17A is a simplified cross-sectional view showing an example of a detached, unsupported, device layer, under net compressive stress after its fabrication, on a thin substrate layer, deforming its thin substrate layer into a concave shape.
• Figure 17B is a simplified cross-sectional view of the effect of the addition of a stress- compensating layer to the backside of a thin substrate containing a stressed device layer on the top side.
• Figure 18 is a simplified view of the bonding a high-purity, single crystalline transfer layer onto a chemically or mechanically "weak" separation layer on a substrate.
• Figure 19A shows a simplified cross-sectional view of high-energy, high dose proton implant to form a Hydrogen-rich layer placed several microns below the CMOS transistor layer.
• Figure 19B is a simplified cross-sectional view of CMOS device layers after completion of the formation of final gate stack and metal interconnect structures, with a Hydrogen-rich layer formed by a high-energy, high-dose proton implant performed just prior to the "replacement gate” fabrication steps.
• Figure 20 shows a simplified cross-sectional view of a "top-to-top" metal layer bonding of a transfer device layer and a lower device layer in a 3DIC stack.
• Figure 21 illustrates a process for forming a 3DIC structure with different die sizes.
• Figure 22 is a simplified cross-sectional view showing an example of a lower device structure.
• Figure 23 is a simplified cross-sectional view showing an example of a stacked device structure.
• Figure 24 is a simplified cross-sectional view showing an example of smaller die size devices bonded on a 3DIC.
• Figure 25 is a simplified cross-sectional view showing an example of materials deposited over smaller die size devices bonded on a 3DIC.
• Figure 26 is a simplified cross-sectional view showing an example of a 3DIC structure with different die sizes.
• Figure 27 is a simplified cross-sectional view showing another example of a 3DIC structure with different die sizes.
• Figure 28 is a simplified cross-sectional view showing an example of proton implantation.
• Figure 29 is a simplified cross-sectional view showing an example of proton implantation through a range compensating layer.
• Figure 30 illustrates thermal conductivity of a silicon substrate at various phosphorus dopant concentrations and temperatures.
• Figure 31 illustrates thermal conductivity of a silicon substrate at various boron dopant concentrations and temperatures.
• Figure 32 illustrates thermal conductivity according to temperature for 6H-SiC at various temperatures and dopant concentrations.
• Figure 33 illustrates thermal conductivity of various carbon materials.
• Figure 34 illustrates a bonding step for a transfer layer.
• Figure 35 illustrates forming a buried Hydrogen profile below a partially completed device layer.
• Figure 36 illustrates a complete device layer over the Hydrogen profile.
• Figure 37 illustrates 1 MeV protons implanted into a 3 pm thick multilayer containing Cu metal and S1O2 dielectric layers on a Si substrate with a CMOS device layer located just below the metal/oxide multilayer.
• Figure 38A and 38B respectively illustrate a recoil profile and an ionization profile for the implantation of Figure 37.
• the present disclosure provides a method and resulting devices for stacking and interconnecting three-dimensional (3-D) devices using heterogeneous and non-uniform layers, such as fully fabricated integrated circuits.
• the integrated circuits can include, among others, memory devices, processor devices, digital signal processing devices, application specific devices, controller devices, communication devices, and others.
• An embodiment builds and extends the capabilities of two large areas of technology, layer transfer methods for formation of bonded stacks of homogeneous layers, such as the formation of Silicon-on-Insulator (SOI) wafers and diverse methods in present use and development to form 3- D stacks of electrical devices through the use of complex interposer layers and sparse arrays of metal vias for inter-device connections.
• SOI Silicon-on-Insulator
• An embodiment provides for methods of stacking and interconnection of diverse electrical and electro-mechanical layers with simplified bond and interconnect structures with physical scales that are a factor of 10 or more smaller than presently available interposer/TSV methods and providing for greatly increased number of inter-device electrical connection paths, resulting in greatly expanded data transfer bandwidth and 3-D device functionality.
• the present disclosure also provides for protection of sensitive device layers from harmful ultraviolet radiation associated with the use of high-energy proton beam lines and for construction of inter-level networks of coolant flow channels for removal of heat from the volume of the functions 3-D device stack. Further details of the present disclosure can be found throughout the present specification and more particularly below.
• Embodiments may combine Silicon-On-Insulator (SOI) wafer formation approaches utilizing techniques such as H-cut separation and plasma-activated bonding to achieve a room temperature transfer process, combined with Si separation utilizing MeV proton technology, to achieve full-CMOS 3D stacking.
• SOI Silicon-On-Insulator
• LT Layer-Transfer
• WSP Wafer-Scale Packaging
• ETse of plasma fusion bonding allows favorable alignment. And, embodiments as described herein may make layer alignment and interconnect practically achievable goals.
• Embodiments utilizing LT technology involving cold processing allow processing of wafers with Interlayer Dielectric ( ⁇ LD)/metal interconnects.
• ⁇ LD Interlayer Dielectric
• the plasma-activated fusion bond confers bond strength, ultra-thin bond, no glue layers.
• fast thinning operation is possible, without necessarily requiring chemical mechanical polishing (CMP), polishing, or grinding operations.
• CMP chemical mechanical polishing
• Embodiments may be compatible with a variety of IC processes, including those used to fabricate complementary metal oxide semiconductor (CMOS) and Random Access Memory (RAM) devices, etc.
• CMOS complementary metal oxide semiconductor
• RAM Random Access Memory
• Implant scanning techniques may be used. Examples can include obtaining channeling improvements through“dithering”.
• MeV protons Utilization of MeV protons by embodiments for full CMOS stacking, may offer certain benefits. Embodiments may allow avoidance of shadowing due to CMOS layers that include transistor, dielectric, and/or metal layer structures. [0097] A 1 MeV proton beam is sufficient to perform H-cut implants through 8 Cu metal interconnect layers and a full- depth CMOS microprocessor unit (MPU) with ⁇ 1 Opm Si penetration.
• MPU CMOS microprocessor unit
• a figure of merit for the desired minimum separation below the CMOS transistor layer of the proton damage region and bond oxide surface of the transferred layer substrate layer is the depletion depth into the substrate material of a biased, powered on, bulk CMOS array, on the order of 1 micrometer for a 1 V supply voltage and a 10 Ohm-cm substrate material.
• CMOS transistor layers comprising bulk“finFET” and“fully- depleted SOI” devices can have somewhat thinner substrate depletion thickness, depending on the device design and supply voltage. Relative precision (straggling/range) of 1 MeV proton profiles is much sharper than standard SOI wafer fabrication implants (at ⁇ 40 keV).
• H peak depth can be reduced by spin-on resist absorber layers. This aspect is further described in connection with Figures 1-9 discussed later below.
• Figure 10 shows one example of a process flow 1000 for preparing a separable substrate according to an embodiment.
• a donor substrate 1002 is subjected to cleave plane formation 1004, e.g., by the implantation of hydrogen ions.
• the donor substrate including the cleave plane is bonded to a handle substrate 1006, e.g. by a plasma-activated bonding process 1008.
• the LT occurs by the performance of a room Temperature - Controlled Cleaving Process (rT-CCPTM), such that a portion of the donor remains with the handle substrate.
• rT-CCPTM room Temperature - Controlled Cleaving Process
• a portion of the donor may remain with a temporary carrier substrate if this layer is to be retransferred again to a permanent handle substrate (e.g., for back side illumination CMOS image sensors).
• the remaining portion of the donor substrate is reclaimed 1011 for further use.
• the handle including the transferred layer 1010 may be subjected to further processing - e.g., epitaxial (EPI) smoothing and thickening 1012, to produce the separable substrate 1014.
• EPI epitaxial
• Figure 10A shows a simplified process flow 1050 illustrating downstream steps performed upon the substrate provided by a substrate manufacturer of Figure 10. Those steps may comprise IC processing 1052 (see, e.g., Fig. 11 below) and/or thinning 1054 (see, e.g., Figs. 12-15 below).
• Figure 11 shows a simplified view of a general IC process flow 1100 according to an embodiment.
• the IC Maker received“special wafer” 1102 and processes IC layer“n+l” 1104 without any modifications.
• the IC layer is bonded onto the Wafer Scale Processing (WSP) stack (1 to n) 1106. After bonding, the wafer 1102 can be released.
• WSP Wafer Scale Processing
• FIG. 12-15 describe four options of LT for thinning.
• Figure 12 shows an embodiment of LT after IC processing.
• the simplified process flow 1200 shown in this figure involves putting a cleave plane 1202 within the substrate 1203, and then cleaving 1204 after IC processing 1206. It requires more intrusive post-IC process steps.
• Figure 13 shows an embodiment utilizing cleave onto an etchable substrate.
• the simplified process flow 1300 according to this embodiment allows the substrate 1302 to be more easily etched 1304 than SOI bond-grind back processes.
• the etchable substrate may be thin.
• An electrostatic (ES) chuck can be used to help stiffen cleave and handle the thin substrate.
• Transparent substrates can help with layer alignment.
• Figure 14 shows an embodiment of a process flow 1400 where the substrate 1402 comprises a“thin” substrate attached to a releasable base substrate.
• the thin substrate can be utilized in the final 3D product.
• the releasable substrate is solely used for handling during the IC process.
• Figure 15 shows a simplified process flow 1500 according to another embodiment.
• the silicon film 1502 is mounted to a releasable substrate 1504.
• the releasable substrate is solely used for handling during IC process 1506 resulting in processed layer 1508.
• An internal release layer is used after LT.
• the release layer is put within the bond plane.
• LT is used to release the processed Si-layer, followed by thickening if necessary.
• H- cut splitting and layer transfer techniques may be extended to beyond lamination of uniform composition layers to enable wafer-scale stacking of heterogeneous and non-uniform individual layers, with the specific application of intimate stacking of fully-fabricated integrated circuits, including transistor layers and multi-layer interconnect networks.
• Embodiments may achieve high data transfer bandwidth with high-density inter-die interconnect with thin device stacking using "intimate bonding" with H-cut and layer transfer techniques.
• Embodiments may increase manufacturability and device yield by use of room to modest- temperature process throughout the stacking process.
• Some implementations may outline device layer lamination with H-cut and plasma bonding operations (using high-alignment accuracy bonding tools).
• Particular embodiments may utilize variations on front-back stack and front-front stack bonding, with corresponding interconnect depths and locations.
• Some embodiments may thin total device layer elements (no need for interposers), with decreases in RC losses even for high-density inter-device via connections.
• Certain embodiments may implement methods for post-splitting damage layer removal and substrate thickness reduction (selective etching) - appropriate for bonding and heat transfer requirements (much less stringent than SOI wafer layer lamination).
• metrology can be used.
• a scan effect of non-uniform Cu density collects backscattered proton current from a large-angle collection electrode facing IC metal surface with a ⁇ lxl um 2 aperture for MeV proton beam.
• a precision stage scanner for IC motion under aperture maps out net Cu density by backscatter current.
• Design rules can be used to address non-uniformity. These design rules may specify allowable variations in total Cu thickness across IC device areas. Wafer-level splitting can be achieved with large-area checkerboard H distributions.
• a manufacturing process can be used to address non-uniformity.
• a "dummy" Cu or other similar material layer may be added at positions of low-Cu thickness, such as inter layer metal via channels.
• other materials include materials such as CVD-deposited oxide and nitride dielectrics, polymers, and other metals. In general, the material should have sufficient ion stopping power and thickness to bring the location of deep proton peaks into an approximately similar depth across a cleave plane.
• Embodiments may set the cleave plane depth, not directly affected by proton energy or variation in total Cu-layer densities, by constructing IC devices over a high-stress epi layer, such as a graded Si-Ge thin layer, to localize post-stopping H concentration along high-stress interfaces.
• the cleave plane will be set by the location of the high-concentration H distribution accumulated at the built in high-stress interface.
• Total proton dose and related risk of dielectric bond damage (in low-k interconnect and high-k gate dielectrics) from electronic stopping events may be reduced, by increasing proton lattice damage accumulation (via nuclear stopping events) by lowered wafer temperature during proton implantation.
• Figure 1 is a schematic view of an embodiment at completion of a two-device 3D stacking process.
• the upper device layer containing heterogeneous layers of transistors formed in semiconductor materials, usually Si, and a dense network of metal, usually Cu with various other metals for liners and vias, layers separated by low-dielectric constant electrical insulator materials, is separated from a semiconductor wafer after formation processing by hydrogen implant and associated cleaving process.
• the transfer device structure is covered with a uniform photoresist layer of sufficient thickness and properties to protect the device layers from damaging exposure to ultra-violet radiation from recombination processes in the proton beam line plasma.
• the transferred device layer is also coated with a second photoresist layer patterned to adjust the depth of the proton beam and the resulting cleave surface along the paths of a network of coolant flow channels designed to remove heat from the volume of the completed 3-D device stack.
• Conductive structures include transistor junctions in the substrate and a metal interconnect network contacted to the transistor layer.
• the cleaved lower surface of the transfer device is processed to remove implant damage in the region of the cleave surface and adjust the thickness of the transfer device substrate layer. Then a CVD oxide layer is deposited on the lower surface to provide an efficient bonding surface and to provide an electrically insulating and passivated surface for the coolant flow channels, if present.
• the lower device surface is then etched and filled with metal to form inter-level electrical connection to the transfer device interconnect layers, through a substrate and deposited oxide layer thickness of the order of 1 or more microns.
• the inter-level metal lines in upper transfer device layers are terminated with metal bond pads with bond surfaces at the same plane as the deposited oxide bonding layer.
• a similar deposited oxide is formed on the lower device top surface to provide efficient bonding, a network of vias are etched and filled with metal to provide electrical connections with the lower device interconnect layers.
• the lower metal lines are terminated by metal bond pads at the same plane as the lower deposited oxide surface.
• Figure 2 shows a view of patterned PR and device layer after layer transfer to lower device layer.
• a heterogeneous structure containing a layer of transistor devices and an upper network of metal and low-dielectric constant materials providing interconnects for an integrated circuit (IC) is coated with a uniform photoresist (PR) layer, where the resist properties and thickness is chosen to provide adequate protection for sensitive IC layers and interfaces from exposure to ultra-violet (wavelength less than 400 nm) radiation arising from recombination events in the proton accelerator beam line plasma.
• the thickness and stopping of the uniform PR layer is also chosen to adjust the range of the proton beam to a desired depth below the IC device transistor and depletion layers.
• a second, patterned, PR layer is added over the uniform PR layer with the thickness and stopping of the second PR layer chosen to locally adjust the depth of the implanted proton distribution to provide a non-planar material splitting surface.
• the non-planar splitting surface provides a network path, reflecting the patterning of the upper PR layer, for flow of coolant in the finished IC device stack for removal of heat during device operation.
• inter-level metal vias and bonding landing pads and oxide bonding interfaces which are added to the lower section of the upper transferred device layer before bonding to the lower device layers, described in more detail in later figures.
• Top absorber layers may be used to (1) locally control the depth of the peak of the proton damage profile in the transfer device substrate, thereby controlling the location of cleave surface at separation; (2) define the lateral location and depth of coolant channels formed by the depth variations in the cleave surface; and/or (3) provide a protective layer to absorb UV-radiation arising from electron capture and subsequent radiative processes by proton ions in the accelerator beam line.
• Certain embodiments of this process use an un-patterned, cross-linked photo-resist (PR) layer with a second PR layer deposited above, lithographically exposed and developed to leave a patterned PR over layer.
• PR photo-resist
• CVD deposited dielectric films may use CVD deposited dielectric films.
• an un-patterned CVD oxide layer is deposited on the top surface of the metal interconnect network of the device layer to be transferred to the 3DIC stack.
• the thickness of this first CVD oxide layer may be chosen so that the combined stopping power effects of the CVD oxide, device metal interconnect network and the device substrate places the proton and damage peaks at the desired depth of the main cleave plane surface below the transfer device transistor layer.
• a CVD nitride layer is then deposited on the first CVD oxide layer to act as an etch stop to protect the underlying oxide layer during the etching of the top CVD oxide layer.
• a second CVD oxide layer is deposited on the nitride layer.
• the thickness of the top CVD oxide layer may be chosen to locally shift the location of the peak of incident proton beam to be shallower than the location of the main cleave surface by the desired height of coolant flow channels to be formed by the subsequent bonding of the transferred device layers to a planar bonding surface on the top of an underlying device layer in the 3DIC stack.
• a PR layer may then be deposited on the top oxide, lithographically exposed and developed to leave a patterned PR over-layer. This patterned PR layer protects the top CVD oxide layer in the locations where the coolant channels will be formed during the subsequent oxide etch step, with the nitride layer protecting the lower oxide layer.
• Figure 2A is a simplified cross-sectional view of the transfer device layer at proton implant showing an un-patterned top CVD layer with thicknesses chosen to shift the peak of the proton profile to be at a depth of the desired location of the cleave surface.
• a patterned second CVD oxide layer with thickness chosen to shift the proton beam peak to the height of the (optional) coolant channels to be formed during the subsequent bonding step to the 3DIC device stack.
• a CVD nitride layer deposited between the two oxide layers act as an etch stop for the top oxide patterning etch.
• Figure 2B is a simplified view of upper layers of the transfer device after deposition of un patterned CVD oxide and nitride layers, deposition of a top CVD oxide and PR layers. After lithographic exposure and development of the PR pattern, exposed top CVD layer material is etched off. The nitride layer protects to the lower CVD layer from etch removal. The PR layer is removed prior to proton implant.
• CVD dielectric layers may offer the manufacturing benefit of avoiding the process complications that accompany high-energy implants through polymer PR films, such as out-gassing of Hydrogen and other volatile materials due to the bond-breaking in the PR materials by collisions with the passing proton beam.
• the local control of the proton implant profile into the device and substrate layer through the use of patterned and un-pattemed CVD top layers can be used to compensate for local variations pattern density and total layer thickness in metal interconnect networks both across complex chip die and for processing diverse chip designs on in-process, large-area wafers.
• This capability for local control on the proton profile depth and location of the cleave surface at separation enables the use of a constant energy proton beam for processing of diverse device types, improving in-line wafer manufacturing efficiency.
• Figure 3 is a schematic view of the transferred device layer viewed at the point of non- uniform surface cleaving after proton implants through patterned dual-layer PR layers, viewed after removal of the PR layers and attachment of a temporary -bonded transfer holder. Following the non-uniform surface splitting, the damaged material surrounding the cleave planes, containing H-filled platelets and adjacent lattice damage regions, is removed and additional bottom layer material is removed leaving the desired depth of substrate material containing the IC device transistor and depletion regions.
• non-planar splitting surface is then treated with deposited oxide films to form passivated surface walls for coolant channels as well as formation of efficient bonding surfaces for attachment to adjacent device layers.
• the lower region of the transferred device layer is also processed to form inter-layer metal connection paths between the device layers, described in later figures and discussions.
• FIGS 4 through 9 illustrate the 3D stacking process for a generic set of IC layers using a uniform top PR layer, with no provisions for incorporated coolant channels, for simplicity. Further details of these drawings can be found throughout the present specification and more particularly below.
• FIG. 4 sketches a to-be-transferred IC device at the point of the high-dose proton implant, with a uniform PR layer in place over the device metal interconnect layers.
• the metal interconnect layers are typically a densely patterned, multi-layer structure, comprising 10 to 15 layers of Cu metal, for advanced logic devices, less for memory devices.
• the Cu metal layers and vias are electrically isolated by interleaved layers of low-dielectric constant insulating materials.
• the net Cu layer thickness is typically 3 microns or less in modern practice, without the 5 to 8 micron thick metal layers used for accurate distribution of device synchronization, or "clock", signals, power and ground. Provisions for additional of thick metal interconnects are offered as part of the inter level stacking process.
• the density, optical properties and thickness of PR are chosen to provide adequate protection of the underlying device layers from exposure to UV-wavelength recombination radiation from the proton accelerator beam line plasma and to adjust the depth of the proton peak and cleave plane below the transistor doping and depletion layers.
• FIG. 5 A view of the transfer device layer after the proton implant, removal of the PR layer attachment of the temporary bonded transfer holder and completion of the wafer level cleaving process is shown in Figure 5.
• the cleaving action can be affected by local application of energy in the form of mechanical, chemical, laser or other thermal exposure or global energy or any combination thereof. Cleaving can occur using any of the techniques disclosed in the‘563 Patent, which had been incorporated by reference, a blister technique, or others.
• Figure 6 shows the major steps applied to the bottom region of the transferred device layer which include removal of proton-damaged material in the immediate vicinity of the cleave plane as well as any additional material in order to obtain the desired transfer substrate thickness, formation by chemical vapor deposition (CVD) of a planar bonding interface and formation of inter-level metal lines connecting the transferred device metal interconnect network with lower bonding pads at the plane of the deposited bonding oxide interface. Inter-layer via formation is shown.
• CVD chemical vapor deposition
• Figure 7 shows the cleaved and prepared transferred device layer at the point of precision alignment with mating interconnect structures on the upper surface of a lower device layer in the developing 3D device stack.
• An embodiment exploits the capabilities of advanced alignment and bonding apparatus with wafer level alignment tolerances in the range of 150 nm for 300 mm wafers. Vias and via landing pads are shown.
• Figure 8 shows a completed intimate 3D stack of a transferred IC device bonded to a lower device layer, with aligned inter-level metal lines in place and bonded at landing pads along the oxide layer bond interface. Also shown in Figure 8 is a top deposited oxide layer with metal vias and landing pads at the bond interface level for subsequent stacking of an additional device layer on top of the present transferred device layer.
• FIG. 9 shows a schematic example of two device layers stacked with thick metal interconnect layers, the power device with the completed metal layers in place if it is the bottom device layer and the upper transferred device with the thick metal interconnects added after device transfer and permanent bonding and before the deposition of bonding oxide and formation of inter-level metal lines and bond landing pads.
• the dual device stack has incorporated thick metal clock & power distribution layers.
• TSVs Through-Silicon vias
• the substrate can be almost any monocrystalline, polycrystalline, or even amorphous type substrate.
• the substrate can be made of III/V materials such as gallium arsenide, gallium nitride (GaN), and others.
• the multi-layered substrate can also be used according to an embodiment.
• the multi-layered substrate includes a silicon-on-insulator substrate, a variety of sandwiched layers on a semiconductor substrate, and numerous other types of substrates.
• One of ordinary skill in the art would easily recognize a variety of alternatives, modifications, and variations.
• oxide layers in the bonding stack may be limited as a heat transfer layer by the relatively low thermal conductivity of S1O2.
• the use of higher thermal conductivity, electrically insulating materials as inter-layer structures can increase the heat transfer from local device thermal source regions.
• using high-energy proton implantation, low-thermal budget layer cleaving and transfer bonding may facilitate heat spreading from local device structure“hot spots” and efficiently remove device thermal energy through the use of local coolant flows.
• Proton cleaving and layer transfer methods combined with the patterned cleave regions formed by use of a patterned top layer of photo-resist (or oxide as discussed below) at the proton implant step, bonded to a planar device surface to form inter-layer channels for stack coolant flows, and the use of inter-layer structures with high-thermal conductivity (and low electrical conductivity), provide flexible design elements for controlling the thermal environment in a complex 3D device stack.
• Comparing the thermal conductivity of a variety of common semiconductor materials indicates a variety of materials with substantially higher thermal conductivity than S1O2, with SiC and AI2O3 (sapphire) comprising candidates for this purpose.
• Other high thermal conductivity materials may also be used for the purpose enhancing heat spreading and transport by factors of -10 to -100, compared to equivalent S1O2 layers.
• SiC 120 (W/m-K)
• GaAs 52 (W/m-K)
• AI2O3 30 (W/m-K)
• Inter-layer thermal spreading layer thickness of ⁇ 0.5 to 2 um may be expected for efficient heat flows.
• Figure 16 shows a simplified cross-sectional view including a high-K layer in place, incorporating coolant channels.
• Integrated circuit devices containing diverse layers of semiconductor, dielectric and metal materials, may develop substantial internal stresses during fabrication. Unaddressed, these stresses may be sufficiently high to warp full thickness Si wafers, with thickness greater than 700 micrometers, into a variety of concave, convex, and complex shapes. These deformations may be sufficiently large to create issues in fine-line lithography optics during device fabrication.
• a stress-containing device layer on a detached thin (e.g., several micrometers) substrate were placed in an unsupported fashion on a planar surface, the stress-induced deformation of a wafer-scale combination could pose a challenge for bonding to a planar substrate surface.
• thin device layers may be attached to stiff bonding structures, capable of maintaining a planar bond interface with the stressed layer attached, before they are detached from their initial substrate wafers.
• Figure 17A shows a simplified view of an example of a detached, unsupported, device layer, under net compressive stress after its fabrication, on a thin substrate layer, deforming its thin substrate layer into a concave shape.
• Actual device layer deformations can be in concave, convex, and complex "potato chip" shapes. These deformations can lead to challenges when bonding to a planar surface as well as to bond failures and device degradation due to excess local stresses during subsequent thermal cycles during additional fabrication steps and during device operation.
• embodiments may provide for the addition of stress-compensating layer(s) to the back side of stressed device thin transfer layers to facilitate a bonding process, including improved inter-layer device and bond pad alignment, and to compensate for deleterious effects of subsequent fabrication and device operation thermal cycles.
• U.S. Patent No. 7,772,088 is hereby incorporated by reference for all purposes.
• the backside stress compensation materials can be chosen of materials with complementary thermal expansion properties to the device layer and with thickness sufficient to offset the distortion effect of the device structure internal stress
• Figure 17B is a simplified cross-sectional view showing the effect of the addition of a stress-compensating layer to the backside of a thin substrate containing a stressed device layer on the top side.
• the role of the stress-compensating backside layers is to (1) facilitate bonding to a planar bond surface, (2) improve bond pad alignment accuracy during wafer-level bonding, and/or (3) counteract the effects of differential thermal stress during subsequent fabrication steps and during device stack operation.
• the stress compensating layers can be formed by direct layer transfer to the transfer device layer backside while the transfer device layer is attached to temporary bonding structure.
• a stress compensating layer can be deposited by CVD or other approaches.
• planar, stress compensated, transfer layer can provide a desirable geometry for achieving a high degree of bond pad alignment during wafer level bonding, which is one consideration for successful wafer-level bonding for 3DIC manufacturing.
• Embodiments may employ single crystal layer transfer onto chemical or mechanically "weak” separation layers.
• it may be desirable to allow attaching a high-purity, single crystalline material layer onto a temporary holding layer that is sufficiently robust to survive the thermal, chemical and mechanical stresses of IC or other device fabrication processes, but is "weak” enough to form a separation path under directed chemical or mechanical action.
• Examples of these weak temporary separation layers can include but are not limited to (1) oxide layers formed by thermal growth, CVD deposition or by direct implantation and subsequent thermal processing, that can form a separation path under an overlying layer by chemical action of a selective etchant, such as HF attack on an underlying Si02 layer, and (2) various forms of poly- crystalline or porous forms of the general substrate material that are susceptible to form a separation path under selected chemical or mechanical attack.
• a selective etchant such as HF attack on an underlying Si02 layer
• Forms of directed mechanical attack can include but are not limited to, (1) stress-assisted crack formation initiated by a laterally directed force on a separating wedge-shaped tool, and (2) kinetic attack by laterally directed fluid jets into a mechanically weak layer, such as a porous substrate material region.
• Some forms of chemically or mechanically weak separation layers may lack the high-level crystalline interface required for epitaxial growth of high-purity and high-quality crystalline upper layers useful for fabrication of high performance semiconductor devices.
• embodiments can be used to separate and bond entire device structures, including a fully-formed transistor layers and multi level metal interconnect networks onto suitably chosen temporary separation layers for later fabrication and device integration processing. This may be followed by subsequent separation from the carrier substrate.
• the methods and apparatuses according to embodiments can also be used to separate and bond uniform, high-purity and crystalline layers to be formed into electrical, mechanical or optical devices followed by subsequent separation from the carrier substrate.
• Figure 18 is a simplified view of the bonding a high-purity, single crystalline transfer layer onto a chemically or mechanically "weak" separation layer on a substrate.
• the upper crystalline transfer layer is formed to the desired thickness by the use of high-energy proton implantation and room-temperature separation along the peak of the proton distribution.
• the upper transfer layer can be a uniform crystalline layer or including a combination of IC, mechanical or optical devices and their corresponding metal interconnect networks.
• Embodiments may also provide proton implants useful for separation and layer transfer stacking of highly-sensitive CMOS device structures. As previously mentioned, embodiments utilize high-energy proton implants to form a Hydrogen-rich cleave surface several microns below the combined thickness and stopping power effects of a combination of top layers of photo-resist or CVD dielectrics, and a multi-layer metal interconnect network and transistor layers.
• Radiation damage effects arising from the passage of a high-dose, high-energy proton beam through the metal interconnect and transistor layers, may be at manageable levels - recoverable by standard annealing cycles at modest temperatures.
• embodiments can include an implementation that bypasses concerns for radiation damage effects in device dielectric layers.
• CMOS device fabrication process When the high-dose, high-energy proton implantation is performed at specific points during the CMOS device fabrication process, radiation effects from the proton beam can be substantially avoided.
• One point in the CMOS process can be identified as occurring after the high temperature (e.g., greater than 500 °C) processes associated with activation of dopants in CMOS junctions are completed, and before the deposition of sensitive gate stack oxides and subsequent incorporation of inter-layer dielectrics in the metal interconnect network.
• the principal material in the device wafer is crystalline silicon in doped junctions, with poly-silicon filled lateral isolation regions, and the substrate wafer.
• the only substantial, long-term radiation damage effects in predominantly silicon material are associated with lattice damage arising from the nuclear stopping components of the proton slowing down process.
• Lattice damage events for a high-energy proton beam may be localized near the peak of the proton profile.
• that peak may be placed several microns below the CMOS junctions in the transistor layer and provide key hydrogen-trapping sites for localization of the cleave surface during layer separation.
• the several micron separation between the CMOS transistor layer and its associated carrier depletion layers and the proton-induced lattice damage in the region of the subsequent layer separation, may be sufficient to avoid risk for deleterious device effects from the proton lattice damage layer.
• the gate stack regions are initially defined by temporary films and structures which are "replaced", after completion of the high-temperature thermal cycles, by final device structures incorporating high-dielectric constant ("high-k”) gate oxides and multi layer metal gate electrodes.
• high-k high-dielectric constant
• low-k inter-metal layer
• a high-dose proton implant performed at the point just before the "replacement gate” fabrication would avoid risk of damage to the final device gate and inter-metal layer dielectrics and would not be exposed to 500 °C or higher thermal cycles, that could lead to spontaneous layer separation prior to the desired non-thermal separation process at layer separation after the fabrication of the transfer device layers is completed.
• Figure 19A shows a simplified cross-sectional view of high-energy, high dose proton implant to form a Hydrogen-rich layer placed several microns below the CMOS transistor layer. This is performed after completion of >500 °C anneals associated with dopant activation in the transistor junctions and before fabrication of "replacement gates” including final device gate dielectrics and metal gate electrodes.
• Figure 19B is a simplified cross-sectional view of CMOS device layers after completion of the formation of final gate stack and metal interconnect structures, with a Hydrogen-rich layer formed by a high-energy, high-dose proton implant performed just prior to the "replacement gate” fabrication steps.
• the materials properties of the final gate and inter-metal layer dielectrics limit the fabrication process temperatures to be below 500 °C, which also avoids conditions leading to spontaneous splitting along the Hydrogen-rich region prior to the desired separation, by non- thermal approaches, after completion of the full device structure.
• Utilization of methods and apparatuses according to embodiments may permit modulation of inter-layer bandwidth by stacking order and inter-layer thickness.
• a principal goal of 3DIC stacking is to provide an alternative path for increasing the bandwidth for signal processing communications between devices.
• Bandwidth is the product of the data signal frequency, often approximated by the CPU clock frequency, and the number of external communication channels. For much of its history, IC development has focused on increasing the CPU and other data processing chip cycle frequencies, possibly at the cost of increasing chip power use. The number of communication channels has been limited by the density of bond pads available along the periphery of a planar device.
• the minimum metal channel or "pin” pitch depends on a variety of process and device considerations.
• One factor is the aspect ratio (AR) of the inter-layer metal channels: the ratio of the metal line diameter to the length of the via hole to be filled.
• Conventional "Through Silicon Via” (TSV) structures may typically exhibit an AR of between about 5 to 20. This is significantly higher than the typical design rules for vias in high-density metallization for IC devices - often with an AR of less than 2.
• methods and apparatus of specific embodiments may provide one or more procedures to locally increase the inter-level metal channel density and corresponding communication bandwidth between adjacent device layers.
• Use of high-energy, high-dose proton implants through a substantially completed metal interconnect network and fully formed CMOS transistor layer for formation of a Hydrogen-rich region for non-thermal layer separation and bonding onto a 3DIC stack provides an inter-layer separation of a few micrometers (or less, for the cases of device layers on SOI buried oxides or other device types with minimal carrier depletion layer thicknesses). This allows substantially less inter-layer separation than the tens of micrometers typical of present day TSV and interposer stacking methods.
• the thinner inter-device Si layers and elimination interposer and associated adhesive layers provide by embodiments allows for fabrication shorter and thinner inter-device metal signal connections and greatly reduces the "dead zone" effects arising from thermal stress of present day several microns thick Cu TSV channels.
• some embodiments may employ a variety of layer transfer techniques to align and bond the top layer of the metal interconnect network of the transfer device to inter-layer connection channels in the top layer of the metal network of the lower device layer in the 3DIC stack.
• layer transfer approaches are outlined in Figures 12 through 15.
• the inter-layer communication channel density can be expected to be similar to the pin density in the top layer metallization layers in the two device layers, with pin pitch on the order of a few micrometers or less.
• This“top-to-top” layer bonding results in a factor of 100 to l,000x higher inter-layer connection density, and corresponding increased bandwidth, than existing 2.5D and 3D chip stacking technologies.
• Figure 20 shows a simplified cross-sectional view of a "top-to-top” metal layer bonding of a transfer device layer and a lower device layer in a 3DIC stack.
• This approach can provide inter level metal connection channel densities, and corresponding increased bandwidth, similar to via densities of the top metal layers of CMOS devices.
• 3DIC structures may be characterized by an IO density (in Pins/cm2) of between about 1.0E+06 - 1.0E+08, over a pin pitch range (in nm) of l.E+02 - l.E+04.
• IO density in Pins/cm2
• pin pitch range in nm
• aspect ratios depth: minimum width of diameter
• proton implantation to form a 3DIC structure may take place at energies of about 1 MeV, including energies of between about 300 keV-5MeV, about 500 keV-3 MeV, about 700keV-2 MeV, or about 800keV-l MeV. Incorporated by reference herein for all purposes, is ET.S. Patent Pub. No. 2008/0206962.
• implant properties of hydrogen ions at such higher energy ranges may vary as between the 40 keV energies typical of layer transfer processes for SOI wafer manufacturing.
• a first order description is the ratio of the“half-width” of the proton profile reflecting“straggling” ( ⁇ DC>), to the depth of the“projected range” profile ( ⁇ X>).
• the 1 MeV proton profile is ⁇ 4x“sharper” than the 40 keV profile.
• 3DIC structures are commonly stacked at the wafer level. Wafer-level processing, especially when combined with the directness of the transfer methods for fully-metallized CMOS devices described herein, has substantial advantages for economic and efficient processing.
• Wafer-level processing of bonded structures typically assumes that the same size wafers are used, and the placement of dies on the joined wafers are closely coordinated to result in vertical stacked 3DIC structures after separation into discrete systems. These conditions are commonly met for large-area logic and memory devices fabricated on 200 or 300 mm Si wafers in mass- production foundry processing.
• RF tuners are considerably smaller in die size than cm 2 -sized logic and memory devices.
• These smaller die sized devices may be fabricated on diverse wafer sizes such as 100 and 150 mm, and may use non-bulk silicon substrates such as Radio-Frequency Silicon on Insulator (RF-SOI), GaAs, etc.
• RF-SOI Radio-Frequency Silicon on Insulator
• GaAs GaAs
• TTV Total Thickness Variation
• Embodiments of the present disclosure include devices and processes for 3DIC structures that include heterogeneous die sizes. Dies that are formed by performing ion implantation through circuit structures including dielectric and conductive materials to cleave base substrates simplify the thinning process, and have less variation than backgrinding processes. TTV values that can be obtained by ionic cleaving may be, for example, less than 2%, less than 1.5%, and less than 1.0%. In addition, backgrinding applies a substantial amount of mechanical stress to semiconductor devices, which may disrupt structures in the device, causing further alignment and performance issues.
• Figure 21 shows an embodiment of a process 2100 for forming a 3DIC structure with different die sizes. An advantage of process 2100 is that it combines the economic advantages of wafer-level processing with the flexibility of incorporating layers of smaller area dies, which may be fabricated on a diverse variety of substrate materials and wafer sizes into composite 3DIC structures.
• a base device structure is prepared at 2102.
• Figure 22 illustrates an embodiment in which a base device structure 2202 is prepared using high-energy hydrogen implantation, where the peak concentration of a high-dose hydrogen implant is located in the substrate region below a metallized layer which may be, for example, a CMOS or MEMS device layer.
• the base device structure 2202 includes two wafer-level bonded semiconductor layers, 2202A and 2202B, which are formed by implanting ions through dielectric and conductive structures that are formed on semiconductor wafers. In some embodiments, the base device structure 2202 may be more than two stacked semiconductor layers or a single stacked semiconductor layer.
• Figure 23 illustrates wafer-level bonding in a device orientation where the bonding occurs along the metalized layers of the two layers, where the upper (second) device layer 2202B is face down compared to the lower (first) device layer2202A, which is face up. Although only a single device of each of the first and second device layers are illustrated in Figure 23, in an embodiment, cleaving and bonding operations are performed on a plurality of devices on a wafer.
• inter-metal dielectric materials insulated by inter-metal dielectric materials, that can provide both vertical (device to device) and lateral connections for signal, timing, poser and ground connections.
• inter-device metal connection layers 2204 are analogous in function to redistribution layers (RDL) in modern 2.5 D multi-chip packaging schemes.
• interconnect layer 2208 is formed on the exposed upper surface of base device structure 2202 in process 2104.
• the interconnect layer 2208 may include appropriate bonding pads on the top layer of the base device structure 2202 for direct pick and place addition of various smaller die components, as well as lateral wiring connections to interface between the contact pads exposed by the base device structure 2202.
• the top metal layers of interconnection layer 2208 include multi-level metal networks for lateral communication, power and ground connections for a composite device, with the addition of bonding pad arrays designed for placement and bonding of face-down metal connections with smaller, diverse die types.
• one or more die 2210 is placed on the interconnect layer 2208 in process 2106.
• the one or more smaller die 2210 may be placed using known pick and place techniques to align terminals of the one or more smaller die 2210 with the bonding pads exposed on the upper surface of the interconnect layer 2208.
• the location and metal -to-metal bonding of discrete die types on a composite wafer-level bonded structure 2202 can be accomplished by an automated die pick, place and bond apparatus.
• smaller dies 2210 have different sizes and thicknesses from one another.
• the smaller dies 2210 may be a heterogenous set of devices that perform different functions, or a homogenous set of devices.
• dies 2210 may have various thicknesses, and in some embodiments may be thicker than the desired substrate thickness (e.g., in the range of 1 to 10 um), a layer of deposited material with a similar erosion rate under CMP processes as the substrate die of the added smaller devices may be formed between and over the dies 2210 at 2108.
• dielectric material 2212 may be deposited over exposed surfaces of the device structure including dies 2210 in process 2108.
• the dielectric material 2212 provides for electrical isolation of the smaller dies 2210.
• the dielectric material 2212 may be one or more of a variety of materials commonly used in the semiconductor industry that provide insulation from stray current flows, including a CVD oxide or other suitable insulating material.
• a filler material 2214 is deposited over the dielectric material 2212 at 2110.
• the deposited layer may be plasma deposited poly-Si or amorphous-Si.
• the filler material 2214 may be selected to have a similar erosion rate to the dielectric material 2212 and the substrate material of the smaller die devices 2210 when planarizing the structure at 2112, for example by performing CMP.
• process 2100 and the associated figures describe forming a separate dielectric material 2212 and filler material 2214, in some embodiments only a single material or more than two materials are deposited over the dies 2210.
• a planarization process is performed at 2112 to planarize the upper surface of the device until contact pads are exposed.
• the slurry chemistry for the CMP process may be selected based on the dielectric material 2212 and the filler material 2214 to achieve approximately equal erosion rates of the substrates in the added smaller die structures 2210 and the deposited over-lay er materials.
• planarization process 2112 thins the added smaller die 2210 substrates to thicknesses of about 10 pm or less for later formation of vertical metal vias for interconnection with later added structures and bonding pads.
• planarization 2112 is performed until in an overall layer thickness of 10 to 30 pm is obtained.
• planarization process 2112 provides a planar top surface for the newly enlarged composite device structure for subsequent addition of multi-level metal interconnects for lateral signal, power and ground connections as well as bonding pads designed for connections of additional layers added to the composite structure with wafer-level or discrete die placement methods.
• the planarization process 2112 may be performed on the top surface until the surface roughness has an RA value that is 5 Angstroms or less, or 3 Angstroms or less.
• the deposition and planarization elements of process 2100 may be performed such that substrates of the smaller dies 2110 are thinned to a desired thickness.
• the dielectric and filler materials 2208 and 2210 provide mechanical support, and in some embodiments one or more of the layers formed over dies 2110 facilitate heat transfer out of a final 3DIC structure.
• the device may be packaged after planarization 2112 without placing upper device structures on the smaller dies 2210.
• interconnect structures 2216 to electrically couple at least one of the one or more smaller dies 2210 to upper device layers 2218 of the 3DIC are formed at process.
• the interconnect structures 2216 may be formed on exposed surfaces of smaller dies22l0, and/or on an exposed surface of upper device structure 2218 before it is placed onto the smaller dies.
• the upper device structure 2218 may be a single substrate as illustrated in Figure 23, two wafer level bonded substrates, or more than two substrates.
• Embodiments of process 2100 provide for the addition of layers of discrete dies to a wafer- level process flow for bonding of multi-level device structures into a composite 3DIC structure.
• a device made according to process 2100 may have lateral electrical isolation of diverse added dies in the multi-chip layer, and may include vertical metal connections in dense, high-band width networks as well as lateral metal connection networks for the composite device structure containing wafer-level and discrete die placements.
• process 2100 can accommodate these structures by planarization and thinning of the diverse substrates in the composite device layer.
• a network of channels for flow of coolant fluids can be formed in close proximity to a heat-generating transistor layer by adjusting the local penetration depth of the hydrogen implant profile by adding a patterned "range adjusting" layer comprised of materials formed at a sufficient thickness to result in a local offset in the hydrogen depth and subsequent cleave surface.
• a network of channels can be formed in the bottom surface by bonding the transfer device layer to a planar surface, such as the planarized top layer of another device layer, as shown in Figure 1.
• the range compensating layers may comprise patterned layers of CVD silicon oxide of appropriate thickness combined with an unpattemed silicon nitride layer, which acts as an etch stop for the removal of the patterned oxide layer after the implant step.
• the range compensating layer is a patterned layer of thick photoresist.
• Figure 27 shows an embodiment of a device that includes diverse sized dies 2710 disposed between a lower which has several features that are not present in the device of Figure 26.
• the diverse dies 2710 are formed over a base device structure 2702, which includes upper and lower parts that may be formed by implanting ions through metal and dielectric structures to form a cleave layer at the wafer level, and bonding the upper and lower parts to form the lower device structure 2702.
• the device of Figure 27 shows a plurality of cooling channels 2720 that are disposed at the interface between the upper and lower parts of the base device structure 2702, and at a lower surface of the substrate of upper device structure 2718.
• Figure 26 is the location of vertical interconnect structures. While the embodiment of Figure 26 has vertical vias 2206 that penetrate the upper device structure 2218 and filler material 2214, Figure
• FIG. 27 shows vertical vias 2722 that pass through small die structures 2710 to provide electrical communication between devices of the lower structure 2702, the small dies 2710, and the upper structure 2718.
• Persons of skill in the art will recognize that numerous variations are possible beyond the specific features shown in Figure 26 and Figure 27.
• Processes according to the present disclosure may be applied for transferring devices which contain large variations in the density of total metal layers in local regions of the transferred device.
• the depth of the cleave plane may be affected by the arrangement of conductive and dielectric structures in a circuit layer.
• the depth of peak energy, which manifests as a cleave plane may be less in a high-density area of a device than a low-density, or sparse area.
• Hydrogen cleave plane depth can vary in between different areas of a high-performance microprocessor where a dense, multi-layer metallization layer over the logic core is surrounded by more sparse metal interconnect networks in memory (e.g. embedded SRAMs) and timing and input/output circuits.
• memory e.g. embedded SRAMs
• Other examples include optical sensor (cellphone cameras, etc.) devices where densely metalized image processing circuits are surrounded with more sparsely metalized photosensor arrays.
• MEMS devices often contain multiple layers and open spaces of various material densities. These variations can translate to different stopping powers for hydrogen ions, which can vary the depth of a cleave plane.
• transferring devices containing MEMS devices In an embodiment that includes transferring devices containing MEMS devices.
• embodiments of the present disclosure may include forming a range compensating layer 2902 over a top surface of a semiconductor device to compensate for variations in ion penetration depth resulting from variations in density and/or the types of materials present between an upper surface of the semiconductor device and a cleave plane.
• the compensating layer 2902 has an even thickness, and is selectively deposited over areas of the device which would otherwise have a higher ion penetration depth than areas with no compensating layer.
• the compensating layer 2902 has variations in thickness to account for multiple variations in ion penetration depth.
• a shape of the compensating layer 2902 can be developed by performing ion implantation on a device that lacks a compensating layer, measuring depth variation in the cleave plane, and forming a compensating layer whose thickness varies as a mirror image of the depth variation, e.g. greater depth ion penetration areas would correlate with thicker sections of the compensating layer, and vice versa.
• the thickness of the range compensating layer 2902 may vary from one functional region of a circuit to another, as opposed to varying based on individual nano-scale structures within a region.
• provisions are made for active removal of heat generated by circuit switching and resistive power losses in a volumetric 3D composite multidevice layer system by formation of cooling channels formed along the cleave surface defined by a high-concentration Hydrogen profile.
• the cleave surface depth is defined by the thickness, stopping power and location of patterned layers added to the device surface before Hydrogen implantation.
• embodiments of the present disclosure include a cooling channel.
• he cooling channel was created by modulating a depth profile of implanted Hydrogen with a patterned CVD oxide overlayer that is present when hydrogen is implanted to form a cleave layer.
• An associated CVD nitride layer is used to provide an etch stop for the CVD oxide layer patterning. Both of the CVD nitride and oxide layers are removed in later processing.
• Figure 2 illustrates an embodiment of cooling channels formed along the cleave surface by offsetting the proton depth with a patterned stopping layer photoresist (PR) layer.
• the stopping layer may be a similar dense material deposited on the device wafer surface.
• the thickness and stopping power of the underlying un-patterned PR layer can be used to modulate the depth of the cleave surface features in the substrate material below the transferred device layers.
• FIG. 2 shows the formation of a completed cooling fluid channel by bonding the modulated cleave surface to a planar top surface of an underlying device or substrate layer.
• cooling channels are enhanced by applying a surface coating.
• a surface coating material may be selected to improve heat transfer from the active device layers to a cooling fluid in the cooling channels, and/or to reduce or eliminate chemical reactions between a heat transfer fluid in the cooling channel and a substrate material.
• a cooling channel is disposed in a layer with high thermal conductivity, and the high thermal conductivity material reacts with a heat transfer fluid that flows through the coolant channel.
• exposed surfaces of the coolant channel may be coated with an inert material such as an oxide or nitride material that prevents chemical reactions between the heat transfer fluid and the high thermal conductivity layer material.
• the inert material may be S1O2 or S13N4.
• characteristics of the coating material including material type, thickness, and deposition technique may be selected based on the particular thermal conductivity layer material and heat transfer fluid used in an embodiment.
• the coating material assists in heat transfer, and has a higher thermal conductivity than a substrate material over which the coating is formed.
• Other favorable characteristics of a coating layer on coolant channels include excellent adhesion to the coolant channel wall material, uniform conformal coating thickness for good thermal conductivity and free flow of coolant materials and, being inert to the coolant fluid material at device operating temperatures.
• a fluid in the coolant channels may be a heat transfer fluid with a relatively high thermal conductivity.
• the fluid is an inert substance such as water, or a highly dilute solution.
• the heat transfer fluid may be a nanofluid that comprises nanoparticles that enhance the thermal conductivity of the fluid compared to the liquid phase component. The heat transfer fluid may circulate through an external heat exchanger to transfer heat away from the device.
• the location of the cooling channel can be chosen to be at a transfer device bond layer as seen in Figure 2, or in an alternate location for cases where direct bonding of device metal layers is desired, for high-bandwidth circuit connections, as seen in Figure 20.
• the cooling channels are located near a planar bond surface for a subsequently added device layer.
• one or more heat transfer layer may be included in a 3DIC device.
• a heat transfer layer may be a material that has superior heat transfer characteristics to materials used in an active layer.
• the heat transfer layer may be disposed adjacent to the cooling channels, so that a heat transfer fluid travelling through the cooling channels transfers heat from device circuitry to the heat transfer layer.
• cooling channels are formed directly in a high thermal conductivity heat transfer layer.
• Multi-layer lamination of devices allows for the insertion of layers of high-thermal conductivity materials and interfaces to improve both the lateral spreading of heat from local active circuit regions and the vertical transfer of heat to the network of fluid flowing in cooling channels.
• the provisions for controlling the local depth of the cleave surface in materials also allows for the formation of cooling channels in subsequently laminated high-thermal conductivity layers in a similar fashion as the transferred device layers.
• FIG. 16 illustrates a high thermal conductivity heat spreading layer with coolant flow channels that is bonded between two circuit layers by CVD oxide bond layers.
• the room-temperature thermal conductivity of Silicon the dominant substrate material for current IC fabrication, has a relatively high thermal conductivity, matched closely only by Silicon Carbide (SiC).
• SiC Silicon Carbide
• a consideration for a material for a high thermal conductivity heat transfer material is the thermal conductivity properties of materials at temperatures characteristic of active circuit operations, which are generally in the range of 80 to 120C.
• thermal conductivity decreases strongly with increased temperature, leading to a risk of "thermal runaway" for local regions heated by active circuit power.
• Si thermal conductivity decreases at all temperatures for increased dopant concentrations due to phonon-dopant scattering.
• the dopant levels are relatively low ( ⁇ l0 15 dopants/cm 3 ) leading to relatively high thermal conductivity compared to the higher concentrations illustrated in Figures 30 and 31.
• Figure 32 illustrates thermal conductivity of 6H-SiC at various temperatures and doping concentrations as reported by Morelli et al. (1993).
• Thermal conductivity values of various forms of silicon carbide are reported as being higher than silicon, with conductivity values of 3C, 4H and 6H polytypes being twice as high as silicon at 300K.
• thermal conductivity of some carbon-based materials is much higher than silicon.
• diamond, graphite, graphene and Carbon nano-tubes all have thermal conductivity values that are substantially higher than thermal conductivity of silicon, especially at higher temperatures. While Figures 30 and 31 show a steep decline in silicon’s thermal conductivity above room temperature, the decline in thermal conductivity of carbon-based materials is relatively shallow, and in the case of amorphous carbon, thermal conductivity increases above room temperature.
• thermal conductivity values reported for diamond and graphene are an order of magnitude greater than thermal conductivity of silicon at 300K.
• Another material with a high thermal conductivity that is comparable to forms of diamond is cubic Boron Arsenide. In embodiments of the present disclosure, one of these materials may be used as a bulk substrate material.
• the term“plane” is used to describe a cleave plane, which is generally understood to be a location at which a cleaved layer is separated from a substrate.
• a range compensating layer may be applied to a substrate before ion implantation, which can result in an as-cleaved surface that includes one or more contours which may define, for example, a cooling channel.
• use of the term“cleave plane” in the present disclosure should not be construed as limiting embodiments of this disclosure to cleaved surfaces that are perfectly flat.
• a chemically or mechanically weak cleave surface is formed by ion implantation prior to the formation of any sensitive or reliability concerned device layers, interfaces of structures.
• Such an embodiment may be used in the formation of a full device structure, including a full network of metal interconnects and inter-metal layer dielectrics, to be followed by initiation of cleave action at the pre-formed cleave surface for transfer to a 3DIC stack structure.
• Such an embodiment would reduce concerns for device yield and reliability problems related to the formation of the buried cleave surface.
• this embodiment allows for use of substantially lower proton ion energies for the implant step for a desired cleave surface depth.
• Benefits of such an embodiment include that the mechanical, thermal and chemical conditions for the post-cleave plane formation device fabrication and testing process should be conducted to avoid premature initiation of the cleave action. In an embodiment that uses Hydrogen-driven cleaving, this involves restricting the post-cleave surface formation processing to temperatures below -500C.
• Figure 34 illustrates a bonding step for a transfer layer.
• the transfer layer is a high-purity, crystalline transfer layer that is bonded to a substrate layer containing a chemically of mechanically weak separation layer that can subsequently be cleaved after initiation of appropriate cleave surface formation conditions.
• Figures 35 and 36 illustrate an embodiment of forming a buried Hydrogen profile with peak concentration appropriate for formation of a cleave surface at a depth below a partially completed device layer, prior to formation of sensitive device layers, interfaces or structures.
• Figure 36 illustrates a fully completed device structure, including fully constructed metal interconnect and inter-metal dielectric layers prior to introduction of process conditions for initiation of a cleave surface at the buried Hydrogen-rich cleave surface.
• a process may be performed where a chemically or mechanically weak layer is formed in a partially completed device substrate prior to the formation of sensitive device layers, interface or structures.
• Thermal, mechanical and chemical processing of the subsequent device fabrication may be restricted to conditions which do not initiate cleaving action at the cleave surface locations.
• the sensitive structures may include gate dielectric and inter-metal layer dielectric layers.
• An example of a subsequent process restriction for the case of a Hydrogen implant formed cleave surfaces include processing at temperatures at or below 500C.
• the completed, fully-metallized device structure is transferred to a 3DIC stack following cleaving initiated at the cleave surface.
• Control of implant conditions during proton implantation is important for successful layer transfer of electronic devices.
• One aspect of this control is the radiation damage associated with the passage of protons through electronic device materials and into an underlying substrate.
• the effects caused by these two forms of ion-target atom collisions depend on the type of materials in the target.
• the types of target materials include electronic devices and surrounding structures.
• Nuclear stopping collisions result in a large transfer of kinetic energy to the target atoms, often knocking the target atom out of its original lattice site and creating interstitial target atoms and vacant lattice sites. These interstitials and vacancies can combine with similar defects to form stable structures, which may be collectively referred to as implant damage.
• Figure 37 is a graphical illustration of a model calculation for 1 MeV protons implanted into a 3 pm thick multilayer containing Cu metal and S1O2 dielectric layers on a Si substrate with a CMOS device layer located just below the metal/oxide multilayer.
• the proton tracks show that 1 MeV protons extend deeper than 10 pm below the top metal layer.
• Figure 37 shows that ions injected at a single point on the wafer surface spread laterally over several microns near the deepest portions of the profile, which is referred to as lateral straggling.
• the proton insertion at a point on the metal/oxide multilayer surface results in a spread of implanted protons approximately 15 pm below the surface and several pm in lateral directions.
• Figure 38A illustrates 1 MeV proton and target atom recoil profiles for high-dose protons implanted through the 3 pm thick metal and oxide multilayer structure, CMOS transistor region and silicon substrate illustrated in Figure 37, while Figure 38B illustrates the corresponding ionization profile.
• the depth profiles for the implanted protons have a peak concentration at about 14 pm below the top surface, which is about 11 pm below the CMOS transistor and depletion layers.
• Both the proton and Si recoil distributions are sharply peaked near the deep portions of the implant profiles.
• the Si recoil concentration at the CMOS device layers, which are about 3 pm deep, is more than ten times lower than the recoil concentration peak at the approximate depth of the layer cleave surface, which is 14 pm.
• the high levels of Si recoils at the depth of 14 pm depth produce, under proper process conditions, a dense network of accumulated damage structures that serve to trap the implanted Hydrogen in place.
• Another effect of proton passage through the model device layers is the deposited energy from scattering of energetic protons by loosely bound target electrons.
• the deposited energy typically referred to as ionization energy expressed in eV/Angstrom, has strong peaks in the Cu metal and deep Si layers as seen in Figure 38B. These effects are quickly neutralized by motion of nearby electrons in these two conductive materials.
• the deposited energy from electron scattering in the oxide layers is relatively small at about 4 eV/Angstrom in this example, any scattering collisions that results in a displaced electron creates a broken bond that is not readily repaired by electron motion in the insulating dielectric layers.
• the proton energy may be set high enough so that peaks of proton and recoil damage distributions are deeper than the location of the electronic device transistor layer and the thickness of a depletion layer formed when the device is at operating potential, e.g. 1 pm in 10 Ohm-cm Si, which is a commonly used resistivity. Any overlap of the proton damage layer with the device depletion region could result in strong leakage currents, carrier recombination and other deleterious effects on the device performance.
• the proton depth below the transistor layer and the associated depletion width should allow for removal of most or all of the cleave surface damage region to form a bond surface of adequate planarity and smoothness for high-strength atomic bonding.
• the implant conditions is set to be favorable for the formation a dense and stable accumulated damage region at the location of the desired cleave surface with trapping of a significant portion of the peak proton distribution.
• embodiments may use high proton ion density beams, slow beam and wafer scan speeds, and maintenance of the target temperature during implantation below the onset on in-situ annealing of recoil damage, which is approximately 100C for Si and lower for other materials of interest such as III-V compounds.
• Implant machines that are appropriate for embodiments of the present application include refurbished ion implantation machines that were produced before about 2002.
• Thermal processing after implant and before cleaving along the Hydrogen rich layer such as deposition of CVD layers, thermal treatment of intermediate bond layers, etc. may be performed in order to maintain the integrity of the Hydrogen trapping damage layers.
• a maximum allowed temperature to maintain stable proton trapping is approximately 400C. Accordingly, embodiments of the present application may include limiting all thermal processes performed after Hydrogen implantation and prior to cleaving to temperatures that do not exceed a maximum temperature that may be, for example, 500C, 450C or 400C.
• a thermal process that repairs damage to the dielectric and conductive structures is performed at a temperature of 350C or greater in an environment that includes hydrogen gas. Conditions in a repair process should be sufficient to allow hydrogen to penetrate the device surface and bond to a molecule that was damaged by an implantation process. In one specific embodiment, the repair annealing is conducted at a temperature of 400C in an atmosphere that includes from 2 to 5 percent hydrogen, with a remainder being one or more inert gas.
• the repair annealing is conducted for a period of time that is sufficient to allow the hydrogen gas to diffuse though circuit structures in a device, which may include an interconnect network of metal and low-dielectric constant dielectric material, and to occupy passivating sites at damaged dielectric bonds.
• a device which may include an interconnect network of metal and low-dielectric constant dielectric material
• annealing is conducted at a temperature of 400C for one hour to repair implantation damage.
• the specific temperature relates to the amount of time it takes Hydrogen to diffuse through metal and dielectric interconnect networks and gate stack structures to regions where damaged bonds are located, which may be specific to each device.
• the diffusion of atoms in materials is proportional to (Dt) 1/2 , where D is a diffusion rate exponentially dependent on temperature and t is the diffusion time.
• a repair process may be performed at a temperature as low as 300C. In another embodiment, a temperature of up to 500C may be used. However, certain materials are sensitive to elevated temperatures. Exposing a device to elevated temperatures and longer times may cause unfavorable phase changes in high-k dielectric gate oxides such as HfCk, HfSiCk, etc., loss of lateral dimension control on dopant diffusion in sub-20 nm gate length finFETs, and degradation of dopant activation in laser- doped junction contact regions. With these principles in mind, persons of skill in the art will recognize that appropriate thermal repair processes may be performed at temperatures from 300C to 500C and times of at least 30 minutes in a gas environment comprising at least 1% Hydrogen.
• Some embodiments may use a forming gas for a thermal repair process after ion implantation.
• Forming gasses are a mixture of Nitrogen and Hydrogen gasses with a Hydrogen concentration that is typically between 3% and 5%.
• other embodiments may use inert gasses other than Nitrogen gas, and different concentrations of Hydrogen.
• embodiments may use an inert gas such as Argon, and embodiments may use Hydrogen concentrations of more than 1%. Lower concentrations of Hydrogen may require longer exposure times, while higher concentrations of Hydrogen represent an explosive hazard.
• the Hydrogen gas penetrates exposed surfaces of a damaged device, and may terminate broken bonds in order to repair damage.
• Thermal anneals with forming gas or other hydrogen-bearing gas have appropriate time and temperature conditions to allow diffusion of Hydrogen into the sensitive dielectric layers of electronic devices, including low-k insulators in the metal interconnect network, gate oxides such as SiCk, SiON, high-k dielectrics such as HfCk, and oxide and nitride spacer gate sidewall insulators.
• Materials with higher K values are more sensitive to damage from implantation, so a thermal repair process is increasingly effective for higher K materials.
• a thermal repair process may be performed after implanting through materials having a K value of 10 or more, or materials having a K value of 15, 20, 25 or more.
• High-K materials that benefit from a thermal repair process include hafnium oxide (HfCk), hafnium silicon oxide (HfSiCk), hafnium silicate (HfSiCk), tantalum oxide (TaCk), tungsten oxide (WO3), cerium oxide (CeCk), titanium oxide (TiCk), yttrium oxide (Y2Ck), strontium titanate (SrTiCk), lanthanum aluminate (LaAlCk), niobium pentoxide (NiCk), zirconium silicate (ZrSiCk), zirconium oxide (ZrCk), barium titanate (BaTiCk) and lead titanate (PbTiCk).
• HfCk hafnium oxide
• HfSiCk hafnium silicon oxide
• HfSiCk hafnium silicate
• tantalum oxide TaCk
• tungsten oxide WO3
• a thermal cycle for a repair process does not exceed a threshold for dissolution of the Hydrogen trapping implant damage structure in the region of the intended cleave surface. If the temperature exceeds the dissolution threshold, the trapped Hydrogen will disperse into the substrate so that it is not possible to perform a cleaving operation.
• the temperatures to which a substrate is exposed to after a thermal repair process may be limited to being below a threshold value, e.g. 500C, 450C or 400C after repairing and before cleaving to limit dispersion.
• a thermal repair process it is desirable to perform a thermal repair process to repair ion damage with direct access for the ambient gas to the dielectric layers in the metal interconnect network and transistor gate stack regions.
• a thermal repair process is performed prior to sealing of the electronic device surfaces. Accordingly, it is preferred to perform a thermal repair process prior to performing deposition processes that could limit access to damage sites.
• the thermal anneal is performed before the layers are bonded.
• a network of channels for flow of cooling fluids is defined by modulation of implanted Hydrogen depth by a patterned layer of materials at the device wafer surface during Hydrogen implant with thickness, stopping power and location chosen to create a non-planar cleave surface in the transfer device substrate.
• Similar methods for modulating the depth of the cleave plane may be used to define cooling channels in a selected high-thermal conductivity material layer for subsequent insertion into a laminated multi-layer, multi-device 3DIC stack.
• the surface regions of a cooling fluid flow network are coated with material chosen to increase thermal conductivity between the heated device layer and substrate and the flowing cooling fluid, and to prevent chemical reactions between the device substrate and cooling fluids.
• Embodiments incorporate the advantages of wafer-level bonding processes, including incorporation of cooling fluid network channels, with a design flexibility for incorporation of dies fabricated on different wafer sizes, different wafer thickness and different substrate materials.
• Devices formed using the cleaving and stacking techniques provided in this disclosure have numerous advantages over conventional technologies.
• Substrates that are formed by backgrinding are subject to substantially higher levels of mechanical stress and higher levels of thickness variation over the substrate surface. Ionic cleaving can be performed with fewer process steps than backgrinding, simplifying the process and reducing the amount of handling required.
• Layers of the 3DIC structures according to the present disclosure may be interconnected through dense high bandwidth vertical and lateral metal connections, which may displace the need for interposer and solder bump structures, leading to smaller, more tightly integrated, higher speed devices that are more efficient to manufacture.

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