EP3685433A1 - Systeme und verfahren für ladungsausgeglichene halbleiterleistungsbauelemente mit schneller schaltfähigkeit - Google Patents

Systeme und verfahren für ladungsausgeglichene halbleiterleistungsbauelemente mit schneller schaltfähigkeit

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Publication number
EP3685433A1
EP3685433A1 EP18859235.6A EP18859235A EP3685433A1 EP 3685433 A1 EP3685433 A1 EP 3685433A1 EP 18859235 A EP18859235 A EP 18859235A EP 3685433 A1 EP3685433 A1 EP 3685433A1
Authority
EP
European Patent Office
Prior art keywords
region
implantation
regions
layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18859235.6A
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English (en)
French (fr)
Other versions
EP3685433A4 (de
Inventor
Alexander Viktorovich BOLOTNIKOV
Peter Almern LOSEE
Reza Ghandi
David Alan LILIENFELD
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
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Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of EP3685433A1 publication Critical patent/EP3685433A1/de
Publication of EP3685433A4 publication Critical patent/EP3685433A4/de
Pending legal-status Critical Current

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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
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    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
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    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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    • H01L29/861Diodes

Definitions

  • CB charge balanced
  • CB devices demonstrate reduced resistance and reduced conduction losses per unit area relative to traditional unipolar device designs.
  • the switching speed of CB devices utilizing floating regions depends on the recombination-generation rates of the carriers in the semiconductor material.
  • the recombination-generation rates may be relatively low and may result in relatively low switching speeds.
  • point defects may be introduced into the semiconductor material. However, the point defects may increase the leakage current of the device.
  • a method of manufacturing a semiconductor device includes performing a first implantation in a semiconductor layer via ion implantation and performing a second implantation in the semiconductor layer via ion implantation.
  • the first and second implantation overlap with one another and combine to form a connection region extending through the semiconductor.
  • a CB device in a second embodiment, includes a device layer having a first conductivity type, a first charge balance (CB) layer having the first conductivity type disposed adjacent to the device layer, a first connection region having the second conductivity type comprising a region where a first implantation and a second implantation overlap with one another, a first region formed by the first implantation and is adjacent to the connection region, and a second region formed by the second implantation and is adjacent the connection region, opposite the first region.
  • the device layer comprises a top region having a second conductivity type disposed in a top surface of the device layer.
  • the first CB layer comprises a first plurality of charge balance (CB) regions having the second conductivity type.
  • a CB device includes at least one epitaxial (epi) layer having a first conductivity type that includes a plurality of charge balance (CB) regions having a second conductivity type to form at least one charge balance (CB) layer, a top epitaxial layer having the first conductivity type disposed adjacent to the at least one CB layer to form a device layer, a connection region having the second conductivity type formed by a first implantation and a second implantation overlap with one another, a first region is adjacent the connection region and formed by the first implantation, and a second region is adjacent the connection region and formed by the second implantation, opposite the first region.
  • epi epitaxial
  • CB charge balance
  • a thickness of each of the plurality of CB regions is less than a thickness of the at least one CB layer.
  • the device layer includes a top region having the second conductivity type.
  • the connection region extends from the top region of the device layer to at least one of the plurality of CB regions of the at least one CB layer.
  • FIG. 1 illustrates a perspective view of a of CB metal-oxide-semiconductor field-effect transistor (MOSFET) device that includes a plurality of CB layers, each having a plurality of CB regions, in accordance with an embodiment
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • FIG. 2 illustrates a cross-sectional view of the drift region of the CB MOSFET device of FIG. 1, in accordance with an embodiment
  • FIG. 3 illustrates a perspective view of a CB MOSFET device that includes a connection region that adjoins the CB regions of the CB layers to a well region of the CB device, in accordance with an embodiment
  • FIG. 4 illustrates a perspective view of a CB MOSFET device that includes a connection region that adjoins the CB regions of the CB layers to a well region of the CB device, in accordance with an embodiment
  • FIG. 5 is a cross-sectional view of a drift region of a CB device including a connection region that adjoins the CB regions of the CB layers to a top region of the CB device, wherem the equipotential lines demonstrate the electric field present under reverse bias conditions, in accordance with an embodiment
  • FIG. 6 is a perspective view of a CB device that includes a segmented connection region that adjoins the CB regions of the CB layers to a top region of the CB device, in accordance with an embodiment
  • FIG. 7 i s a perspective vi ew of a CB devi ce that includes a segmented connection region that adjoins the CB regions of the CB layers to a top region of the CB device, in accordance with an embodiment
  • FIG. 8 is a side, secti on view of an embodiment of an epi layer for use in an CB device having first implantation regions of a second conductivity type, in accordance with an embodiment
  • FIG. 9 is a side, section view of the epi layer of FIG. 8 having second implantation regions that overlap with the first implantation regions, in accordance with an embodiment
  • FIG. 10 is a side, section view of the CB device of FIG. 9 having connection regions with overlapping first and second implantation regions, in accordance with an embodiment
  • FIG. 1 1 is a cross-sectional view of a drift region of an embodiment of a CB device wherein first and second low doped regions of the connection region are of the second conductivity type, and N2/2 >N1 , in accordance with an embodiment;
  • FIG. 12 is a cross-sectional view of the drift region of an embodiment of a CB device wherein the first and second low doped regions of the connection region are of the second conductivity type, and N2/2 ⁇ N1, in accordance with an embodiment; and
  • FIG. 13 is a flow chart of a process for creating one or more connection regions in the CB device that are formed by multiple misaligned and overlapping implantation regions, with connection region flanked on either side by the first and second low doped regions, in accordance with an embodiment.
  • the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements.
  • the terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.
  • any numerical examples in the following discussion are intended to be non- limiting, and thus additional numerical values, ranges, and percentages are within the scope of the disclosed embodiments.
  • the term “layer” refers to a material disposed on at least a portion of an underlying surface in a continuous or discontinuous manner.
  • the term “layer” does not necessarily mean a uniform thickness of the disposed material, and the disposed material may have a uniform or a variable thickness.
  • a layer refers to a single layer or a plurality of layers, unless the context clearly dictates otherwise.
  • disposed on refers to layers disposed directly in contact with each other or indirectly by having intervening layers there between, unless otherwise specifically indicated.
  • adjacent as used herein means that the two layers are disposed contiguously and are in direct contact with each other.
  • a layer/region when a layer/region is described as "on" another layer or substrate, it is to be understood that the layers/regions can either be directly contacting each other or have one (or more) layer or feature between the layers and regions.
  • the term “on” describes the relative position of the layers/regions to each other and does not necessarily mean “on top of since the relative position above or below depends upon the orientation of the device to the viewer.
  • the use of "top,” “bottom,” “above,” “below,” “upper”, and variations of these terms is made for convenience, and does not require any particular orientation of the components unless otherwise stated.
  • the terms “lower,” “middle,” or “bottom” refer to a feature (e.g., epitaxial layer) that is relatively nearer the substrate layer, while the terms “top” or “upper” refer to the particular feature (e.g., epitaxial layer) that is relatively the farthest from the substrate layer.
  • CB vertical semiconductor charge-balance
  • SJ semiconductor super-junction
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • IFETs junction field effect transistors
  • BJTs bipolar junction transistors
  • diodes as well as other devices that may be useful for medium -voltage (e.g., 2 kV - 10 kV) and high-voltage (e.g., greater than or equal to 10 kV or lOkV - 20 kV) power conversion related applications.
  • medium -voltage e.g., 2 kV - 10 kV
  • high-voltage e.g., greater than or equal to 10 kV or lOkV - 20 kV
  • wide band gap CB devices such as silicon carbide (SiC) CB devices, gallium nitride CB devices, diamond CB devices, aluminum nitride CB devices, boron nitride CB devices, as well as other CB devices manufactured using one or more wide band gap semiconductor materials.
  • SiC silicon carbide
  • gallium nitride CB devices gallium nitride CB devices
  • diamond CB devices aluminum nitride CB devices
  • boron nitride CB devices as well as other CB devices manufactured using one or more wide band gap semiconductor materials.
  • the disclosed CB devices include multi-layered drift regions implemented using repeated epitaxial growth and dopant implantation steps.
  • multi-layered as well as references to a particular number of layers (e.g., “two-layered,” “three-layered,” “four-layered,”), refers to the number of epitaxial (epi) layers of the CB device.
  • the disclosed multi-layered drift region designs include charge balance (CB) layers having a first conductivity type (e.g., n-type CB layers).
  • each of these CB layers includes a plurality of charge balance (CB) regions, which are discrete, buried, implanted regions of doping having the opposite conductivity type as the remainder of the CB layer that reshape the electrical field in the active area of a CB device.
  • CB regions are described herein as "buried” in that they are disposed within the lower epi layers (e.g., within a CB layer that is disposed between the upper/device epi layer and the substrate layer) of the CB device and are not in contact with a device terminal.
  • these CB layer designs enable low conduction losses and high blocking voltages while still maintaining a relatively simple fabrication process.
  • connection regions of the same conductivity type as the CB regions include connection regions of the same conductivity type as the CB regions, and the connection regions generally provide an electrical connection (e.g., a vertical connection) between the CB regions of the CB layers and a highly doped region (e.g., a top region, a second conductivity region, a well region, body contact region, a junction barrier region, a body region, or termination region) of the same conductivity type as the CB regions that is disposed on or proximate to a top surface (e.g., farthest from the substrate layer) of the device.
  • Fast switching speeds and high blocking voltages may be achieved via connection regions that are narrow and deep, connecting the CB regions.
  • connection region may be formed by two intentionally misaligned implants of doped material.
  • the connection region may be formed by two intentionally misaligned implants of doped material.
  • JFETs junction field effect transistors
  • BJTs bipolar junction transistors
  • diodes e.g., junction barrier Schottky (IBS) diodes, merged PiN Schottky (MPS) diodes, etc.
  • IBS junction barrier Schottky
  • MPS PiN Schottky
  • CB devices that may be useful for medium- voltage (e.g., 2 kV - 10 kV) and high-voltage (e.g., greater than or equal to 10 kV or lOkV - 20 kV) power conversion related applications.
  • FIG. 1 is a perspective view of an embodiment of a CB MOSFET device 8 having a drift region 12 that includes a device layer 14 disposed on a number of charge balance (CB) layers 16.
  • CB charge balance
  • the drift regi on 12 of the CB MOSFET device 8 illustrated in FIG. 1 includes a number of epitaxial layers 18 having a first conductivity type (e.g., n- type epi layers 18) that form the device layer 14 and the CB layers 16 of the CB MOSFET device 8. Additionally, the epi layers 18 each have a dopant concentration, which may be the same or different, in certain embodiments. While the illustrated embodiment includes three epi layers 18 (e.g., 18A, 18B, and 18C), the CB MOSFET device 8 may include any- suitable number of epi layers 1 8 (e.g., 2, 4, 5, 6, or more) to yield a CB MOSFET device 8 having a particular desired voltage rating.
  • a first conductivity type e.g., n- type epi layers 18
  • the epi layers 18 each have a dopant concentration, which may be the same or different, in certain embodiments. While the illustrated embodiment includes three epi layers 18 (e.g., 18A, 18B, and 18C), the CB MO
  • the epi layers 18 may be formed from one or more wide band gap semiconductor materials, such as silicon carbide, gallium nitride, diamond, aluminum nitride, and/or boron nitride.
  • the epi layers 18 may be fabricated using repeated cycles of epitaxial overgrowth. As illustrated, the first epi layer 18A is disposed above and adjacent to a substrate layer 30, the second epi layer 18B is disposed above and adjacent to the first epi layer 18A, and the third epi layer 18C is disposed above and adjacent to the epi layer 18B.
  • a top surface 10 of the device layer 14 of the illustrated CB MOSFET device 8 includes a well region 20 having a second conductivity type (e.g., a p-well region 20) and disposed adjacent to a source region 22 having the first conductivity type (e.g., n-type source region 22).
  • a dielectric layer 24 (also referred to as a gate insulating layer or gate dielectric layer) is disposed adjacent to the device layer 14, and a gate electrode 26 is disposed adjacent to the dielectric layer 24.
  • the plurality of CB layers 18 is disposed on a substrate layer 30 (e.g., a semiconductor substrate layer, a wide band gap substrate layer), and a dram contact 32 is disposed on the bottom 11 of the CB MOSFET device 8, adjacent to the substrate layer 30.
  • a substrate layer 30 e.g., a semiconductor substrate layer, a wide band gap substrate layer
  • a dram contact 32 is disposed on the bottom 11 of the CB MOSFET device 8, adjacent to the substrate layer 30.
  • a source contact 28 is disposed adjacent to the top surface 10 of the device layer 14, and is disposed on a portion of both the source region 22 and the well region 20 of the device layer 14.
  • the portion of the source region 22 (e.g., n-type source region 22) of the CB MOSFET device 8 disposed below the source contact 28 may be more specifically referred to herein as a source contact region 34 of the CB MOSFET device 8.
  • a portion of the well region 20 (e.g., p- type well region) of the CB MOSFET devi ce 8 may be more specifically referred to herein as a body region 36 (e.g., p+ body region 36) of the CB MOSFET device 8.
  • the portion of the body region 36 that is disposed below and adjacent to (e.g., covered by, directly electrically connected to) the source contact 28, may be more specifically referred to herein as a body contact region 38 (e.g., p+ body contact region 38) of the CB MOSFET device 8.
  • an appropriate gate voltage (e.g., at or above a threshold voltage (VTH) of the CB MOSFET device 8) may cause an inversion layer to be formed in a channel region 40, as well as a conductive path to be enhanced in a junction field-effect transistor (JFET) region 42 due to accumulation of carriers, allowing current to flow from the drain contact 32 (e.g., dram electrode, drain terminal) to the source contact 28 (e.g., source electrode, source terminal).
  • the channel region 34 may be generally defined as an upper portion of the well region 20 disposed below the gate electrode 26 and the dielectric layer 24.
  • the CB MOSFET device 8 includes two CB layers 16A and 16B that each include a plurality of CB regions 46.
  • the plurality of CB regions 46 may include any of the features described in U.S. Patent No. 9,735,237, entitled, "ACTIVE AREA DESIGNS FOR SILICON CARBIDE SUPER- JUNCTION POWER DEVICES," filed June 26, 2015, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
  • the device layer 14 may include other implanted features (e.g., features particular to other device structures/types) without spoiling the effect of the present approach.
  • the CB regions 46 are oppositely doped relative to the remainder 48 of the CB layers 16A and 16B.
  • the CB regions 46 are p-type
  • the dopant concentration in the CB regions 46 of the CB layer 16A and in the CB regions 46 of the CB layer 16B may be the same or different, in certain embodiments.
  • the CB regions 46 and the remainder 48 of the CB layers 16A and 16B are each generally designed to substantially deplete and to generally provide similar amounts (e.g., substantially equal amounts) of effective charge (e.g., per cm z , normalized to device active area) from ionized dopants under reverse bias.
  • effective charge e.g., per cm z , normalized to device active area
  • the illustrated charge balance structure allows the CB MOSFET device 8 to achieve high breakdown voltage and low on-state resistance, since the p-type semiconductor portions and the n-type semiconductor portions are both completely depleted under nominal blocking conditions.
  • the CB regions 46 of the CB MOSFET device 8 are separated by (e.g., not vertically connected through) and do not extend through the entire thicknesses of the epi layers 18C and 1 8B.
  • FIG. 2 which is a cross-sectional view of the embodiment of the CB MOSFET device 8 illustrated in FIG. 1 , illustrates the dimensions of the epi layers 1 8A-C and the CB regions 46.
  • the epi layers 1 8A, 18B, and 18C have thicknesses 70 A, 70B, and 70C, respectively, that may be the same or different, in certain embodiments.
  • the CB regions 46 in the CB layers 16A and 16B of the illustrated CB MOSFET device 8 have a particular thickness 72.
  • the thickness 72 of the CB regions 46 may be different in different CB layers 16.
  • the thickness 72 of the CB regions 46 is less than the thicknesses 70A and 70B of the CB layers 16A and 16B, respectively, and as such, the CB regions 46 are not vertically connected through (i.e., do not extend through the entire thicknesses 70 A and 70B) of the epi layers 18A and 18B. It may be appreciated that this feature is in contrast to other CB device designs in which the charge-balance regions are continuous (e.g., continuous vertical pillars that extend through the entire thicknesses of the epi layers 18A and 18B). CB devices including continuous, vertical charge balance pillars are capable of providing low conduction losses and high blocking voltages.
  • fabricating continuous, vertical charge balance pillars that extend through the thi cknesses 70 A and 70B of the epi layers 18 A and 18B may be challenging for certain semiconductor materials having Sow diffusion coefficients of dopants.
  • fabricating such charge balance pillars may be challenging for embodiments in which the epi layers 18A and 18B are fabricated from SiC, which has low diffusion coefficients of dopants compared to silicon (Si).
  • the first epi layer 18A may be formed on top of the substrate layer 30 using epitaxial growth techniques (e.g., epitaxial SiC grown techniques), and the CB regions 46 may be formed in the first epi layer 18A using ion implantation to yield a first CB layer 16 A.
  • the second epi layer 18B may be formed on top of the first epi layer 18A using epitaxial growth techniques, and the CB regions 46 may be formed in the second epi layer 18B using ion implantation to yield a second CB layer 16B.
  • the epitaxial growth/ion implantation steps may be repeated multiple (e.g., 2, 3, 4, 5, or more) times to yield a CB MOSFET device 8 with any suitable number of CB layers 16.
  • the final epi layer 18C may be formed on top of the second epi layer 18B using epitaxial growth techniques and may be suitably implanted with particular features to form the device layer 14 of the CB MOSFET device 8.
  • each CB region 46 may have a particular width 74 and a particular spacing 76.
  • the dimensions (e.g., thickness 72, width 74, and/or spacing 76) of the CB regions 46 may be different in different CB layers 16.
  • the CB regions 46 may have different cross-sectional shapes (e.g., defined by implantation energies/doses). For some embodiments, the shape of the CB regions 46 may not substantially vary along the Z-axis.
  • the doping of the epi layers 18, the doping of the CB regions 46, the thicknesses 70 of the epi layers 18, the thickness 72 of the CB regions 46, the width 74 of the CB regions 46, and the spacing 76 between the CB regions 46 may be varied for different embodiments to enable desired electrical performance (e.g., desired blocking voltage) of the CB MOSFET device 8.
  • the disclosed CB MOSFET device 8 may incorporate different values of the doping of the epi layers 8, the doping of the CB regions 46, the thicknesses 70 of the epi layers 18, the thickness 72 of the CB regions 46, the width 74 of the CB regi ons 46, and the spacing 76 between the CB regions 46 as discussed in co-pending U.S. Application No.
  • certain cell parameters may be selected to provide a blocking voltage of the CB MOSFET device 8 that is between approximately I kilovolt (kV) and 10 kV, 1 kV and 5 kV, or any other suitable range.
  • the specific on-resistance of the drift region 12 of the CB MOSFET device 8 may between approximately 40% and 50% less than the specific on-resistance of a drift region of a non-SJ/CB device (e.g., a semiconductor power device without the CB regions 46).
  • the dopant concentration of the CB regions 46 and/or the epi layers 18 may be between approximately 5x10 " ° cm “3 and approximately 5x10 18 cm “3 , approximately 2xl0 16 cm “3 and approximately 1x10 18 cm “3 , or approximately 5xl0 lb cm “3 and approximately 5x1 Q ! cm “3 .
  • the effective sheet dopant concentration of the CB regions 46 which may be calculated by normalizing the doping concentration of the CB regions 46 to the unit cell area of the CB MOSFET device 8, may be less than or equal to approximately l. lxlO 13 cm “2 .
  • the spacing 76 between the CB regions 46 may be between approximately 0.25 micrometers ( ⁇ ) and approximately 10 ⁇ , approximately 0.5 ⁇ and approximately 8 ⁇ , approximately 0.75 ⁇ and approximately 6 ⁇ , or approximately 1 ⁇ and approximately 3 ⁇ .
  • the CB MOSFET device 8 may also include features to decrease switching losses and increase switching speed.
  • the embodiment of the CB device 80 e.g., a CB MOSFET device illustrated in FIG. 3 includes a connection region 100 having the same conductivity type as the CB regions 46 (opposite conductivity type as the epi layers 8) that is implanted into each of the epi layers 8.
  • the connection region may include two or more intentionally misaligned and overlapping implantation regions, forming a narrow and deep connection region 100 (e.g., a bus/connection) connecting various CB regions 46.
  • the CB device 80 may include any suitable number of connection regions 100 in the form of continuous, vertical pillars or continuous, vertical blocks) that are implanted into portions of the epi layers 18A-C.
  • the disclosed connection regions 100 are disposed adjacent to one or more highly doped regions 102 (e.g., top regions, second conductivity regions, well regions 20, body regions 36, body contact regions 38, or junction barrier regions) of the same conductivity type as the connection region 100 and the CB regions 46.
  • the one or more highly doped regions 102 may be disposed adjacent to (e.g., disposed on, disposed in, implanted in, etc.) the top surface 10 of the device layer 14 of the CB device 80 (e.g., a well region 20, a body region 36, a body contact region 38, a junction barrier region). Additionally, the disclosed connection regions 100 may connect at least one highly doped region 102 disposed in the device layer 14 to at least one of the plurality of CB regions 46 of the CB layers 16. In particular, the disclosed connection regions 100 may extend vertically from one or more highly doped regions 102 (e.g., from one or more features near the top surface 10 of the device layer 14) to at least one CB region 46 of the CB layers 16. For example, the connection regions 100 may adjoin the highly doped regions 102 and at least one CB region 46. In some embodiments, the connection regions 100 may overlap with the highly doped regions 102 and at least one CB region 46.
  • the one or more connection regions 100 may have a depth 104 (e.g., vertical dimension, thickness) to reach the deepest CB regions 46 (i.e., the CB regions 46 that are nearest the substrate 30 and farthest from the device layer 14). Further, the depth 104 of the one or more connection regions 100 may be such that the connection regions 100 extend to and contact (e.g., are disposed adjacent to) the deepest CB regions 46, extend through (e.g., overlap with) a portion of the thicknesses 72 of the deepest CB regions 46, or extend through (e.g., overlap with) the entire thicknesses 72 of the deepest CB regions 46.
  • a depth 104 e.g., vertical dimension, thickness
  • the depth 04 may be greater than or equal to the sum of the thicknesses 70 of n - 1 epi layers 18, where n is the total number of epi layers 18 in a CB device 80.
  • the depth 104 of the connection region 100 is greater than the sum of the thicknesses 70B and 70C of the CB layers 16A and 16B (i.e., the lower two epi layers 18A and 18B).
  • the connection region 100 extends from (e.g., is disposed adjacent to and contacts) the highly doped region 102, winch in this case is the well region 20.
  • connection region 100 extends through the third epi layer 18C (i.e., through the thickness 70C of the third epi layer 18C), through the second epi layer 18B (i . e. , through the thickness 70B of the second epi layer 18B and the thickness 72 of the CB regions 46 in the second CB layer 16B), and through a portion of the thickness 70C of the first epi layer 18A (i.e., through the thickness 72 of the CB regions 46 in the first CB layer 16A).
  • the depth 104 may be such that the connection region 100 only extends through the thicknesses 70B and 70C of the second and third epi layers 18B and 18C, respectively (i.e., the connection region 100 does not extend through the CB regions 46 in the bottom CB layer 16A), or such that the connection region 100 extends through only a portion of thickness 72 of the CB regions 46 in the bottom CB layer 16A.
  • the one or more connection regions 100 may be fabricated by introducing dopants (e.g., boron, aluminum, nitrogen, phosphorus) into the epi layers 18 of the CB device 80 using high energy ion implantation.
  • dopants e.g., boron, aluminum, nitrogen, phosphorus
  • a single connection region may include multiple misaligned and/or overlapping implantation regions.
  • dopants may be implanted with implant acceleration energies between approximately 500 keV and approximately 60 MeV to achieve the desired depth 104.
  • the one or more connection regions 100 may formed using high energy ion implantation along with high stopping power or high blocking mask (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high-Z metals such as platinum, molybdenum, gold).
  • SOI silicon on insulator
  • polysilicon thick silicon oxide
  • high-Z metals such as platinum, molybdenum, gold
  • the high stopping power mask may be placed on the top surface 10 of the top epi layer 18C after epitaxial growth, and the high stopping power mask may have openings for one or more connection regions 100 while covering the remainder of the top surface 10 of the top epi layer 18C. If a single connection region 100 includes multiple implantation regions, this process may be repeated multiple times for each implantation.
  • the blocking mask may be removed and a new blocking mask applied in a slightly different location.
  • the new- blocking mask may be added on top of the existing blocking mask without removing the existing blocking mask.
  • the blocking mask may be shifted slightly to the new implantation location.
  • connection regions 100 may be formed before or after the highly doped regions 102 (e.g., the well region 20) in different embodiments.
  • the one or more connection regions 100 may be at least partially implanted between the epi growth steps (e.g., implanted before or after the CB regions 46 are formed in the epi layer 18B and before the epi growth of the next epi layer 18C) such that a lower energy implant may be used to achieve a suitable depth 104.
  • the resulting connection region may have a narrower width than the minimum aperture feature size of the blocking mask.
  • connection regions 100 which connect the CB regions 46 to the one or more highly doped regions 102, in this case the well region 20, generally decrease switching losses and increase maximum switching speed of the CB device 80.
  • carriers from the well region 20 may flow directly to the CB regions 46 via the one or more connection regions 100 during transition of the CB device 80 from off-state (e.g., blocking state) to on-state (e.g., conducting state), and similarly, carriers from the CB regions 46 may flow directly to the well region 20 via the one or more connection regions 1 00 during transition of the CB device 80 from on-state to off-state.
  • the one or more connection regions 100 may decrease switching losses and increase switching speeds of the CB device 80 without substantially increasing the leakage current of the CB device 80.
  • the switching speed of the CB device 80 having the one or more connection regions 100 may be between approximately 10 and approximately 2000, approximately 25 and approximately 1000, approximately 50 and approximately 750, approximately 75 and approximately 500, or approximately 100 and approximately 250 times greater than the switching speed of CB devices without the one or more connection regions 100.
  • the switching speed of the CB device 80 including the one or more connection regions 100 may be at least 1 kilohertz (kHz). In some embodiments, the switching speed of the CB MOSFET device 8 may be between approximately 75 kHz and approximately 150 kHz, approximately 85 kHz and approximately 125 kHz, or approximately 95 kHz and approximately 105 kHz. CB devices utilizing floating CB regions without the disclosed connection regions 100 may have switching speeds less than approximately 1 kHz, less than approximately 750 Hz, less than approximately 500 Hz, or less than approximately 250 Hz. Accordingly, the disclosed CB device 80 having the one or more connection regions 100 may have significantly faster switching speeds than CB devices utilizing floating CB regions without the disclosed connection regions 100.
  • the one or more highly doped regions 102 may be disposed adjacent to the top surface 10 of the device layer 14.
  • the one or more highly doped regions 102 may be or may include the well region 20 (e.g., the p-type well region 20).
  • the one or more highly- doped regions 102 may be or may include the body region 36 (e.g., the p+ body region 36) the body contact region 38 (e.g., the p+ body contact region 38), and/or a junction barrier region (e.g., a junction barrier region of a junction barrier Schottky (JBS) or a merged PiN Schottky (MPS) diode). That is, the one or more connection regions 100 may be disposed adjacent to and/or may extend through (e.g., overlap with) at least a portion of the well region 20, the body region 36, and/or the body contact region 38.
  • a junction barrier region e.g., a junction barrier region of a junction barrier Schottky (JBS) or a merged PiN Schottky (MPS) diode.
  • JBS junction barrier Schottky
  • MPS merged PiN Schottky
  • the one or more highly doped regions 102 may have a dopant concentration between approximately 2xl0 lo cm “3 and approximately 5x10 20 cm “3 , approximately 5x10 16 cm “3 and approximately lxl0 19 cm “3 , or approximately l xl0 17 cm “3 and approximately 5xl0 i8 cm “3 , In some embodiments, the highly doped regions 102 may generally have a doping concentration that is at least 50% greater (e.g., between approximately 50% and 200%, or more) than the doping concentration in the CB regions 46 and/or the connection regions 100.
  • the highly doped regions 102 may generally have a doping concentration that is at least 1 xl0 lj cm "2 /thickness of the region (e.g., the CB regions 46 and/or the connection regions 100). In some embodiments, the highly doped regions 102 may generally have a doping concentration that is between approximately 1 order of magnitude and 6 orders of magnitude greater than the doping concentration in the CB regions 46 and/or the connection regions 100.
  • connection region 100 also includes a width 1 10.
  • connection regions 100 that are narrower i.e., smaller width 110 help enable the device 80 to achieve higher switching speeds with no significant impact on device blocking voltage.
  • manufacturing constraints may limit dimensions of implantation regions such that implantation regions having a width 110 less than a minimum viable width is not achievable
  • the width of the overlap forms a connection region that may have a width smaller than the minimum width of a single implantation region or blocking mask feature used to pattern such implant, enabling a narrower connection region.
  • the width 110 and the dopant concentration of the connection region 100 may be selected to maintain charge balance within the CB layers 16 (e.g., the Sower epi layers 18A and 18B) having the CB regions 46, as well as to enable desirable electrical performance of the CB device 80 (e.g., a desired blocking voltage).
  • the width 1 10 may be between approximately 1 ⁇ and approximately 10 ⁇ .
  • each implantation region may be between approximately 2 ⁇ wide and approximately 7 ⁇ wide.
  • the overlap between the implantation regions may be between approximately 0.5 ⁇ and between approximately 4 ⁇
  • the dopant concentration of the connection region 100 may be between approximately IxlO 16 cm “3 and approximately lxlO 1 ' cm “3 , approximately lxl0 lb cm° and approximately 4x10 16 cm “3 , or approximately 4x10 l6 era “3 and approximately lxl 0 17 cm “3 .
  • the dopant concentration of the connection region 100 may be equal to or less than the dopant concentration of the CB regions 46.
  • the dopant concentration of the connection region (e.g., the overlap between implantation regions) may range from approximately 0.5 times the dopant concentration of the CB layers 18 to approximately 1.2 times the dopant concentration of the CB layers 18.
  • the CB regions 46 may entirely or partially overlap with the connection region 100.
  • the CB regions 46 may entirely overlap with the connection region 100 such that the CB regions 46 extend through the width 1 10 of the connection region 100.
  • the CB regions 46 may only extend partially through the width 110 of the connection region 100.
  • the CB regions 46 may overlap with the connection region 100 by a distance 140 that is less than the width 110 of the connection region 100.
  • the distance 140 may be greater than or equal to 0.1 ⁇ . In certain embodiments, the distance 140 may be less than half of the width 110.
  • connection region 100 Although the embodiments of the CB devices 80 and 120 illustrated in FIGS. 3 and 4, respectively, include one connection region 100, it should be noted that the CB devices 80 and 120 may include any suitable number of connection regions 100.
  • FIG. 5 illustrates a cross-sectional view of the drift region 12 of an embodiment of a CB device 190 that includes the CB regions 46 and the connection region 100.
  • the multi-layer drift region 12 includes the three epi layers 18A, 18B, and 18C, and the CB regions 46 are formed in the lower epi layers 18A and 18B (i.e., CB layers 16A and 16B).
  • the connection region 100 connects two particular CB regions, 46A and 46B, with the highly doped region 102.
  • FIG. 5 includes equal potential lines 200 that indicate the electric field present in the drift region 12 of the CB device 190 under reverse bias conditions.
  • connection region 100 may increase the switching speed of the CB device 190 by providing carriers from the highly doped region 102 to the CB regions 46 without substantially changing the electric field distribution and without resultantly decreasing the blocking voltage of the CB device 190.
  • FIG. 6 illustrates an embodiment of a CB device 220 including a segmented connection region 100.
  • the connection region 100 may include a first connection segment 222 that extends from the highly doped region 102 to a CB region 46 in the second CB layer 16B.
  • the connection region 100 may include a second connection segment 224 that extends from the CB region 46 in the second CB layer 16B to a CB region 46 in the first CB layer 16A.
  • the first connection segment 222 and the second connection segment 224 are not adjoined (e.g., are staggered, are not vertically aligned).
  • the second connection segment 224 is spaced apart from the first connection segment 222 by a distance 226.
  • connection region 100 may include any suitable number of connection segments, such as two, three, four, five, or more, and the connection segments may be adjoined or not adjoined in different CB layers 16. Further, in some embodiments, the connection region 100 may include connection segments that extend through multiple CB regions 46 in the same CB layer 16. For example, as illustrated in FIG. 7, the connection region 100 may include a first connection segment 240 that extends from the highly doped region 102 to a first CB region 242 in the second CB layer 16B.
  • connection region 100 may include a second connection segment 244 that extends from the first CB region 242 in the second CB layer 16B and from a second CB region 246 in the second CB layer 16B to third and fourth CB regions 248 and 250, respectively, in the first CB layer 16A.
  • first connection segment 240 and the second connection segment 244 may not be adjoined in some embodiments. In certain embodiments, the first connection segment 240 and the second connection segment 244 may be adjoined (e.g., may at least partially overlap with one another).
  • connection segments 240, 244 having a higher aspect ratio help enable the device 220 to achieve higher switching speeds.
  • manufacturing constraints e.g., masking technology
  • the connection segments 240, 244 may include two misaligned, overlapping implantation regions. The overlap between the two implantation regions forms a connection region that may be narrower than the minimum implantation region width.
  • the highly doped connection region may be flanked on either side by low doped regions where the implantation regions do not overlap.
  • FIGS. 8-10 illustrate how connection regions or segments may be formed from multiple misaligned overlapping implantation regions.
  • FIG. 8 is a side, section view of an embodiment of an CB device 300 in which an epi layer includes first implantation regions 304 of a second conductivity type.
  • a first blocking mask 306 is applied to a top surface 308 of the epi layer 18.
  • the first blocking mask 306 includes apertures 308 of width 310.
  • An ion implantation process is used to dope the portion of the epi layer 18, forming the region 304. Specifically, ions are accelerated toward the epi layer 18. The ions do not penetrate into the portions of the epi layer 18 beneath the blocking mask 306, but where there are apertures 308, the ions travel through the aperture in the blocking mask 306 and are implanted into the epi layer 18.
  • the first implantation regions 304 have a width 312, which may be approximately equal to the width 310 of the apertures 308 in the first blocking mask 306.
  • the first implantation region 304 may have a width 312 between approximately 2 ⁇ wide and approximately 7 ⁇ wide.
  • the width 312 of the first implanted region 304 may be approximately 2.0 ⁇ , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , 4.0 ⁇ , 4.5 ⁇ , 5.0 ⁇ , 5.5 ⁇ , 6.0 ⁇ , 6.5 um, or 7.0 ⁇ .
  • the first blocking mask 306 is then removed.
  • FIG. 9 is a side, section view of the CB device 300 of FIG. 8 having a second implantation region 350 that overlaps with the first implantation region 304.
  • a second blocking mask 352 is applied to the top surface 308 of the epi layer 18.
  • the second blocking mask 352 has apertures 354 having a width 356.
  • the width 356 of the apertures 354 of the second blocking mask 352 may be the same or different from the width of the apertures of the first blocking mask.
  • the apertures 354 of the second blocking mask 352 may be misaligned with, but overlapping with the apertures of the first blocking mask.
  • An ion implantation process is used to dope the epi layer 18, forming second region 350, having a width 358.
  • the second implanted region 350 may have a width 358 between approximately 2 ⁇ wide and approximately 7 ⁇ wide.
  • the width 312 of the first implantation region 304 may be approximately 2.0 ⁇ , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , 4.0 ⁇ , 4.5 ⁇ , 5.0 ⁇ , 5.5 ⁇ , 6.0 ⁇ , 6.5 ⁇ , or 7.0 ⁇ .
  • the first and second implantation regions 304, 350 overlap one another by a width 362, forming a connection region 364.
  • the width 362 may range from approximately 0.5 ⁇ to approximately 4 ⁇ .
  • the width 362 may be approximately 0.5 ⁇ , 1.0 ⁇ , 1.5 ⁇ , 2.0 ⁇ , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , or 4.0 ⁇ . Because the width 362 of the connection region 364 may be less than the minimum aperture width 310, 356 of the first and second blocking masks, the connection region 364 may have a narrower width 362 than a connection region made with a single implantation, enabling the CB device 300 to reach faster switching speeds. Once the second implantation region 350 has been formed, the second blocking mask 352 may be removed.
  • FIG. 10 is a side, section view of the CB device 300 of FIG. 9 having overlapping first and second implantation regions 304, 350 forming the connection regions 364.
  • the connection region 364 has the width 362 and extends through the internal portion of the doped region.
  • the connection region 364 is of a second conductivity type.
  • On either side of the connection region 364 are low doped regions 366.
  • connection region 364 may range from approximately 0,5 times the dopant concentration of the CB layer to approximately 1.4 times the dopant concentration of the CB regions.
  • the connection region 364 may have a dopant concentration between approximately 0.5xl0 io cm “3 and 5x10 16 era "5 .
  • the connection region is narrower than would otherwise be possible, resulting in a CB device 300 with higher switching speeds.
  • the dopant concentrations of epi region 18 is referred to as Nl (first type of conductivity).
  • concentration of the second type of conductivity dopants in the connection region 364 is referred to as N2.
  • Whether the low doped regions 366 are of a first or second conductivity type depends on the ratio ofNl and N2. Specifically, ifN2/2 is greater than Nl, the low doped regions 366 are of the second conductivity type. However, ifN2/2 is less than Nl, the low doped regions 366 are of the first conductivity type. This assumes that both misaligned implants have identical doping profiles/concentrations.
  • FIG. 11 is a cross-sectional view of the drift region 12 of an embodiment of a CB device 400 wherein the low doped regions are of the second conductivity type.
  • N2/2 is greater thanNl.
  • the multi-layer drift region 12 includes the three epi layers 18A, 18B, and 18C.
  • the CB regions 46 are formed in the lower epi layers 18A and 18B (i.e., CB layers 16A and 16B).
  • the connection region 100 connects two particular CB regions 46 with the highly doped region 102.
  • the equal potential lines 200 indicate the electric field present in the drift region 12 of the CB device 400 under reverse bias conditions.
  • connection region 100 and adjacent low doped regions of the second conductivity type may increase the switching speed of the CB device 400 by providing carriers from the highly doped region 102 to the CB regions 46 without substantially changing the electric field distribution and without resultantly decreasing the blocking voltage of the CB device 400.
  • FIG. 12 is a cross-sectional view of the drift region 12 of an embodiment of the CB device 400 wherein the low doped regions of the connection region 100 are of the first conductivity type.
  • N2/2 is less than NJ.
  • the equal potential lines 200 are relatively unchanged as compared to the embodiment in which N2/2 is greater than NJ and the low doped regions are of the second conductivity type, shown in FIG. 1 1 .
  • the spacing between the equal potential lines 200 does not substantially change with addition of the connection region 100.
  • the connection region 100 does not substantially change or alter the strength of the electric field m the drift region 12.
  • connection region 100 and adjacent low doped regions of the first conductivity type may increase the switching speed of the CB device 400 by- providing carriers from the highly doped region 102 to the CB regions 46 without substantially changing the electric field distribution and without resultantly decreasing the blocking voltage of the CB device 400.
  • FIG. 13 is a flow chart of a process 500 for creating one or more connection regions in a CB device that include multiple intentionally misaligned and overlapping implantation regions, forming a narrow connection region flanked on either side by low doped regions.
  • a first blocking mask is applied to the top surface of the epi layer.
  • the blocking mask includes first apertures that correspond to the width and locations of the desired first implantation regions.
  • the first apertures may be between approximately 2 ⁇ wide and approximately 7 ⁇ wide.
  • the first apertures may be approximately 2.0 , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , 4.0 ⁇ , 4.5 ⁇ , 5.0 ⁇ , 5.5 ⁇ , 6.0 ⁇ , 6.5 ⁇ , or 7.0 ⁇ wide.
  • a first ion implantation process is used to dope a portion of the epi layer, forming the first implantation regions of a second conductivity type. Specifically, ions are accelerated toward the first blocking mask. The blocking mask blocks many of the ions, but where there are first apertures, the ions travel through the first apertures and into the epi layer. When the ions penetrate into the epi layer, the local area of the epi layer is doped, forming the first implantation regions.
  • the first implantation regions have a width approximately equal to the width of the apertures in the first blocking mask.
  • the first implantation region may have a width between approximately 2 ⁇ wide and approximately 7 ⁇ wide. That is, the width of the first implantation region may be approximately 2.0 ⁇ , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , 4.0 ⁇ , 4.5 ⁇ , 5.0 ⁇ , 5.5 ⁇ , 6.0 ⁇ , 6.5 ⁇ , or 7.0 ⁇ .
  • the first blocking mask is then removed (block 506).
  • a second blocking mask is applied to the top surface of the epi layer.
  • the blocking mask includes second apertures that correspond to the width and locations of the desired second implantation regions, which may be misaligned with and overlapping with the first implantation regions.
  • the second apertures may be the same size as the first apertures, or of a different size than the first apertures.
  • the second apertures may be between approximately 2 ⁇ wide and approximately 7 ⁇ wide. That is, the second apertures may be approximately 2.0 ⁇ , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , 4.0 ⁇ , 4.5 ⁇ , 5.0 ⁇ , 5.5 ⁇ , 6.0 ⁇ , 6.5 ⁇ , or 7.0 ⁇ wide.
  • a second ion implantation process is used to dope a portion of the epi layer, forming the second implantation regions of a second conductivity type.
  • ions are accelerated toward the second blocking mask. Th ough the blocking mask blocks many of the ions, the ions that travel through the second apertures into the epi layer and dope the local area of the epi layer, forming the second implantation regions.
  • the second implantation regions have a width approximately equal to the width of the apertures in the second blocking mask. For example, in some embodiments, the second implantation region may have a width between approximately 2
  • the width of the second implantation region may be approximately 2.0 ⁇ , 2.5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , 4.0 ⁇ , 4.5 ⁇ , 5.0 ⁇ , 5.5 ⁇ , 6.0 ⁇ , 6.5 ⁇ , or 7.0 ⁇ .
  • the first and second implantation regions overlap one another, forming a connection region extending through the connection region.
  • the width of the connection region may range from approximately 0.5 ⁇ to approximately 4 um.
  • the width of the connection region may be approximately 0.5 ⁇ , 1.0 ⁇ , 1.5 ⁇ , 2.0 ⁇ , 2,5 ⁇ , 3.0 ⁇ , 3.5 ⁇ , or 4.0 ⁇ . Because the width of the connection region may be less than the mmimum aperture width of the first and second blocking masks, the connection region may have a narrower width than connection regions made with a single implantation region, enabling the CB device to reach faster switching speeds.
  • connection regions made of two misaligned and overlapping implantation regions are formed by the overlap of the two implantation regions.
  • the connection region is flanked on two sides by first and second low doped regions where the first and second implantation regions do not overlap.
  • the connection region may be narrower than a similar connection region made with a single implantation using a blocking mask (e.g., hard mask with apertures larger than the resulting connection region).
  • Tins written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods.
  • the patentable scope of the invention is defined by the claims, and may mclude other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.

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EP18859235.6A 2017-09-21 2018-07-20 Systeme und verfahren für ladungsausgeglichene halbleiterleistungsbauelemente mit schneller schaltfähigkeit Pending EP3685433A4 (de)

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Publication number Priority date Publication date Assignee Title
US11233157B2 (en) * 2018-09-28 2022-01-25 General Electric Company Systems and methods for unipolar charge balanced semiconductor power devices
US10937869B2 (en) * 2018-09-28 2021-03-02 General Electric Company Systems and methods of masking during high-energy implantation when fabricating wide band gap semiconductor devices

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW437099B (en) * 1997-09-26 2001-05-28 Matsushita Electronics Corp Non-volatile semiconductor memory device and the manufacturing method thereof
DE19839970C2 (de) * 1998-09-02 2000-11-02 Siemens Ag Randstruktur und Driftbereich für ein Halbleiterbauelement sowie Verfahren zu ihrer Herstellung
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
KR100297705B1 (ko) 1999-03-29 2001-10-29 김덕중 낮은 온저항과 높은 항복전압을 갖는 전력용 반도체소자
DE19943143B4 (de) 1999-09-09 2008-04-24 Infineon Technologies Ag Halbleiterbauelement für hohe Sperrspannungen bei gleichzeitig niedrigem Einschaltwiderstand und Verfahren zu dessen Herstellung
DE10306597B4 (de) 2003-02-17 2005-11-17 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur mit erhöhter Durchbruchspannung durch tieferliegenden Subkollektorabschnitt
US8692324B2 (en) 2005-07-13 2014-04-08 Ciclon Semiconductor Device Corp. Semiconductor devices having charge balanced structure
US20080014693A1 (en) 2006-07-12 2008-01-17 General Electric Company Silicon carbide vertical mosfet design for fast switching applications
ITTO20070392A1 (it) * 2007-06-05 2008-12-06 St Microelectronics Srl Dispositivo di potenza a bilanciamento di carica comprendente strutture colonnari e avente resistenza ridotta
JP5472862B2 (ja) * 2009-03-17 2014-04-16 三菱電機株式会社 電力用半導体装置の製造方法
US9087893B2 (en) 2010-01-29 2015-07-21 Fuji Electric Co., Ltd. Superjunction semiconductor device with reduced switching loss
US8278709B2 (en) 2010-10-05 2012-10-02 Himax Technologies Limited High voltage metal-oxide-semiconductor transistor with stable threshold voltage and related manufacturing method
US8698245B2 (en) 2010-12-14 2014-04-15 International Business Machines Corporation Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure
JP2012169384A (ja) * 2011-02-11 2012-09-06 Denso Corp 炭化珪素半導体装置およびその製造方法
US8524586B2 (en) 2011-04-20 2013-09-03 Richtek Technology Corporation Semiconductor overlapped PN structure and manufacturing method thereof
US8785279B2 (en) * 2012-07-30 2014-07-22 Alpha And Omega Semiconductor Incorporated High voltage field balance metal oxide field effect transistor (FBM)
KR101779237B1 (ko) 2013-06-04 2017-09-19 매그나칩 반도체 유한회사 반도체 전력소자 및 이를 제조하는 방법
US10199459B2 (en) * 2013-07-19 2019-02-05 Great Wall Semiconductor Corporation Superjunction with surrounding lightly doped drain region
KR101514537B1 (ko) * 2013-08-09 2015-04-22 삼성전기주식회사 전력 반도체 소자 및 그 제조 방법
US9293528B2 (en) * 2013-12-31 2016-03-22 Infineon Technologies Austria Ag Field-effect semiconductor device and manufacturing therefor
US10468479B2 (en) * 2014-05-14 2019-11-05 Infineon Technologies Austria Ag VDMOS having a drift zone with a compensation structure
US9831330B2 (en) 2015-03-05 2017-11-28 Infineon Technologies Americas Corp. Bipolar semiconductor device having a deep charge-balanced structure
US9881997B2 (en) * 2015-04-02 2018-01-30 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
US9735237B2 (en) 2015-06-26 2017-08-15 General Electric Company Active area designs for silicon carbide super-junction power devices
US10243039B2 (en) 2016-03-22 2019-03-26 General Electric Company Super-junction semiconductor power devices with fast switching capability
JP6809071B2 (ja) * 2016-09-14 2021-01-06 富士電機株式会社 半導体装置および半導体装置の製造方法

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CN111133567A (zh) 2020-05-08
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US10600649B2 (en) 2020-03-24
CN111133567B (zh) 2023-10-20
WO2019060032A1 (en) 2019-03-28
JP7257390B2 (ja) 2023-04-13
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TW201923974A (zh) 2019-06-16
TWI798254B (zh) 2023-04-11

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