EP3350798B1 - Apparatus and methods for driving displays - Google Patents

Apparatus and methods for driving displays Download PDF

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Publication number
EP3350798B1
EP3350798B1 EP16847345.2A EP16847345A EP3350798B1 EP 3350798 B1 EP3350798 B1 EP 3350798B1 EP 16847345 A EP16847345 A EP 16847345A EP 3350798 B1 EP3350798 B1 EP 3350798B1
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Prior art keywords
voltage
gate
switch
display
during
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German (de)
English (en)
French (fr)
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EP3350798A1 (en
EP3350798A4 (en
EP3350798C0 (en
Inventor
Kenneth R. Crounse
Teck Ping SIM
Karl Raymond Amundson
Zdzislaw Jan Szymborski
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E Ink Corp
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E Ink Corp
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Priority claimed from US15/014,236 external-priority patent/US10475396B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0473—Use of light emitting or modulating elements having two or more stable states when no power is applied
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/048—Preventing or counteracting the effects of ageing using evaluation of the usage time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • This invention relates to methods for driving bistable electro-optic displays, and to apparatus for use in such methods. More specifically, this invention relates to driving methods and apparatus for adjusting the gate on voltage value after an active update to reduce transistor degradation associated with voltage stress that may be caused by remnant voltage discharging.
  • the present invention provides an apparatus for driving an electrophoretic display, in accordance with claim 1.
  • the present invention also provides a method for driving an electrophoretic display, in accordance with claim 3.
  • Electro-optic displays comprise a layer of electro-optic material, a term which is used herein in its conventional meaning in the imaging art to refer to a material having first and second display states differing in at least one optical property, the material being changed from its first to its second display state by application of an electric field to the material.
  • the electro-optic medium may be a solid (such displays may hereinafter for convenience be referred to as "solid electro-optic displays"), in the sense that the electro-optic medium has solid external surfaces, although the medium may, and often does, have internal liquid- or gas-filled spaces.
  • solid electro-optic displays includes encapsulated electrophoretic displays, encapsulated liquid crystal displays, and other types of displays discussed below.
  • the optical property may be color perceptible to the human eye, it may be another optical property, such as optical transmission, reflectance, luminescence or, in the case of displays intended for machine reading, pseudo-color in the sense of a change in reflectance of electromagnetic wavelengths outside the visible range.
  • gray state is used herein in its conventional meaning in the imaging art to refer to a state intermediate two extreme optical states of a pixel, and does not necessarily imply a black-white transition between these two extreme states.
  • extreme states are white and deep blue, so that an intermediate "gray state” would actually be pale blue. Indeed, as already mentioned the transition between the two extreme states may not be a color change at all.
  • bistable and “bistability” are used herein in their conventional meaning in the art to refer to displays comprising display elements having first and second display states differing in at least one optical property, and such that after any given element has been driven, by means of an addressing pulse of finite duration, to assume either its first or second display state, after the addressing pulse has terminated, that state will persist for at least several times, for example at least four times, the minimum duration of the addressing pulse used to change the state of the display element.
  • some particle-based electrophoretic displays capable of gray scale are stable not only in their extreme black and white states but also in their intermediate gray states, and the same is true of some other types of electro-optic displays. This type of display is properly called “multi-stable” rather than bistable, although for convenience the term “bistable” may be used herein to cover both bistable and multi-stable displays.
  • the term "remnant voltage” is used herein to refer to a persistent or decaying electric field that may remain in an electro-optic display after an addressing pulse (a voltage pulse used to change the optical state of the electro-optic medium) is terminated.
  • the rate of decay of a remnant voltage of an electro-optic display may become low as the remnant voltage approaches a threshold value.
  • Even low remnant voltages e.g., remnant voltages of approximately 200 mV or less
  • remnant voltage The persistence of the remnant voltage for a significant time period applies a "remnant impulse" to the electro-optic medium, and strictly speaking this remnant impulse, rather than the remnant voltage, may be responsible for the effects on the optical states of electro-optic displays normally considered as caused by remnant voltage.
  • remnant voltages can lead to undesirable effects on the images displayed on electro-optic displays, including, without limitation, so-called “ghosting” phenomena, in which, after the display has been rewritten, traces of the previous image are still visible.
  • a "shift" in the optical state associated with an addressing pulse refers to a situation in which a first application of a particular addressing pulse to an electro-optic display results in a first optical state (e.g., a first gray tone), and a subsequent application of the same addressing pulse to the electro-optic display results in a second optical state (e.g., a second gray tone).
  • Remnant voltages may give rise to shifts in optical state because the voltage applied to a pixel of the electro-optic display during application of an addressing pulse includes the sum of the remnant voltage and the voltage of the addressing pulse.
  • a “drift” in the optical state of a display over time refers to a situation in which the optical state of an electro-optic display changes while the display is at rest (e.g., during a period in which an addressing pulse is not applied to the display). Remnant voltages may give rise to drifts in optical state because the optical state of a pixel may depend on the pixel's remnant voltage, and a pixel's remnant voltage may decay over time.
  • edge ghosting a type of ghosting in which an outline (edge) of a portion of a previous image remains visible.
  • impulse is used herein in its conventional meaning in the imaging art of the integral of voltage with respect to time.
  • bistable electro-optic media act as charge transducers, and with such media an alternative definition of impulse, namely the integral of current over time (which is equal to the total charge applied) may be used.
  • the appropriate definition of impulse should be used, depending on whether the medium acts as a voltage-time impulse transducer or a charge impulse transducer.
  • electro-optic displays are known.
  • One type of electro-optic display is a rotating bichromal member type as described, for example, in U.S. Pat. Nos. 5,808,783 ; 5,777,782 ; 5,760,761 ; 6,054,071 6,055,091 ; 6,097,531 ; 6,128,124 ; 6,137,467 ; and 6,147,791 (although this type of display is often referred to as a "rotating bichromal ball" display, the term "rotating bichromal member" is preferred as more accurate since in some of the patents mentioned above the rotating members are not spherical).
  • Such a display uses a large number of small bodies (which may be, without limitation, spherical or cylindrical) which have two or more sections with differing optical characteristics, and an internal dipole. These bodies are suspended within liquid-filled vacuoles within a matrix, the vacuoles being filled with liquid so that the bodies are free to rotate. The appearance of the display is changed by applying an electric field thereto, thus rotating the bodies to various positions and varying which of the sections of the bodies is seen through a viewing surface.
  • This type of electro-optic medium may be bistable.
  • electro-optic display uses an electrochromic medium, for example an electrochromic medium in the form of a nanochromic film comprising an electrode formed at least in part from a semi-conducting metal oxide and a plurality of dye molecules capable of reversible color change attached to the electrode; see, for example O'Regan, B., et al., Nature 1991, 353, 737 ; and Wood, D., Information Display, 18(3), 24 (March 2002 ). See also Bach, U., et al., Adv. Mater., 2002, 14(11), 845 . Nanochromic films of this type are also described, for example, in U.S. Pat. No. 6,301,038 , International Application Publication No. WO 01/27690 , and in U.S. Patent Application 2003/0214695 . This type of medium may be bistable.
  • electro-optic display is the particle-based electrophoretic display, in which a plurality of charged particles move through a suspending fluid under the influence of an electric field.
  • Electrophoretic displays can have attributes of good brightness and contrast, wide viewing angles, state bistability, and low power consumption when compared with liquid crystal displays. Nevertheless, there may be problems with the long-term image quality of some particle-based electrophoretic displays. For example, particles that make up some electrophoretic displays may settle, resulting in inadequate service-life for such displays.
  • electrophoretic media may include a suspending fluid.
  • This suspending fluid may be a liquid, but electrophoretic media can be produced using gaseous suspending fluids; see, for example, Kitamura, T., et al., "Electrical toner movement for electronic paper-like display", IDW Japan, 2001, Paper HCS1-1 , and Yamaguchi, Y., et al., "Toner display using insulative particles charged triboelectrically", IDW Japan, 2001, Paper AMD4-4 ).
  • Some gas-based electrophoretic media may be susceptible to the same types of problems as some liquid-based electrophoretic media due to particle settling, when the media are used in an orientation which permits such settling, for example in a sign where the medium is disposed in a vertical plane. Indeed, particle settling appears to be a more serious problem in some gas-based electrophoretic media than in some liquid-based ones, since the lower viscosity of gaseous suspending fluids as compared with liquid ones allows more rapid settling of the electrophoretic particles.
  • Encapsulated electrophoretic media comprise numerous small capsules, each of which itself comprises an internal phase containing electrophoretically-mobile particles in a fluid medium, and a capsule wall surrounding the internal phase. Typically, the capsules are themselves held within a polymeric binder to form a coherent layer positioned between two electrodes.
  • the charged particles and the fluid are not encapsulated within microcapsules but instead are retained within a plurality of cavities formed within a carrier medium, typically a polymeric film.
  • a carrier medium typically a polymeric film.
  • the walls surrounding the discrete microcapsules in an encapsulated electrophoretic medium could be replaced by a continuous phase, thus producing a so-called polymer-dispersed electrophoretic display, in which the electrophoretic medium comprises a plurality of discrete droplets of an electrophoretic fluid and a continuous phase of a polymeric material, and that the discrete droplets of electrophoretic fluid within such a polymer-dispersed electrophoretic display may be regarded as capsules or microcapsules even though no discrete capsule membrane is associated with each individual droplet; see for example, the aforementioned 2002/0131147. Accordingly, for purposes of the present application, such polymer-dispersed electrophoretic media are regarded as sub-species of encapsulated electrophoretic media.
  • microcell electrophoretic display A related type of electrophoretic display is a so-called "microcell electrophoretic display.”
  • the charged particles and the suspending fluid are not encapsulated within microcapsules but instead are retained within a plurality of cavities formed within a carrier medium, e.g., a polymeric film.
  • a carrier medium e.g., a polymeric film.
  • microcell electrophoretic displays can refer to all such display types, which may also be described collectively as “microcavity electrophoretic displays” to generalize across the morphology of the walls.
  • electro-optic display is an electro-wetting display developed by Philips and described in Hayes, R. A., et al., "Video-Speed Electronic Paper Based on Electrowetting," Nature, 425, 383-385 (2003 ). It is shown in copending application Ser. No. 10/711,802, filed Oct. 6, 2004 , that such electro-wetting displays can be made bistable.
  • bistable ferroelectric liquid crystal displays are known in the art and have exhibited remnant voltage behavior.
  • electrophoretic media may be opaque (since, for example, in many electrophoretic media, the particles substantially block transmission of visible light through the display) and operate in a reflective mode
  • some electrophoretic displays can be made to operate in a so-called "shutter mode" in which one display state is substantially opaque and one is light-transmissive. See, for example, the patents U.S. Pat. Nos. 6,130,774 and 6,172,798 , and U.S. Pat. Nos. 5,872,552 ; 6,144,361 ; 6,271,823 ; 6,225,971 ; and 6,184,856 .
  • Dielectrophoretic displays which are similar to electrophoretic displays but rely upon variations in electric field strength, can operate in a similar mode; see U.S. Pat. No. 4,418,346 .
  • Other types of electro-optic displays may also be capable of operating in shutter mode.
  • An encapsulated or microcell electrophoretic display may not suffer from the clustering and settling failure mode of traditional electrophoretic devices and may provide further advantages, such as the ability to print or coat the display on a wide variety of flexible and rigid substrates.
  • printing is intended to include all forms of printing and coating, including, but without limitation: pre-metered coatings such as patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; silk screen printing processes; electrostatic printing processes; thermal printing processes; inkjet printing processes; electrophoretic deposition; and other similar techniques.
  • pre-metered coatings such as patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating
  • roll coating such as knife over roll coating, forward and reverse roll coating
  • gravure coating dip coating
  • spray coating meniscus coating
  • spin coating spin coating
  • brush coating air knife coating
  • silk screen printing processes
  • the bistable or multi-stable behavior of particle-based electrophoretic displays, and other electro-optic displays displaying similar behavior is in marked contrast to that of liquid crystal displays ("LCDs"). Twisted nematic liquid crystals are not bi- or multi-stable but act as voltage transducers, so that applying a given electric field to a pixel of such a display produces a specific gray level at the pixel, regardless of the gray level previously present at the pixel. Furthermore, LC displays are only driven in one direction (from non-transmissive or "dark” to transmissive or “light”), the reverse transition from a lighter state to a darker one being effected by reducing or eliminating the electric field.
  • bistable electro-optic displays act, to a first approximation, as impulse transducers, so that the final state of a pixel depends not only upon the electric field applied and the time for which this field is applied, but also upon the state of the pixel prior to the application of the electric field.
  • a high-resolution display may include individual pixels which are addressable without interference from adjacent pixels.
  • One way to obtain such pixels is to provide an array of non-linear elements, such as transistors or diodes, with at least one non-linear element associated with each pixel, to produce an "active matrix" display.
  • An addressing or pixel electrode, which addresses one pixel, is connected to an appropriate voltage source through the associated non-linear element.
  • the non-linear element is a transistor
  • the pixel electrode may be connected to the drain of the transistor, and this arrangement will be assumed in the following description, although it is essentially arbitrary and the pixel electrode could be connected to the source of the transistor.
  • the pixels may be arranged in a two-dimensional array of rows and columns, such that any specific pixel is uniquely defined by the intersection of one specified row and one specified column.
  • the sources of all the transistors in each column may be connected to a single column electrode, while the gates of all the transistors in each row may be connected to a single row electrode; again the assignment of sources to rows and gates to columns may be reversed if desired.
  • the display may be written in a row-by-row manner.
  • the row electrodes are connected to a row driver, which may apply to a selected row electrode a voltage such as to ensure that all the transistors in the selected row are conductive, while applying to all other rows a voltage such as to ensure that all the transistors in these non-selected rows remain non-conductive.
  • the column electrodes are connected to column drivers, which place upon the various column electrodes voltages selected to drive the pixels in a selected row to their desired optical states.
  • the aforementioned voltages are relative to a common front electrode which may be provided on the opposed side of the electro-optic medium from the non-linear array and extends across the whole display.) After a pre-selected interval known as the "line address time,” a selected row is deselected, another row is selected, and the voltages on the column drivers are changed so that the next line of the display is written.
  • a preferred embodiment for dissipating remnant voltage brings all pixel transistors into conduction for an extended time.
  • all pixel transistors may be brought into conduction by bringing gate line (as referred to herein as "select line”) voltage relative to the source line voltages to values that bring pixel transistors to a state where they are relatively conductive compared to the non-conductive state used to isolate pixels from source lines as part of normal active-matrix drive.
  • select line gate line
  • a specially designed circuitry may provide for addressing all pixels at the same time.
  • select line control circuitry typically does not bring all gate lines to values that achieve the above-mentioned conduction state for all pixel transistors.
  • a convenient way to achieve this condition is afforded by select line driver chips that have an input control line that allows an external signal to impose a condition where all select line outputs receive a voltage supplied to the select driver chosen to bring pixel transistors into conduction. By applying the appropriate voltage value to this special input control line, all transistors may be brought into conduction.
  • some select drivers have a "Xon" control line input.
  • the gate on voltage is routed to all the select lines.
  • the description of this invention is written for backplane that employs n-type pixel transistors. In this case the gate on voltage is positive.
  • backplane made with p-type pixel transistors all the methods described here can be employed by inverting all the voltages described and shown in this invention. In this case the gate on voltage would be negative.
  • the gate on voltage is an important voltage for the purpose of dissipating remnant voltage of an electro-optic active matrix display.
  • Application of the gate on voltage across the entire display is integral to the "post-drive discharge” which is typically applied at the end of the "active drive phase” (also referred to herein as “image update” or “active update period”).
  • the "post-drive discharge phase” (also referred to herein as “remnant voltage discharge phase” or “remnant voltage discharging”) is part of the "voltage decay phase” and, if the post-drive discharge phase is equal to the voltage decay phase, these terms may be used interchangeably (and herein are used interchangeably).
  • Post-drive discharging may be performed after every active update, after a specified number of active updates, after a specified period of time or when requested by a user. Further, post-drive discharging may be interrupted by an active update such that the gate on voltage value may not reach a zero value.
  • the present invention relates to methods for adjusting the gate on voltage value after the active update phase.
  • the optimal decay rate for dissipating remnant voltage in a display may be determined empirically by balancing the acceptable level of discharging efficacy and the impact on the pixel transistor's transconductance.
  • One advantage of this invention is that the post-drive discharge may be achieved at a lower voltage which will reduce pixel transistor degradation and prevent optical shifting.
  • Electro-optic displays may receive power from external electronics, such as a display controller and supply voltages from "power management” circuitry.
  • the power management circuitry may supply multiple voltages, including “gate on voltage” supplied to gate lines (also referred to herein as “select lines”) to bring transistors on selected lines into conduction.
  • the power management circuitry may be discrete components or an integrated circuit (e.g., Power Management Integrated Circuit (“PMIC”)). Additional circuitry may include pulldown resistor(s) and/or pulldown capacitor(s).
  • FIG. 1A is a schematic of a simple prior art gate on voltage electrical circuit of an electro-optic display using a PMIC 102 that shows the gate on voltage line 104 from the PMIC 102 to the gate driver 106 of the active matrix display.
  • the circuitry of FIG. 1 allows for controlling the gate on voltage 104 at the end of an active drive by changing the value of the pull down resistor R 108. A high value for R 108 would slow the gate on voltage decay rate while a low value of R 108 would speed up the gate on voltage decay rate.
  • the pulldown resistor (“R") 108 will cause the gate on line 104 to decay exponentially to zero volts with a time constant given by the resistor value ("R") times the line capacitance ("C").
  • the post-drive discharge method described in US 2016/0225321 A1 takes advantage of the slow decay in the gate on voltage.
  • the gate on voltage is allowed to decay typically through resistors connected to ground.
  • all active-matrix select lines are brought to the gate on voltage, which decay to ground from its value during active display driving.
  • FIG. 1B is a graph showing gate on voltage versus time during an active update and a voltage decay phase, which includes a post-drive discharge phase, where the gate on voltage decays exponentially to ground.
  • a "post-drive discharge" period is defined as starting at a time t 1 and ending at a time t 2 .
  • the time t 1 may be as small as zero, in which case the post-drive discharge begins immediately after the update, or may be delayed until the gate on voltage value decays or decreases to a preferred value.
  • the time t 2 is chosen to be large enough that the post-drive discharge is effective in sufficiently reducing charge polarization in the display or, if time allows, until the gate on voltage decays to zero volts.
  • the simplest implementation of post-drive discharge is to allow the "gate on" voltage to decay exponentially during the post-drive discharge. The higher, initial voltage values are sufficient for the timely draining of remnant voltage, even if, the lower, later voltage values may be too small to enable timely draining of remnant voltage. Further, it advantageous to minimize the time that all select lines are turned on to enable sufficient remnant voltage discharging, but no longer than that.
  • This invention controls the "gate on” voltage to achieve these advantages by shaping the time profile of the "gate on” voltage during the post-drive discharge phase.
  • T m is the total time that the "gate on” voltage lies between a low voltage magnitude (V L ) and a high voltage magnitude (V H ) within a time domain starting at the end of a display update and up to a time t 2 after the end of the update
  • T h is the total time that the "gate on” voltage is greater than V H
  • t 2 is the time of the end of post-drive discharge when it is not interrupted by other display processes such as a next image update.
  • the values V L and V H may be later defined or bounded based upon display performance and usage. Assigning values for V L and V H is described in more detail below.
  • the voltages are defined relative to another voltage and are all relative to the "zero voltage” or “ground” for the driving electronics (source and/or select drivers and display controller).
  • K natural Natural K
  • K natural ln V H V L ln V 0 V H
  • V 0 the "gate on” voltage applied during an image update or active update (as described above, all voltages are defined relative to the "gate off” voltage for the display under consideration).
  • ⁇ K K natural
  • K, K natural and alpha K K natural
  • a preferred voltage profile has alpha greater than 2, alpha greater than 5 or, preferably, alpha greater than 20, and where the values of V L and V H meet at least 2 of the following constraints: 1) V L is at least 5% of V 0 ; 2) V H is at less than 80% of V 0 ; 3) V H is greater than V L ; and 4) (V H - V L )/[( V H + V L )/2] > 0.1.
  • the fourth constraint may be met to assure that the separation between V H and V L is significant compared to the average of V H and V L .
  • FIG. 1C is a graph showing gate on voltage versus time during an active update and a voltage decay phase having a preferred voltage profile.
  • the dashed line previously depicted and described in FIG. 1B , shows a typical exponential decay after an active update.
  • the solid line shows an example of a more advantageous voltage profile of a post-drive discharge phase where the gate on voltage value rapidly decays or is reduced to a lower value, then decays from this reduced value over time of post-drive discharge.
  • the initial rapid reduction of the gate on value after the active update is completed prior to "turning on" all the select lines.
  • all select lines may be turned on after the gate on voltage value is initially reduced and has decayed to a desired value or after a predetermined time. All select lines may be turned off (t 2 ) after post-drive discharge is effective in sufficiently reducing charge polarization in the display or, alternatively, after the gate on voltage decays to zero volts.
  • FIG. 2A is a schematic of a simple prior art electrical circuit layout derived from that of FIG. 1A by adding a "single pole, single throw” switch (“SW1") 210 (which, as shown, is “open”) between the PMIC 202 and the gate driver 206.
  • SW1 single pole, single throw
  • the circuit actively drives the gate driver 206.
  • the SW1 switch 210 is opened (at the end of the active drive), the PMIC 202 will cease to drive the gate high voltage 206 and the gate on voltage decay rate will be determined by the pulldown resistor R 208 and the various capacitances experienced by the gate on line 204.
  • FIG. 2B is a graphical schematic depicting the gate on voltage over time of the circuit of FIG. 2A during the active drive phase 220 when the SW1 switch is closed and the voltage decay phase 222 when the SW 1 switch is open.
  • FIG. 3A is a schematic of a gate on voltage electrical circuit according to a background example not part of the claimed invention .
  • FIG. 3A shows the gate on voltage line 304 with a first "single pole, single throw” switch (“SW1") 310 from the PMIC 302 to the gate driver 306 of the active matrix display.
  • the circuitry further comprises a resistor R 308, a second "single pole, double throw” switch (“SW2”) 312 (which, as shown, is at position "a”) and a pulldown capacitor (“Ci”) 314.
  • SW 1 and SW2 are programmed to open and close approximately simultaneously, such that only one switch will be engaged at a time. In operation, SW 1 closes and SW2 opens during active display driving while SW 1 opens and SW2 closes during voltage decay phase and post-drive discharging.
  • SW1 is an example of a single pole, single throw switch where it is only connected when the closed position.
  • SW2 is an example of a single pole, double throw switch where it switches between two points such that it is always connected to either position "a" or position "b".
  • the gate on voltage value may be reduced to a lower value and, then, may decay from this reduced voltage value.
  • FIG. 3B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 3A during the active drive phase 320, when the SW1 switch is closed and the SW2 switch is in position "a", and the voltage decay phase 322, when the SW1 switch is open and the SW2 switch is connected to position "b".
  • the PMIC drives the gate driver 306.
  • the voltage value is pulled quickly to a smaller voltage value (i.e., V 0 C/(C+ C 1 )) and decays from this smaller value 322 at a rate determined by pulldown resistor R 308 and capacitance of C and C 1 .
  • FIG. 4A is a schematic of a gate on voltage electrical circuit according to another background example not part of the claimed invention .
  • FIG. 4A shows the gate on voltage line 404 with a first switch (“SW1") 410 from the PMIC 402 to the gate driver 406 of the active matrix display.
  • the circuitry further comprises a resistor R 408, a second switch (“SW2") 412 (which, as shown, is in position "a"), a pulldown capacitor (“C 1 ”) 414 and a second pulldown resistor (“R 1 ”) 416.
  • the pulldown capacitor C 1 414 and pulldown resistor R 1 416 are in series with SW2 412; however, their positions in relation to SW2 may be swapped.
  • the PMIC drives the gate driver 406 at the active drive gate on voltage value and charges capacitor C 1 414.
  • the gate on voltage value is reduced to the value of capacitor C 1 414 and decays at rate determined by resistors R 408 and R 1 416.
  • the addition of the capacitor C 1 and resistors R and R 1 allows for a greater degree of control over the initial reduction and the decay rate of the gate on voltage value.
  • FIG. 5A is a schematic of a gate on voltage electrical circuit according to another background example not part of the claimed invention that is equivalent to FIG. 3A .
  • FIG. 5A shows the gate on voltage line 504 with a first switch (“SW1") 510 from the PMIC 502 to the gate driver 506 of the active matrix display.
  • the circuitry further comprises a second single pole, double throw switch (“SW2") 512 (which, as shown, is in position "a”) positioned on the gate on voltage line 504.
  • SW2 512 engages a pulldown resistor R 508 and a pulldown capacitor C 1 514.
  • the active drive phase as depicted in FIG. 3B 320
  • capacitor C 1 514 will be charged.
  • the voltage decay phase (as depicted in FIG. 3B 322), when SW1 is open and SW2 is in position "b", the voltage value will initially drop to the value of capacitor C 1 514, then decay at a rate determined by resistor R508.
  • the PMIC may drive the gate on voltage at +22 volts.
  • a gate on voltage value of +22 volts is excessive and a reduced gate high voltage value is preferred.
  • remnant voltage discharge may be achieved by using a voltage value of about +8 volts.
  • a preferred circuit of FIG. 5A includes a capacitor C 1 sufficient to bring the gate on voltage down quickly to about 10 to 12 volts after the active drive phase.
  • the preferred capacitor C 1 value is about equal to the capacitance of the gate on line when it is attached to the display (SW2 is in position "b") but the PMIC is disconnected (SW1 is in position "b").
  • a single capacitance value C 1 will not apply to all displays, but may be selected based on the desired initial voltage drop.
  • resistor R 508 a single resistor value will not apply to all displays, but may be selected based on the desired voltage decay rate.
  • FIG. 5B is a schematic of a gate on voltage electrical circuit according to another background example not part of the claimed invention that is equivalent to FIG. 4A .
  • FIG. 5B is a schematic of the electrical circuitry of FIG. 5A further comprising a pulldown resistor Ri 516.
  • SW2 512 engages a pulldown resistor R 508, pulldown capacitor Ci 514 and pulldown resistor Ri 516.
  • R 508 and R 1 516 is a schematic of the electrical circuitry of FIG. 5A further comprising a pulldown resistor Ri 516.
  • SW2 512 engages a pulldown resistor R 508, pulldown capacitor Ci 514 and pulldown resistor Ri 516.
  • the active drive phase as depicted in FIG. 4B 420
  • capacitor C 1 514 will discharge to 0V.
  • the voltage decay phase depicted in FIG. 4B 422
  • the voltage value will initially drop to the value of capacitor C 1 514, then decay at a rate determined by R 508 and R 1 516.
  • FIG. 6A is a schematic of a gate on voltage electrical circuit according to an embodiment of the present invention.
  • FIG. 6A shows the gate on voltage line 604 with a first switch (“SW1") 610 from the PMIC 602 to the gate driver 606 of the active matrix display.
  • the circuitry further comprises a pulldown resistor R 608, a pulldown capacitor (“Ci”) 614, a second pulldown resistor (“Ri”) 618, a second pulldown capacitor (“Cz”) 616, and a second switch (“SW2”) 612 (which, as shown, is "open") positioned between the resistor R 1 618 and the pulldown capacitor C 2 616.
  • the pulldown capacitor C 1 614, the pulldown resistor R 1 618 and the pulldown capacitor C 2 616 are in series.
  • the PMIC drives the gate driver 606 at the gate on voltage value for the active driving and charges capacitors C 1 and C 2 , to voltage values that sum up to the "gate on" voltage value.
  • the gate on voltage value drops to the level of the voltage that was across C 1 during the active drive and then decays from this lower value.
  • capacitors C 1 and C 2 and resistors R and R 1 allow for a greater degree of control over the initial reduction in the gate on voltage value, both in time and amount of reduction, and the rate of decay after the initial drop in value. These values may be set to optimize the reduction in voltage value during the voltage decay phase, or one or both of these resistors could be removed from the electrical circuit.
  • the present invention provides methods of driving a bistable electro-optic display having a plurality of pixels in an active matrix array.
  • active matrix transistors include amorphous silicon, microcrystalline, poly silicon, and organic among others.
  • Transistors in an active matrix display are typically designed to support an ON:OFF ratio of 1:1000 as most active matrix displays have about 1000 rows.
  • n-channel (“n-type”) amorphous silicon thin film transistor (“a-Si TFT”) in an active matrix display the transistor is in its ON state (row is selected) when there is a positive voltage on the gate-to-source and is in its OFF state when there is a negative voltage on the gate-to-source.
  • n-type thin film pixel transistors typically experience a positive to negative charge ratio of 1: 1000.
  • p-type a-Si TFT in an active matrix display
  • the p-type transistor is in its ON state when there is a negative voltage on the gate-to-source and is in its OFF state when there is a positive voltage on the gate-to-source.
  • p-type thin film pixel transistors typically experience a negative to positive charge ratio of 1: 1000.
  • the ON:OFF ratio is altered so that the transistor is ON more often than the normal ratio, the transistor may degrade and adversely affect the optical performance of the display.
  • Amorphous silicon transistors are highly susceptible to degradation due to atypical charge biasing.
  • One method for reducing this type of transistor degradation is to standardize the ON:OFF ratio by turning the transistor to its OFF position so that the ON:OFF ratio will be closer to its typical value of 1:1000, as described more fully herein.
  • Charge biasing may occur when remnant voltage is discharged from electro-optic displays according to techniques disclosed herein and in the aforementioned US 2016/0225321A1 .
  • a remnant voltage of a pixel of an electro-optic display may be discharged by activating the pixel's transistor (i.e., turning all transistors ON) and setting the voltages of the front and rear electrodes of the pixel to approximately a same value for a period of time.
  • the amount of remnant voltage discharged by a pixel during a remnant voltage discharge pulse may depend, at least in part, on the rate at which the pixel discharges the remnant voltage, and on the duration of the remnant voltage discharge pulse.
  • the duration of the period during which a remnant voltage discharge pulse is applied may be at least 50 ms, at least 100 ms, at least 300 ms, at least 500 ms, at least 1 sec or any other suitable duration.
  • all pixel transistors may be brought into conduction by bringing gate line voltage relative to the source line voltages to values that bring pixel transistors to a state where they are relatively conductive compared to the non-conductive state used to isolate pixels from source lines as part of normal active-matrix drive.
  • this may be achieved by bringing gate lines to values substantially higher than source line voltage values.
  • p -type thin film pixel transistors this may be achieved by bringing gate lines to values substantially lower than source line voltage values.
  • all pixel transistors may be brought into conduction by bringing gate line voltages to zero and source line voltages to a negative (or, for p -type transistors, a positive) voltage.
  • select line control circuitry typically does not bring all gate lines to values that achieve the above-mentioned conduction state for all pixel transistors.
  • select line driver chips that have an input control line that allows an external signal to impose a condition where all select line outputs receive a voltage supplied to the select driver chosen to bring pixel transistors into conduction.
  • select driver chips By applying the appropriate voltage value to this special input control line, all transistors may be brought into conduction.
  • some select drivers have a "Xon" control line input. By choosing a voltage value to input to the Xon pin input to the select drivers, the "gate high" voltage is routed to all the select lines and turns all transistors to the ON state.
  • the positive to negative charge ratio experienced by, for example, the n-type transistors may change from approximately 1:1000 to approximately 1:10 or even 1:1.
  • This atypical charge bias may cause transistor degradation and reduced display performance.
  • the current and voltage ("IV") curve of a display shifts in value. If the IV curve shifts to a higher value, more voltage is needed to activate the transistor switch. The effect of the shift in the IV curve may be shown by optically measuring resultant graytone shift and ghosting shift in display reflectance (measured in L-star value (L*)).
  • Graytone shift measures 16 of these transitions.
  • ghost shift measures a property of the remaining 240 transitions.
  • Graytone Placement measures the optical state resulting from applying the 16 transitions to all possible gray tones (including black and white) when starting from a white image
  • graytone placement shift is the absolute value of the maximum L* shift over the 16 gray tones at time k, which may be defined by the number of sequences, minus the graytone shift at time zero.
  • GTP shift is an absolute measurement of the 16 transitions.
  • Ghosting measures the remaining 240 transitions from all possible 16 gray tones except white to all possible 16 gray tones, and subtracts the GTP value for the final displayed graytone. That is, the ghost measurement compares the optical state of a graytone when it transitions from a non-white graytone to the optical state of that same graytone when it transitions from white.
  • ghost shift is the absolute value of the maximum ghosting at time k, which may be defined by the number of sequences, minus the ghosting at time zero.
  • ghost shift is a relative measurement based on GTP values.
  • the display Prior to taking measurements for GTP shift and ghost shift as shown in FIGS. 7A, 7B , 8A and 8B , the display was cleared by switching the display from its current state to black, white, white, white.
  • any display clearing technique may be used as long as it is consistent so that measured values will be comparable.
  • FIG. 7A is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute graytone shift against the number of updates with remnant voltage discharging 1002 and without remnant voltage discharging 1004, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging results in a significant gray tone shift of approximately 2 L* after approximately 100,000 updates (or over approximately two years).
  • FIG. 7B is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute ghost shift against the number of updates with remnant voltage discharging 1006 and without remnant voltage discharging 1008, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging results in a significant ghost shift of approximately 3 L* after approximately 100,000 updates (or over approximately two years).
  • FIG. 8A is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute graytone shift against the number of updates with remnant voltage discharging 1102, without remnant voltage discharging 1104, and with remnant voltage discharging and standardization of the ON:OFF ratio 1110, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging 1102 results in a significant gray tone shift of approximately 2 L* after approximately 100,000 updates (or over approximately two years) as compared to updates without the discharging 1104.
  • updates with remnant voltage discharging are standardized or offset by turning the transistors to the OFF position for an additional period of time 1110, the resulting of graytone shift after approximately 100,000 updates is only about 0.25 L* as compared to updates without the discharging 1104.
  • FIG. 8B is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute ghost shift against the number of updates with remnant voltage discharging 1106, without remnant voltage discharging 1108, and with remnant voltage discharging and standardization of the ON:OFF ratio 1112, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging 1106 results in a significant ghost shift of approximately 3 L* after approximately 100,000 updates (or over approximately two years) as compared to updates without the discharging 1108.
  • updates with remnant voltage discharging are standardized or offset by turning the transistors to the OFF position for an additional period of time 1112, the resulting of ghost shift after approximately 100,000 updates is only about 0.75 L* as compared to updates without the discharging 1108.
  • FIG. 9A is a schematic signal-timing diagram showing the gate voltage against time, according to some embodiments.
  • FIG. 9A depicts applied gate voltage over time diagram for one optical update, which includes an active update period 1202 - each positive and negative transition reflects a single frame in a series of multiple frames during the active update period, an remnant voltage discharge (ON state) period 1204, and an OFF state period, in an active matrix display having n-type transistors.
  • an n-type transistor a positive gate voltage is applied to achieve an ON state 1204 while a negative voltage is applied to achieve an OFF state 1206.
  • the active update period may be 500 ms
  • the ON period may be 1sec
  • the OFF period may be 2 secs.
  • the remnant voltage discharge pulse (ON state) 1204 is run after the active update (i.e., optical update) 302 to drain residual charge.
  • the OFF state is run after the ON state to achieve an ON:OFF ratio closer to the typical 1:1000 ratio. While the 1:1000 ratio may not be achieved, an ON:OFF ratio that approximates the 1:1000 ratio, even if it is only 1:10, will reduce transistor degradation.
  • FIG. 9B is a schematic signal-timing diagram showing multiple voltages against time with a display utilizing an Xon connection to turn ON all transistors simultaneously, according to some embodiments.
  • FIG. 9B depicts applied voltages over time diagram for one optical update, which includes an active update period 1202, an remnant voltage discharge (ON state) period 1204, and an OFF state period, in an active matrix display having n-type transistors.
  • the four voltages shown are high level gate line voltage (“VDDH”) 1212, low level gate line voltage (“VEE”) 1218, front electrode voltage (“VCOM”) 1216 and Xon voltage 1214.
  • Each voltage has a separate zero voltage axis which is depicted as a solid gray line.
  • the overall gate voltage depicted in FIG. 9A is a combination of VDDH and VEE voltages.
  • the gate driver output enabled voltage (VGDOE) (not shown), which controls which gate voltage (i.e., VEE or VDDH) is applied.
  • VDOE gate driver output enabled voltage
  • the Xon voltage activates all transistors simultaneously when brought to ground, which turns all transistors ON during the discharge period 1204.
  • VDDH is brought to ground and the transistors experience the applied VEE (negative voltage), which is controlled to approach zero towards the end of the period.
  • the ON:OFF ratio By turning the transistor to its OFF position for an additional period of time, the ON:OFF ratio more closely reflects its typical value of 1:1000. While maintaining the ON:OFF ratio at 1:1000 is preferred, any ON:OFF period that moves the ratio towards its typical value, even if it is only 1:10, 1:50 or 1:100, may prevent transistor degradation.
  • the OFF period adds time to each update.
  • the OFF period may be preassigned a definite amount of time, may be determined by a controller based on the frequency of updates and/or may be interrupted.
  • the OFF period preferably occurs after the ON period, but may occur at other times, including before an active update period.
  • the OFF period may range from 500 ms to 4 sec, preferably from 1 sec to 2 secs.
  • the OFF period may be extended to up to 10 secs.

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