EP3327809A1 - Afficheur - Google Patents

Afficheur Download PDF

Info

Publication number
EP3327809A1
EP3327809A1 EP17202036.4A EP17202036A EP3327809A1 EP 3327809 A1 EP3327809 A1 EP 3327809A1 EP 17202036 A EP17202036 A EP 17202036A EP 3327809 A1 EP3327809 A1 EP 3327809A1
Authority
EP
European Patent Office
Prior art keywords
layer
conductive layer
display device
insulating layer
driving voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP17202036.4A
Other languages
German (de)
English (en)
Other versions
EP3327809B1 (fr
Inventor
Donghyun Lee
Deukjong Kim
Keunsoo Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of EP3327809A1 publication Critical patent/EP3327809A1/fr
Application granted granted Critical
Publication of EP3327809B1 publication Critical patent/EP3327809B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • Exemplary embodiments relate to a display device.
  • Purposes of a display device have been diversified. Also, since the display device has a thin thickness and is lightweight, the range of usage of the display device has been gradually widened. As the display device is utilized variously, design purposes of the display device such as reduction in the area of a non-display area have been diversified.
  • Exemplary embodiments are directed to a display device having a structure in which at least a portion of a non-display area is flexible.
  • these exemplary embodiments are provided as examples and the scope of the disclosure is not limited thereto.
  • a display device includes a substrate including a display area and a peripheral area, outside the display area, which includes a flexible area in which the substrate is flexible around a bending axis located and extending in one direction, a data line and a driving voltage line disposed in the display area, an inorganic insulating layer on the substrate and which defines an opening corresponding to the flexible area, a first conductive layer and a second conductive layer disposed in the peripheral area and which are spaced apart from each other around the opening, an organic insulating layer which covers the first conductive layer and the second conductive layer, and a connection conductive layer on the organic insulating layer.
  • connection conductive layer connects the first conductive layer and the second conductive layer via contact holes defined in the organic insulating layer, the first conductive layer and the second conductive layer includes a same material as that of one of the data line and the driving voltage line, and the connection conductive layer includes a same material as that of the other of the data line and the driving voltage line.
  • the first conductive layer and the second conductive layer may be disposed on the inorganic insulating layer.
  • a portion of the organic insulating layer may be disposed between the data line and the driving voltage line.
  • the display device may further include a third conductive layer inside the opening and which includes the same material as that of the first conductive layer and the second conductive layer.
  • connection conductive layer may connect to the third conductive layer via a contact hole defined in the organic insulating layer.
  • connection conductive layer may include a first connection conductive layer which connects the first conductive layer to the third conductive layer and a second connection conductive layer which connects the second conductive layer to the third conductive layer and is spaced apart from the first connection conductive layer.
  • the third conductive layer may include a plurality of sub-conductive layers spaced apart from each other inside the opening, and the connection conductive layer may further include an additional connection conductive layer which connects adjacent sub-conductive layers among the plurality of sub-conductive layers.
  • the display device may further include an additional driving voltage line which overlaps at least a portion of the driving voltage line and is spaced apart from the driving voltage line and electrically connected to the driving voltage line.
  • the additional driving voltage line may include the same material as that of the data line.
  • the substrate may include a plastic layer, and at least a portion of the organic insulating layer inside the opening directly may contact the plastic layer of the substrate.
  • the substrate may further include an inorganic barrier layer on the plastic layer and which defines an opening corresponding to the opening of the inorganic insulating layer and exposing the plastic layer.
  • a display device includes a substrate including a display area and a peripheral area, outside the display area, where includes a flexible area, a thin film transistor disposed in the display area and which includes a semiconductor layer and a gate electrode, an inorganic insulating layer on the substrate and which covers the gate electrode and defines an opening corresponding to the flexible area, a pixel electrode disposed in the display area and which is connected to the thin film transistor, a first wiring layer and a second wiring layer disposed in the display area and between the inorganic insulating layer and the pixel electrode, a first conductive layer and a second conductive layer disposed in the peripheral area, spaced apart from each other around the opening, and on the inorganic insulating layer, an organic insulating layer which covers the first conductive layer and the second conductive layer and a connection conductive layer on the organic insulating layer and which connects the first conductive layer and the second conductive layer via contact holes respectively defined in the organic insulating layer.
  • the first conductive layer and the second conductive layer which covers
  • a portion of the organic insulating layer may be disposed between the first wiring layer and the second wiring layer.
  • the first wiring layer and the second wiring layer may be connected to each other via a contact hole defined in the organic insulating layer.
  • the first wiring layer and the second wiring layer may respectively be an upper driving voltage line and a lower driving voltage line.
  • the display device may further include a data line and a driving voltage line in the display area and which are electrically connected to the thin film transistor, one of the first wiring layer and the second wiring layer may be the data line, and the other of the first wiring layer and the second wiring layer may be the driving voltage line.
  • the display device may further include a third conductive layer inside the opening and which includes the same material as that of the first conductive layer and the second conductive layer.
  • connection conductive layer may connect the third conductive layer via a contact hole defined in the organic insulating layer.
  • connection conductive layer may include a plurality of sub-connection conductive layers, and each of the plurality of sub-connection conductive layers may connect two adjacent conductive layers among the first to third conductive layers.
  • the substrate may include a plastic layer, and at least a portion of the organic insulating layer inside the opening may directly contact the plastic layer via the opening.
  • Exemplary embodiments provide a display device which may implement "bezel-less" by reducing an area of a non-display area and which may minimize the occurrence of defect such as disconnection.
  • the scope of the disclosure is not limited by this effect.
  • relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure.
  • a specific process order may be performed differently from the described order.
  • two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.
  • a layer, region, or component when a layer, region, or component is referred to as being “connected” to another layer, region, or component, it may be “directly connected” to the other layer, region, or component or may be “indirectly connected” to the other layer, region, or component with other layer, region, or component interposed therebetween.
  • a layer, region, or component when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component or may be “indirectly electrically connected” to other layer, region, or component with other layer, region, or component interposed therebetween.
  • the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense.
  • the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.
  • FIG. 1 is a plan view of an exemplary embodiment of a display device 1
  • FIG. 2 is a perspective view of an exemplary embodiment of a portion of the display device 1.
  • the display device 1 includes a display unit 10 on a substrate 100.
  • the display unit 10 includes pixels P.
  • Each of the pixels P is connected to a scan line SL extending in a y-direction and a data line DL extending in an x-direction and crossing the y-direction.
  • each pixel P may emit, for example, red, green, blue, or white light and include an organic light-emitting diode ("OLED").
  • OLED organic light-emitting diode
  • the display unit 10 provides a predetermined image via light emitted from the pixels P and defines a display area DA.
  • the pixel P denotes a sub-pixel emitting red, green, blue, or white light as described above.
  • a peripheral area PA is disposed at outside of the display area DA.
  • the peripheral area PA may surround the display area DA.
  • the peripheral area PA is a region in which the pixels P are not arranged and does not provide the predetermined image via light emitted from the pixels P.
  • the peripheral area PA may include a first scan driver 20 and a second scan driver 30, a terminal portion 40, a driving voltage supply line 60, and a common voltage supply line 70.
  • the first and second scan drivers 20 and 30 may be disposed in the peripheral area PA of the substrate 100, generate a scan signal, and transfer the scan signal to the pixel P via the scan line SL.
  • the first scan driver 20 may be in the left of the display unit 10
  • the second scan driver 30 may be in the right of the display unit 10.
  • the display device 1 may include only one scan driver in the left or right.
  • the terminal portion 40 may be disposed in one side of the substrate 100 and include a plurality of terminals 41, 42, 43, and 44.
  • the terminal portion 40 may not be covered with an insulating layer, be exposed to outside, and be electrically connected to a flexible printed circuit board ("FPCB").
  • FPCB flexible printed circuit board
  • the FPCB connects a controller 80 to the terminal portion 40 electrically. Signals or power transferred from the controller 80 moves to wirings 21, 31, 51, 61, and 71 connected to the terminal portion 40.
  • the controller 80 receives a vertical synchronization signal, a horizontal synchronization signal, and a clock signal and generates control signals for controlling driving of the first and second scan drivers 20 and 30.
  • the generated control signals may be transferred to the first and second scan drivers 20 and 30 respectively via the terminal 43 and the wirings 21 and 31.
  • Scan signals of the first and second scan drivers 20 and 30 are provided to the pixels P via the scan lines SL.
  • the controller 80 provides a driving voltage ELVDD and a common voltage ELVSS to the driving voltage supply line 60 and the common voltage supply line 70 respectively via the terminals 42 and 44 connected to the FPCB and the wirings 61 and 71.
  • the driving voltage ELVDD is provided to each pixel P via a driving voltage line PL, and the common voltage ELVSS may be provided to an opposite electrode of the pixel P.
  • a data driver 50 may be in the FPCB.
  • the data driver 50 provides a data signal to each pixel P.
  • the data signal of the data driver 50 is provided to the pixel P via the terminal 41, the wiring 51 connected to the terminal 41, and the data line DL connected to the wiring 51.
  • FIG. 1 illustrates that the data driver 50 is in the FPCB, the invention is not limited thereto.
  • the data driver 50 may be in the peripheral area PA of the substrate 100.
  • the driving voltage supply line 60 is in the peripheral area PA.
  • the driving voltage supply line 60 may be between the terminal portion 50 and the display unit 10.
  • the driving voltage ELVDD provided from the controller 80 via the wiring 61 connected to the terminal 41 is provided to each pixel P via the driving voltage line PL as described above.
  • the common voltage supply line 70 is in the peripheral area PA and provides the common voltage ELVSS to an opposite electrode (e.g., a cathode) of an OLED of each pixel P.
  • the common voltage supply line 70 has a loop form having one side open and may extend along edges of the substrate 100 except the terminal portion 40.
  • the peripheral area PA includes a flexible area BA.
  • the flexible area BA may be between the terminal portion 40 and the display unit 10.
  • the flexible area BA may extend in a direction crossing an extending direction of the wirings 21, 31, 51, 61, and 71. In an exemplary embodiment, for example, the flexible area BA may extend in a y-direction with a predetermined width along an x-direction.
  • the flexible area BA divides the substrate 100 into a first area 1A including the display area DA, and a second area 2A which is an opposite side to the first area 1A with respect to the flexible area BA. That is, the flexible area BA is between the first area 1A and the second area 2A.
  • the first area 1A may include the display area DA and a portion of the peripheral area PA.
  • the second area 2A may include only a portion of the peripheral area PA.
  • the display device 1 may be bent or curved around the flexible area BA. As illustrated in FIG. 2 , a portion of the substrate 100 of the display device 1 is bent. In an exemplary embodiment, for example, the substrate 100 is bent around a bending axis BAX extending in the y-direction and thus the display device 1 has a bent shape like the bent substrate 100.
  • the substrate 100 may include various materials (e.g., a polymer resin) having a flexible or bendable characteristic.
  • FIG. 2 illustrates a structure in which the substrate 100, not the entire display device 1, is bent.
  • FIG. 3 is a circuit diagram of an exemplary embodiment of one pixel of the display device 1 of FIG. 1 .
  • a pixel P may include signal lines SLn, SLn-1, EL, and DL, a plurality of thin film transistors ("TFTs") T1, T2, T3, T4, T5, T6, and T7 connected to the signal lines, a storage capacitor Cst, an initialization voltage line VL, a driving voltage line PL, and an OLED.
  • TFTs thin film transistors
  • FIG. 3 illustrates a case where each pixel P includes the signal lines SLn, SLn-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, the invention is not limited thereto.
  • at least one of the signals lines SLn, SLn-1, EL, and DL and/or the initialization voltage line VL may be shared by adjacent pixels.
  • the TFTs may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.
  • the signal lines include the scan line SLn which transfers a scan signal Sn, the previous scan line SLn-1 which transfers a previous scan signal Sn-1 to the first initialization TFT T4 and the second initialization TFT T7, the emission control line EL which transfers an emission control signal En to the operation control TFT T5 and the emission control TFT T6, and the data line DL which crosses the scan line SLn and transfers a data signal Dm to the switching TFT T2.
  • the driving voltage line PL transfers the driving voltage ELVDD to the driving TFT T1 via the operation control TFT T5, and the initialization voltage line VL transfers an initialization voltage Vint to the driving TFT T1 for initialization via the first initialization TFT T4 and to a pixel electrode of the OLED for initialization via the second initialization TFT T7.
  • a driving gate electrode G1 of the driving TFT T1 is connected to a first storage capacitor plate Cst1, a driving source electrode S1 of the driving TFT T1 is electrically connected to the driving voltage line PL via the operation control TFT T5, and a driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the OLED via the emission control TFT T6.
  • the driving TFT T1 receives the data signal Dm and supplies a driving current I OLED to the OLED in response to a switching operation of the switching TFT T2.
  • a switching gate electrode G2 of the switching TFT T2 is connected to the scan line SLn, a switching source electrode S2 of the switching TFT T2 is connected to the data line DL, and a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1 and electrically connected to the driving voltage line PL via the operation control TFT T5.
  • the switching TFT T2 is turned on in response to a scan signal Sn transferred via the scan line SLn and performs the switching operation of transferring the data signal Dm from the data line DL to the driving source electrode S1 of the driving TFT T1.
  • a compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line SLn, a compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1 and electrically connected to the pixel electrode of the OLED via the emission control TFT T6, and a compensation drain electrode D3 of the compensation TFT T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, a first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1.
  • the compensation TFT T3 is turned on in response to the scan signal Sn transferred via the scan line SLn, and the turned-on TFT T3 makes the driving TFT T1 function as a diode by electrically connecting the driving gate electrode G1 of the driving TFT T1 to the driving drain electrode D1 of the driving TFT T1.
  • a first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line SLn-1, a first initialization source electrode S4 of the first initialization TFT T4 is connected to a second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization TFT T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1.
  • the first initialization TFT T4 is turned on in response to the previous scan signal Sn-1 transferred via the previous scan line SLn-1 and initializes a voltage of the driving gate electrode G1 of the driving TFT T1 by transferring the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1.
  • An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL, an operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line PL, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and connected to the switching drain electrode D2 of the switching TFT T2.
  • An emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL, an emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and connected to the compensation source electrode S3 of the compensation TFT T3, and an emission control drain electrode D6 of the emission control TFT T6 is connected to the second initialization source electrode S7 of the second initialization TFT T7 and connected to the pixel electrode of the OLED.
  • the operation control TFT T5 and the emission control TFT T6 are simultaneously turned on in response to the emission control signal En transferred via the emission control line EL, transfer the driving voltage ELVDD to the OLED, and allow the driving current I OLED to flow through the OLED.
  • a second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SLn-1, a second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and connected to the pixel electrode of the OLED, and a second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and connected to the initialization voltage line VL.
  • the second initialization TFT T7 is turned on in response to a previous scan signal Sn-1 transferred via the previous scan line SLn-1 and initializes the pixel electrode of the OLED using the initialization voltage Vint.
  • FIG. 3 illustrates a case where the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SLn-1
  • the invention is not limited thereto.
  • the first initialization TFT T4 may be connected to the previous scan line SLn-1 and driven in response to the previous scan signal Sn-1
  • the second initialization TFT T7 may be connected to a separate signal line (e.g., a next scan line) and driven in response to a signal transferred via the separate signal line.
  • a second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and an opposite electrode of the OLED is connected to the common voltage ELVSS. Therefore, the OLED may display an image by receiving the driving current I OLED from the driving TFT T1 and emitting light.
  • FIG. 3 illustrates that the compensation TFT T3 and the first initialization TFT T4 have dual gate electrodes
  • the invention is not limited thereto.
  • the compensation TFT T3 and the first initialization TFT T4 may have one gate electrode.
  • at least one of the other TFTs T1, T2, T5, T6, and T7 besides the compensation TFT T3 and the first initialization TFT T4 may have dual gate electrodes, and various modifications may be made.
  • FIG. 4 is a plan view of an exemplary embodiment of one pixel of the display device of FIG. 1
  • FIG. 5 is a cross-sectional view of an exemplary embodiment of a portion of a display device
  • FIG. 6 is a plan view of an exemplary embodiment of a peripheral area PA including a flexible area BA of FIG. 5 viewed in a direction K
  • FIGS. 7A and 7B respectively are a plan view and a cross-sectional view of a peripheral area including a flexible area according to a compared example.
  • FIG. 7B is a cross-sectional view of taken along line VIIb-VIIb' of FIG. 7A .
  • FIG. 7B is a cross-sectional view of taken along line VIIb-VIIb' of FIG. 7A .
  • FIG. 7B is a cross-sectional view of taken along line VIIb-VIIb' of FIG. 7A .
  • FIG. 7B is a cross-sectional view of taken along line VIIb-VIIb' of
  • FIG. 5 illustrates a state in which the display device is not bent, and a cross-sectional view of a display area DA of FIG. 5 corresponds to a cross-sectional view of an exemplary embodiment of one pixel taken along lines A-A' and B-B' of FIG. 4 .
  • FIG. 4 is an arrangement view of an exemplary embodiment of locations of the plurality of TFTs and the capacitor of the one pixel of FIG. 3 .
  • the arrangement illustrated in FIG. 4 is an arrangement view of one pixel. Pixels which are the same as or similar to the pixel of FIG. 4 may be arranged to the top, the bottom, the left, and the right of the pixel of FIG. 4 .
  • a display area DA of FIGS. 4 and 5 is mainly described and then flexible areas BA of FIGS. 5 to 7B are described.
  • a scan line 121, a previous scan line 122, and an emission control line 123 extend in the y-direction, and a data line 171 and driving voltage lines 172 and 178 extend in the x-direction crossing the y-direction.
  • the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 may be disposed on a buffer layer BL (refer FIG. 5 ).
  • These semiconductor layers may be connected to each other, and may be curved in various forms.
  • the semiconductor layers may include polycrystalline silicon, for example.
  • Each of the semiconductor layers may include a channel region not doped with impurities, a source region and a drain region.
  • the source region and the drain region are respectively disposed at opposite sides of the channel region and doped with impurities.
  • the channel region of the semiconductor layer overlaps the scan line 121, the previous scan line 122, or the emission control line 123.
  • the semiconductor layer may be doped with the impurities by using the scan line 121, the previous scan line 122, or the emission control line 123 as a self-align mask.
  • types of the impurities may change depending on a type of a TFT and include N-type impurities or P-type impurities.
  • the channel region, the source region at one side of the channel region, and the drain region at the other side of the channel region may also be referred to as an active layer. That is, a TFT has an active layer and the active layer includes the channel region, the source region, and the drain region.
  • the doped source region and drain region respectively correspond to a source electrode and a drain electrode of a TFT.
  • the driving source electrode may correspond to a driving source region 176a doped with impurities
  • the driving drain electrode may correspond to a driving drain region 177a doped with impurities.
  • terms of a source region or a drain region are used instead of a source electrode or a drain electrode.
  • the driving TFT T1 includes a driving gate electrode 125a and the driving semiconductor layer 130a including a driving channel region, the driving source region 176a and the driving drain region 177a.
  • the driving channel region of the semiconductor layer 130a overlaps the driving gate electrode 125a.
  • the driving channel region of the semiconductor layer 130a has a curved form and thus may have a long channel length.
  • FIG. 4 illustrates the driving channel region having a curved shape in a form of an "omega," the invention is not limited thereto.
  • the driving gate electrode 125a may serve as the gate electrode of the driving TFT T1 and simultaneously serve as the first storage capacitor plate of the storage capacitor Cst described below.
  • a first gate insulating layer GI1 (refer to FIG.
  • the first gate insulating layer GI1 may be an inorganic layer including SiON, SiOx, and/or SiNx, for example.
  • the driving source region 176a is connected to a switching drain region 177b and an operation control drain region 177e described below, and the driving drain region 177a is connected to a compensation source region 176c and an emission control source region 176f described below.
  • the switching TFT T2 includes a switching gate electrode 125b and the switching semiconductor layer 130b including sa witching channel region, a switching source region 176b and a switching drain region 177b.
  • the switching channel region of the switching semiconductor layer 130b overlaps the switching gate electrode 125b, and the switching gate electrode 125b corresponds to a portion of the scan line 121 which overlaps the switching channel region of the switching semiconductor layer 130b.
  • the switching source region 176b is electrically connected to the data line 171 via a contact hole 164 defined in the first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD.
  • the second gate insulating layer GI2 and the interlayer insulating layer ILD may be inorganic layers including SiON, SiOx, and/or SiNx, for example.
  • the switching drain region 177b is connected to the driving TFT T1 and the operation control TFT T5.
  • the compensation TFT T3 includes compensation gate electrodes 125c1 and 125c2 and the compensation semiconductor layer 130c including a compensation channel region, a compensation source region 176c and a compensation drain region 177c.
  • the compensation channel region of the compensation semiconductor 130c overlaps the compensation gate electrodes 125c1 and 125c2.
  • the compensation gate electrodes 125c1 and 125c2 correspond to a portion of the scan line 121 which overlaps the compensation channel region of the compensation semiconductor 130c.
  • the compensation gate electrodes 125c1 and 125c2 are dual gate electrodes including the first gate electrode 125c1 and the second gate electrode 125c2 and may prevent or reduce the occurrence of a leakage current.
  • the compensation drain region 177c may be connected to the first storage capacitor plate 125a of the storage capacitor Cst via a connection member 174.
  • the first storage capacitor plate 125a of the storage capacitor Cst may also serve as the gate electrode of the driving TFT T1 described above.
  • the connection member 174 may include the same material as that of the data line 171 and may be in the same layer as a layer in which the data line 171 is disposed. One end of the connection member 174 may be electrically connected to the compensation drain region 177c and the initialization drain region 177d via a contact hole 166 defined in the first and second gate insulating layers GI1 and GI2 and the interlayer insulating layer ILD. The other end of the connection member 174 may be electrically connected to the first storage capacitor plate 125a via a contact hole 167 defined in the second gate insulating layer GI2 and the interlayer insulating layer ILD. The other end of the connection member 174 may also be connected to the first storage capacitor plate 125a via a storage capacitor opening 127a in a second storage capacitor plate 127.
  • the first initialization TFT T4 includes first initialization gate electrodes 125d1 and 125d2 and the first initialization semiconductor layer 130d including a first initialization channel region, a first initialization source region 176d and a first initialization drain region 177d.
  • the first initialization channel region of the first initialization semiconductor layer 130d overlaps the first initialization gate electrodes 125d1 and 125d2.
  • the first initialization gate electrodes 125d1 and 125d2 correspond to portions of the previous scan line 122 which overlap the first initialization channel region of the first initialization semiconductor layer 130d.
  • the first initialization gate electrodes 125d1 and 125d2 are dual gate electrodes including the first gate electrode 125d1 and the second gate electrode 125d2 and may prevent or reduce the occurrence of a leakage current.
  • the first initialization source region 176d is connected to an initialization voltage line 124 via an initialization connection line 173.
  • the initialization voltage line 124 includes the same material as that of the second storage capacitor plate 127 and may be in the same layer in which the second storage capacitor plate 127 is disposed.
  • One end of the initialization connection line 173 may be electrically connected to the initialization voltage line 124 via a contact hole 161 defined in the second gate insulating layer GI2 and the interlayer insulating layer ILD.
  • the other end of the initialization voltage line 124 may be electrically connected to the initialization source region 176d via a contact hole 162 defined in the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD.
  • the operation control TFT T5 includes an operation control gate electrode 125e and the operation control semiconductor layer 130e including an operation control channel region, an operation control source region 176e and an operation control drain region 177e.
  • the operation control channel region of the operation control semiconductor layer 130e overlaps the operation control gate electrode 125e.
  • the operation control gate electrode 125e corresponds to a portion of the emission control line 123 which overlaps the operation control channel region of the operation control semiconductor layer 130e.
  • the operation control source region 176e may be electrically connected to a lower driving voltage line 172 via a contact hole 165 defined in the first and second gate insulating layer GI1 and GI2 and the interlayer insulating layer ILD. In this case, a portion neighboring the contact hole 165 of the lower driving voltage line 172 may correspond to the source region 176e, that is, the source electrode of the operation control TFT T5.
  • the emission control TFT T6 includes an emission control gate electrode 125f and the emission control semiconductor layer 130f including an emission control channel region, an emission control source region 176f and an emission control drain region 177f.
  • the emission control channel region of the emission control semiconductor layer 130f overlaps the emission control gate electrode 125f.
  • the emission control gate electrode 125f corresponds to a portion of the emission control line 123 which overlaps the emission control channel region of the emission control semiconductor layer 130f.
  • the emission control drain region 177f may be electrically connected to an intermediate connection layer 175 on the interlayer insulating layer ILD via a contact hole 163 defined in the first and second gate insulating layers GI1 and GI2 and the interlayer insulating layer ILD.
  • the intermediate connection layer 175, the data line 171 and the lower driving voltage line 172 may be disposed on the interlayer insulating layer ILD.
  • the intermediate layer 175 is electrically connected to an auxiliary connection layer 179 via a contact hole 183.
  • the auxiliary connection layer 179 is electrically connected to a pixel electrode 310 of an OLED via a contact hole 185.
  • the second initialization TFT T7 includes a second initialization gate electrode 125g and the second initialization semiconductor layer 130g including a second initialization channel region, a second initialization source region 176g and a second initialization drain region 177g.
  • the second initialization channel region of the second initialization semiconductor layer 130g overlaps the second initialization gate electrode 125g.
  • the second initialization gate electrode 125g corresponds to a portion of the previous scan line 122 which overlaps the second initialization channel region of the second initialization semiconductor layer 130g.
  • the second initialization source region 176g is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode 310 of the OLED.
  • the second initialization drain region 177g is connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line 124.
  • the second initialization TFT T7 is turned on in response to a previous scan signal transferred via the previous scan line 122 and initializes the pixel electrode 310 of the OLED.
  • the storage capacitor Cst includes the first storage capacitor plate 125a and the second storage capacitor plate 127.
  • the second storage capacitor plate 127 overlaps the first storage capacitor plate 125a with the second gate insulating layer GI2 therebetween.
  • the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrodes 125a which also serves as the first storage capacitor plate may be directly on the same layer such as the first gate insulating layer GI1 as illustrated in the display area DA of FIG. 5 .
  • the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrodes 125a which also serves as the first storage capacitor plate may include at least one of Mo, Al, Cu, Ti, etc. and include a single layer or a multi-layer.
  • the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrodes 125a which also serves as the first storage capacitor plate may be a single layer including Mo.
  • the second storage capacitor plate 127 and the initialization voltage line 124 may be directly on the same layer such as the second gate insulating layer GI2 as illustrated in the display area DA of FIG. 5 .
  • the second storage capacitor plate 127 and the initialization voltage line 124 may include at least one of Mo, Al, Cu, Ti, etc. and include a single layer or a multi-layer.
  • the second storage capacitor plate 127 and the initialization voltage line 124 may be a single layer including Mo or a multi-layer including Mo/Al/Mo.
  • the data line 171, the lower driving voltage line 172, the initialization connection line 173, the connection line 174, and the intermediate connection layer 175 may be directly on the same layer such as the interlayer insulating layer ILD as illustrated in the display area DA of FIG. 5 .
  • the data line 171, the lower driving voltage line 172, the initialization connection line 173, the connection line 174, and the intermediate connection layer 175 may include the same material.
  • the data line 171, the lower driving voltage line 172, the initialization connection line 173, the connection line 174, and the intermediate connection layer 175 may include, for example, at least one of Mo, Al, Cu, and Ti and include a single layer or a multi-layer.
  • the data line 171, the lower driving voltage line 172, the initialization connection line 173, the connection line 174, and the intermediate connection layer 175 may have a multi-layered structure including Ti/Al/Ti.
  • the lower driving voltage line 172 is electrically connected to the upper driving voltage line 178.
  • the lower driving voltage line 172 is electrically connected to the upper driving voltage line 178 via a contact hole 181 defined in a first organic insulating layer PL1 between the lower driving voltage line 172 and the upper driving voltage line 178.
  • the driving voltage lines 172 and 178 supply a constant electric signal, that is, the driving voltage ELVDD to a plurality of pixels. To implement a display device providing a high quality image, it is desirable that a voltage drop of the driving voltage lines 172 and 178 should not occur.
  • the driving voltage line of the exemplary embodiment has the lower and upper driving voltage lines electrically connected each other, for example, the upper driving voltage line 178 is electrically connected to the lower driving voltage line 172 according to an exemplary embodiment, the resistance of the driving voltage line of the exemplary embodiment may be reduced or minimized. Therefore, the voltage drop due to resistance of the driving voltage lines 172 and 178 may be effectively reduced even if an area of a pixel P is reduced in order to implement a high resolution display device.
  • the upper driving voltage line 178 may include at least one of Mo, Al, Cu, Ti, for example, and include a single layer or a multi-layer. In an exemplary embodiment, the upper driving voltage line 178 may have a multi-layered structure including Ti/Al/Ti, for example.
  • a passivation layer PVX may be on the data line 171, the lower driving voltage line 172, the initialization connection line 173, the connection member 174, and the intermediate connection layer 175.
  • the passivation layer PVX may include, for example, SiNx. Since hydrogen of SiNx combines with a dangling bond of a semiconductor layer, and removes a defect site of the semiconductor layer, electrical characteristics of TFTs can be improved.
  • the passivation layer PVX may cover a portion of wirings exposed from the peripheral area PA and protect the wirings.
  • the wirings 21, 31, 51, 61, and 71 without the passivation layer PVX may be exposed from a portion of the peripheral area PA, and the exposed portion may be damaged by etchant used while the pixel electrode 310 (see FIG. 5 ) is patterned.
  • the passivation layer PVX may protect the wirings 21, 31, 51, 61, and 71 by covering the portion of the wirings 21, 31, 51, 61, and 71.
  • the upper driving voltage line 178 and the auxiliary connection line 179 may be covered with a second organic insulating layer PL2.
  • the first and second organic insulating layers PL1 and PL2 may include an organic material.
  • the organic material may include a general-purpose polymer such as an imide-based polymer, polymethylmethacrylate (“PMMA”) or polystyrene ("PS”), or polymer derivatives having a phenol-based group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.
  • PMMA polymethylmethacrylate
  • PS polystyrene
  • the OLED may be on the second organic insulating layer PL2.
  • the OLED may include the pixel electrode 310, an opposite electrode 330, and an intermediate layer 320 therebetween.
  • the intermediate layer 320 may include an emission layer.
  • a pixel-defining layer 150 may be disposed on the pixel electrode 310.
  • the pixel-defining layer 150 defines a pixel by including an opening corresponding to each sub-pixel, that is, an opening exposing at least a central portion of the pixel electrode 310.
  • the pixel-defining layer 150 may prevent an arc, etc. from occurring between the pixel electrode 310 and the opposite electrode 330 by increasing a distance between an edge of the pixel electrode 310 and the opposite electrode 330.
  • the pixel-defining layer 150 may include an organic material such as polyimide (“PI”) or hexamethyldisiloxane (“HMDSO").
  • the intermediate layer 320 may include a low molecular or polymer material.
  • the intermediate layer 320 may have a structure in which a hole injection layer ("HIL"), a hole transport layer (“HTL”), an emission layer (“EML”), an electron transport layer (“ETL”), an electron injection layer (“EIL”), etc. are stacked in a single or a composite configuration, and may include various organic materials such as copper phthalocyanine (“CuPc”), N,N'-Di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (“NPB”), and tris-8-hydroxyquinoline aluminum (“Alq3"). These layers may be provided by vacuum evaporation.
  • HIL hole injection layer
  • HTL hole transport layer
  • EML emission layer
  • ETL electron transport layer
  • EIL electron injection layer
  • Alq3 tris-8-hydroxyquinoline aluminum
  • the intermediate layer 320 may have a structure including an HTL and an EML, for example.
  • the HTL may include a PEDOT
  • the EML may include a polymer material such as polyphenylene vinylene ("PPV")-based material and a polyfluorene-based material.
  • the structure of the intermediate layer 320 is not limited to the above-described structure but may have various structures.
  • the intermediate layer 320 may be one layer which covers a plurality of pixel electrodes 310 or may include layers, each of which is patterned to correspond to each of the plurality of pixel electrodes 310.
  • the opposite electrode 330 may be disposed in upper part of the display area DA and cover the display area DA. That is, the opposite electrode 330 may have one body which covers a plurality of OLEDs and correspond to the plurality of pixel electrodes 310.
  • the OLED may be easily damaged by external moisture or oxygen, the OLED may be protected by being covered with an encapsulation layer 400.
  • the encapsulation layer 400 may cover the display area DA and extend to an outside of the display area DA.
  • the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.
  • the first inorganic encapsulation layer 410 may cover the opposite electrode 330 and include SiOx, SiNx, and/or SiON, for example. Though not shown, other layers such as a capping layer may be disposed between the first inorganic encapsulation layer 410 and the opposite electrode 330. Since the first inorganic encapsulation layer 410 may be disposed along an uneven structure thereunder and have the same thickness along the display area DA, an upper surface of the first inorganic encapsulation layer 410 may not be planar.
  • the organic encapsulation layer 420 covers the first inorganic encapsulation layer 410.
  • the organic encapsulation layer 420 may have a variable thickness along the display area DA such that an upper surface of the organic encapsulation layer 420 corresponding to the display area DA may be approximately planar.
  • the organic encapsulation layer 420 may include at least one of polyethylene terephthalate (“PET”), polyethylene naphthalate (“PEN”), polycarbonate (“PC”), PI, polyethylene sulfonate, polyoxymethylene (“POM”), polyarylate, and HMDSO, for example.
  • the second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and include SiOx, SiNx, and/or SiON, for example.
  • the encapsulation layer 400 may prevent the crack from being transferred between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420, or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, the encapsulation layer 400 may prevent or minimize forming of a path through which external moisture or oxygen penetrates into the display area DA.
  • a polarization plate may be disposed on the encapsulation layer 400 by using a light transmission adhesive.
  • the polarization plate is a structure for reducing external light reflection. Instead of the polarization plate, a layer including a black matrix and a color filter may be used.
  • the buffer layer BL, the first and second gate insulating layers GI1 and GI2, and the interlayer insulating layer ILD on the substrate 100 may be collectively referred to as inorganic insulating layers IL.
  • the inorganic layers IL may include an inorganic material such as SiOx, SiNx, and/or SiON.
  • FIG. 5 illustrates that an inorganic insulating layer IL in the peripheral area PA around the flexible area BA includes the buffer layer BL, the first and second gate insulating layers GI1 and GI2, and the interlayer insulating layer ILD.
  • the inorganic insulating layer IL may include at least one of the buffer layer BL, the first and second gate insulating layers GI1 and GI2, and the interlayer insulating layer ILD, for example.
  • the inorganic insulating layer IL includes an opening OP corresponding to the flexible area BA.
  • the buffer layer BL, the first and second gate insulating layers GI1 and GI2, and the interlayer insulating layer ILD may respectively define openings op1, op2, op3, and op4 corresponding to the flexible area BA.
  • the inorganic insulating layer IL is continuously provided from the first area 1A to the second area 2A without the opening OP in the flexible area BA, while the display device 1 is bent, stress may be applied to the inorganic insulating layer IL. Since, unlike an organic layer, an inorganic layer has a high hardness, a crack may easily occur in the inorganic insulating layer IL due to the bending of the display device 1. In the case where a crack occurs in the inorganic insulating layer IL, a crack, etc. may also occur in first and second conductive layers 213a and 213b disposed on the inorganic insulating layer IL and cause a defect such as disconnection.
  • the inorganic insulating layer IL since the inorganic insulating layer IL includes the opening OP, the inorganic insulating layer IL may prevent or reduce the occurrence of a crack, etc. by stress efficiently.
  • the opening OP has a width OW in the x-direction which is greater than the width of the flexible area BA and thus minimizes a defect by a crack.
  • the substrate 100 may have a flexible or bendable characteristic by including at least one plastic layer.
  • the substrate 100 may include a first plastic layer 101 and a second plastic layer 105.
  • the substrate 100 may include a first barrier layer 103 and a second barrier layer 107.
  • the first barrier layer 103 may be disposed between the first plastic layer 101 and the second plastic layer 105
  • the second barrier layer 107 may be disposed between the second plastic layer 105 and the buffer layer BL.
  • the first and second plastic layers 101 and 105 may include at least one of PI, polyether sulphone ("PES”), polyacrylate, polyether imide (“PEI”), PEN, PET, polyphenylene sulfide (“PPS”), polyarylate, PC, tri-cellulose acetate("TAC”), cellulose acetate propionate (“CAP”), cyclic olefin polymer, and cyclic olefin copolymer, for example.
  • PES polyether sulphone
  • PEI polyacrylate
  • PEI polyether imide
  • PEN polyether imide
  • PET polyphenylene sulfide
  • PPS polyarylate
  • PC tri-cellulose acetate("TAC)
  • CAP cellulose acetate propionate
  • CAP cellulose acetate propionate
  • the first and second barrier layers 103 and 107 may include an inorganic material such as SiOx, SiNx, and/or SiON and prevent external impurities from penetrating into the first and second plastic layers 101 and 105 and damaging or deteriorating a TFT.
  • an inorganic material such as SiOx, SiNx, and/or SiON and prevent external impurities from penetrating into the first and second plastic layers 101 and 105 and damaging or deteriorating a TFT.
  • the second barrier layer 107 may define an opening 107a corresponding to the flexible area BA.
  • the second plastic layer 105 of the substrate 100 may be exposed via the opening 107a of the second barrier layer 107.
  • the second barrier layer 107 may have the opening 107a corresponding to the opening OP of the inorganic insulating layer IL.
  • "correspond" may be understood as "overlap.”
  • FIG. 5 illustrates that inner lateral surfaces of the opening op1 defined by the buffer layer BL, the opening op2 defined by the first gate insulating layer GI1, the opening op3 defined by the second gate insulating layer GI2, the opening op4 defined by the interlayer insulating layer ILD, and the opening 107a defined by the second barrier layer 107 coincide with each other, the invention is not limited thereto.
  • the inner lateral surfaces of the openings op1, op2, op3, op4, and 107a may not coincide with each other, and the openings op1, op2, op3, op4, and 107a may respectively have different sizes.
  • the opening OP of the inorganic insulating layer IL may be defined as one of the openings having a smallest size from among the openings op1, op2, op3, op4, and 107a.
  • the first conductive layer 213a and the second conductive layer 213b are spaced apart from each other on the inorganic insulating layer IL, for example, the interlayer insulating layer ILD.
  • the first conductive layer 213a is separated from the second conductive layer 213b with the opening OP defined by the inorganic insulating layer IL therebetween.
  • the first conductive layer 213a and the second conductive layer 213b separated from each other are electrically connected by a connection conductive layer 215 on the first organic insulating layer PL1.
  • a structure of the first conductive layer 213a and the second conductive layer 213b separated from each other in the flexible area BA and a structure of the connection conductive layer 215 connecting the first conductive layer 213a to the second conductive layer 213b may correspond to a structure of at least one of the wirings 21, 31, 51, 61, and 71.
  • the first conductive layer 213a and the second conductive layer 213b are disposed on the same layer which may be a similar layer with the layers on which the data line 171 and the lower driving voltage line 172 are disposed and include the same material as that of one of the data line 171 and the lower driving voltage line 172.
  • the connection conductive layer 215 is disposed on the same layer as a layer on which the upper driving voltage line 178 and the auxiliary connection layer 179 are disposed and includes the same material as that of one of the upper driving voltage line 178 and the data line 171.
  • the passivation layer PVX may be disposed between the first or second conductive layers 213a or 213b and the connection conductive layer 215, specifically, between the first or second conductive layers 213a or 213b and the first organic insulating layer PL1.
  • the passivation layer PVX defines an opening PVX-op corresponding to the opening OP defined by the inorganic insulating layer IL and defines holes PVX-h for contact between the first and second conductive layers 213a and 213b and the connection conductive layer 215.
  • the connection conductive layer 215 contacts the first and second conductive layers 213a and 213b via a contact hole CNT.
  • the passivation layer PVX may protect a portion of a wiring, for example, a portion of the first and second conductive layers 213a and 213b not covered with the first and second organic insulating layers PL1 and PL2 in other regions not shown in FIG. 5 in the peripheral area PA.
  • the first and second conductive layers 213a and 213b may be provided by forming a conductive material layer (not shown) on the inorganic insulating layer IL defining the opening OP and then etching the same.
  • the inorganic insulating layer IL may have a thickness from about 20,000 angstroms ( ⁇ ) to about 24,000 ⁇ , for example.
  • a portion of the conductive material layer (not shown) in the opening OP of the inorganic insulating layer IL may remain due to a step difference of the inorganic insulating layer IL and thus a remnant pattern 213s may remain on the second barrier layer 107.
  • a remnant pattern 213s may remain on the second barrier layer 107.
  • the remnant pattern 213s is near to an edge of the opening OP, that is, an inner lateral surface of the inorganic insulating layer IL.
  • an edge of the opening OP that is, an inner lateral surface of the inorganic insulating layer IL.
  • each conductive layer 2213 may be at least one of the wirings 21, 31, 51, 61, and 71 described above with reference to FIG. 1 . In this case, a normal operation of the display device 1 is impossible.
  • the first conductive layer 213a and the second conductive layer 213b are spaced apart from each other, thereby avoiding a short-circuit with the remnant pattern 213s and electrically connected via the connection conductive layer 215. Therefore, in an exemplary embodiment, a wiring, for example, the wirings 21, 31, 51, 61, and 71 described above with reference to FIG. 1 may easily perform their functions without an unnecessary electric short-circuit.
  • FIG. 5 illustrates a state in which a third conductive layer 213c is patterned in the opening OP, the third conductive layer 213c may be omitted.
  • the third conductive layer 213c may have the same material as that of the first conductive layer 213a and the second conductive layer 213b.
  • a portion of the first organic insulating layer PL1 disposed between the first and second conductive layers 213a and 213b and the connection conductive layer 215 fills at least a portion of the opening OP of the inorganic insulating layer IL.
  • the portion of the first organic insulating layer PL1 is disposed inside the opening OP of the inorganic insulating layer IL.
  • At least a portion of the first organic insulating layer PL1 inside the opening OP of the inorganic insulating layer IL may directly contact the second plastic layer 105 via the opening OP and the opening 107a of the second barrier layer 107.
  • connection conductive layer 215 may be covered with the second organic insulating layer PL2 and the pixel-defining layer 150.
  • FIG. 5 illustrates a structure in which the pixel-defining layer 150 extends to only the display area DA, the pixel-defining layer 150 may extend to the flexible area BA in another exemplary embodiment.
  • a probability that a crack occurs in the first and second organic insulating layers PL1 and PL2 is low in view of a characteristic of the first and second organic insulating layers PL1 and PL2 including an organic material. Therefore, the first and second organic insulating layers PL1 and PL2 may effectively prevent or minimize the occurrence of a crack in a portion of the connection conductive layer 215 corresponding to the flexible area BA.
  • the first and second organic insulating layers PL1 and PL2 which are organic layers, have a lower hardness than that of an inorganic layer, the first and second organic insulating layers PL1 and PL2 may absorb tensile stress occurring due to the bending of the display device 1 and thus effectively minimize concentration of the tensile stress on the first and second conductive layers 213a and 213b and/or the connection conductive layer 215.
  • FIG. 8 is a plan view of another exemplary embodiment of one pixel in a display area of a display device
  • FIG. 9 is a cross-sectional view of another exemplary embodiment of a portion of a display device.
  • FIG. 9 illustrates a state in which the display device is not bent
  • the cross-sectional view of the display area DA of FIG. 9 corresponds to a cross-sectional view of another exemplary embodiment of one pixel of the display device taken along lines C-C' and D-D' of FIG. 8 .
  • FIGS. 4 and 5 illustrate a case where the driving voltage line of the display device 1 includes double layers including the upper driving voltage line 178 and the lower driving voltage line 172, the invention is not limited thereto.
  • the driving voltage line may be a single layer including the upper driving voltage line 178.
  • the upper driving voltage line 178 of FIG. 9 may resolve a problem of a voltage drop, etc. by having a greater area than that of the upper driving voltage line 178 of FIGS. 4 and 5 . Since the driving voltage line of FIGS. 8 and 9 is the same as the driving voltage line described above with reference to FIGS. 4 and 5 except that the driving voltage line of FIGS. 8 and 9 includes a single layer of the upper driving voltage line 178, repeated descriptions of other constructions are omitted.
  • FIGS. 10 to 12 are cross-sectional views of other exemplary embodiments of a portion of a peripheral area of a display device, and FIGS. 13 to 15 respectively are plan views of FIGS. 10 to 12 . Since exemplary embodiments of a display device illustrated in FIGS. 10 to 12 have the same structure as the exemplary embodiment described above with reference to FIGS. 5 and 9 with only differences in the structure around the flexible area BA of the display device, only the peripheral area PA around the flexible area BA is illustrated in FIGS. 10 to 12 for convenience of description.
  • connection conductive layer 215 electrically connecting the first and second conductive layers 213a and 213b may also electrically connect the third conductive layer 213c in the opening OP to the first and second conductive layers 213a and 213b.
  • connection conductive layer 215 may include first and second connection conductive layers 215a and 215b which are spaced apart from each other.
  • the first connection conductive layer 215a may electrically connect the first conductive layer 213a to the third conductive layer 213c.
  • the second connection conductive layer 215b may electrically connect the third conductive layer 213c to the second conductive layer 213b.
  • connection conductive layer 215 may include first to third connection conductive layers 215a, 215b, and 215c which are spaced apart from each other.
  • the first connection conductive layer 215a may electrically connect the first conductive layer 213a to the third conductive layer 213c1 disposed near to the first conductive layer 213a.
  • the second connection conductive layer 215b may electrically connect the second conductive layer 213b to the third conductive layer 213c2 disposed near to the second conductive layer 213b.
  • the third connection conductive layer 215c may electrically connect the conductive layers 213c1 and 213c2.
  • connection conductive layer 215 includes a plurality of connection conductive layers spaced apart from each other, a probability that a crack, etc. occur due to tensile stress applied to the connection conductive layer 215 while the display device is bent may be reduced more than in the case where the connection conductive layer is one monolithic layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
EP17202036.4A 2016-11-18 2017-11-16 Afficheur Active EP3327809B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160154453A KR102631257B1 (ko) 2016-11-18 2016-11-18 디스플레이 장치

Publications (2)

Publication Number Publication Date
EP3327809A1 true EP3327809A1 (fr) 2018-05-30
EP3327809B1 EP3327809B1 (fr) 2019-10-30

Family

ID=60387867

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17202036.4A Active EP3327809B1 (fr) 2016-11-18 2017-11-16 Afficheur

Country Status (4)

Country Link
US (2) US10211277B2 (fr)
EP (1) EP3327809B1 (fr)
KR (1) KR102631257B1 (fr)
CN (1) CN108074960B (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3522228A1 (fr) * 2018-02-02 2019-08-07 Samsung Display Co., Ltd Afficheur souple et afficheur tactile
EP3859783A4 (fr) * 2018-09-27 2022-06-22 Boe Technology Group Co., Ltd. Substrat matriciel, panneau d'affichage et appareil d'affichage

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102631989B1 (ko) * 2016-10-31 2024-01-31 엘지디스플레이 주식회사 유기발광 표시장치 및 그 제조방법
KR102631257B1 (ko) * 2016-11-18 2024-01-31 삼성디스플레이 주식회사 디스플레이 장치
JP6982958B2 (ja) * 2017-01-13 2021-12-17 株式会社ジャパンディスプレイ 表示装置
KR102325171B1 (ko) * 2017-03-20 2021-11-10 삼성디스플레이 주식회사 표시 장치
KR102432386B1 (ko) 2017-07-12 2022-08-12 삼성디스플레이 주식회사 표시 장치
KR102325221B1 (ko) * 2017-07-27 2021-11-10 엘지디스플레이 주식회사 표시장치
US10847600B2 (en) * 2017-07-28 2020-11-24 Sharp Kabushiki Kaisha Display device and manufacturing method for display device
WO2019021467A1 (fr) * 2017-07-28 2019-01-31 シャープ株式会社 Dispositif d'affichage, procédé de fabrication d'un dispositif d'affichage, et appareil de fabrication d'un dispositif d'affichage
WO2019026237A1 (fr) * 2017-08-03 2019-02-07 シャープ株式会社 Dispositif d'affichage
KR102349279B1 (ko) * 2017-09-08 2022-01-11 삼성디스플레이 주식회사 디스플레이 장치
US10811488B2 (en) * 2017-09-22 2020-10-20 Sharp Kabushiki Kaisha Display device
CN111108541B (zh) * 2017-09-27 2021-10-15 夏普株式会社 可弯曲性显示装置以及可弯曲性显示装置的制造方法
WO2019064429A1 (fr) * 2017-09-28 2019-04-04 シャープ株式会社 Dispositif d'affichage
KR102550504B1 (ko) * 2018-02-09 2023-07-03 삼성전자주식회사 복수개의 배선층을 벤딩 영역에 포함하는 디스플레이
WO2019214083A1 (fr) * 2018-05-08 2019-11-14 华为技术有限公司 Panneau d'affichage souple et terminal mobile
KR102675480B1 (ko) * 2018-06-15 2024-06-13 삼성디스플레이 주식회사 표시 장치
CN108878486A (zh) * 2018-06-26 2018-11-23 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
KR102569929B1 (ko) * 2018-07-02 2023-08-24 삼성디스플레이 주식회사 디스플레이 장치
CN109065505B (zh) * 2018-08-10 2021-01-15 武汉华星光电半导体显示技术有限公司 显示面板及其制造方法
CN109148529B (zh) * 2018-08-20 2021-11-02 武汉华星光电半导体显示技术有限公司 基板及显示装置
US20220115475A1 (en) * 2018-09-28 2022-04-14 Sharp Kabushiki Kaisha Display device and manufacturing method thereof
KR102620972B1 (ko) * 2018-10-23 2024-01-05 삼성디스플레이 주식회사 디스플레이 장치
KR20200053991A (ko) * 2018-11-09 2020-05-19 엘지디스플레이 주식회사 표시 장치
KR20200057855A (ko) * 2018-11-16 2020-05-27 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
KR20200085962A (ko) * 2019-01-07 2020-07-16 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
KR20200110490A (ko) * 2019-03-13 2020-09-24 삼성디스플레이 주식회사 표시 장치
KR20200110554A (ko) * 2019-03-14 2020-09-24 삼성디스플레이 주식회사 표시 장치
CN109887416B (zh) * 2019-03-15 2021-12-10 京东方科技集团股份有限公司 柔性显示基板及其制造方法、显示装置
CN110246849A (zh) * 2019-05-17 2019-09-17 武汉华星光电半导体显示技术有限公司 阵列基板
KR20200140980A (ko) * 2019-06-07 2020-12-17 삼성디스플레이 주식회사 표시 장치
CN110197845B (zh) * 2019-06-20 2021-06-25 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
KR102671010B1 (ko) * 2019-06-25 2024-06-03 삼성디스플레이 주식회사 표시 장치
KR20210004008A (ko) * 2019-07-02 2021-01-13 삼성디스플레이 주식회사 표시장치
CN110429088A (zh) * 2019-07-18 2019-11-08 武汉华星光电半导体显示技术有限公司 一种tft阵列基板及其显示面板
KR20210014810A (ko) * 2019-07-30 2021-02-10 삼성디스플레이 주식회사 표시 장치
KR20210025160A (ko) * 2019-08-26 2021-03-09 삼성디스플레이 주식회사 디스플레이 패널 및 이를 포함하는 디스플레이 장치
KR20210025747A (ko) * 2019-08-27 2021-03-10 삼성디스플레이 주식회사 표시 장치
KR20210027676A (ko) * 2019-08-30 2021-03-11 삼성디스플레이 주식회사 디스플레이 장치
KR20210027641A (ko) 2019-08-30 2021-03-11 삼성디스플레이 주식회사 표시패널
CN111106154A (zh) * 2019-12-12 2020-05-05 武汉华星光电半导体显示技术有限公司 一种柔性显示面板及其制造方法
KR20210080671A (ko) * 2019-12-20 2021-07-01 삼성디스플레이 주식회사 표시장치
CN111063721A (zh) * 2020-01-06 2020-04-24 武汉华星光电半导体显示技术有限公司 Oled显示面板及显示装置
KR20210113532A (ko) * 2020-03-06 2021-09-16 삼성디스플레이 주식회사 디스플레이 장치
EP4340579A3 (fr) * 2020-03-23 2024-06-12 BOE Technology Group Co., Ltd. Substrat d'affichage, son procédé de préparation, plaque mère d'affichage et dispositif d'affichage
JP7369280B2 (ja) * 2020-04-20 2023-10-25 シャープ株式会社 表示装置および表示装置の製造方法
KR20210130879A (ko) * 2020-04-22 2021-11-02 삼성디스플레이 주식회사 표시 장치
KR20220010692A (ko) * 2020-07-17 2022-01-26 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN115669272A (zh) * 2020-12-18 2023-01-31 京东方科技集团股份有限公司 显示基板、显示面板和显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140042406A1 (en) * 2012-08-07 2014-02-13 Apple Inc. Flexible Displays
WO2016032175A1 (fr) * 2014-08-30 2016-03-03 LG Display Co.,Ltd. Dispositif d'affichage souple muni de fil comprenant une partie renforcée, et son procédé de fabrication
EP3051333A1 (fr) * 2015-01-28 2016-08-03 Samsung Display Co., Ltd. Dispositif d'affichage

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101965257B1 (ko) 2012-10-08 2019-04-04 삼성디스플레이 주식회사 플렉시블 표시 장치
KR102222680B1 (ko) 2013-02-01 2021-03-03 엘지디스플레이 주식회사 플렉서블 디스플레이 기판, 플렉서블 유기 발광 표시 장치 및 플렉서블 유기 발광 표시 장치 제조 방법
KR102047729B1 (ko) * 2013-04-30 2019-11-22 엘지디스플레이 주식회사 유기전계발광표시장치 및 그 제조방법
KR102207563B1 (ko) * 2013-10-29 2021-01-27 삼성디스플레이 주식회사 유기 발광 표시장치 및 유기 발광 표시장치의 제조 방법
KR102253870B1 (ko) * 2014-08-11 2021-05-21 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102352182B1 (ko) * 2015-01-23 2022-01-17 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR102275685B1 (ko) * 2015-01-29 2021-07-12 한국전자통신연구원 콘텐츠 제공 방법 및 상기 방법을 수행하는 콘텐츠 제공 서버, 해설자 단말
KR102370035B1 (ko) * 2015-02-05 2022-03-07 삼성디스플레이 주식회사 투명 표시 기판, 투명 표시 장치 및 투명 표시 장치의 제조 방법
JP2016195000A (ja) * 2015-03-31 2016-11-17 セイコーエプソン株式会社 有機発光装置および電子機器
KR102631257B1 (ko) * 2016-11-18 2024-01-31 삼성디스플레이 주식회사 디스플레이 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140042406A1 (en) * 2012-08-07 2014-02-13 Apple Inc. Flexible Displays
WO2016032175A1 (fr) * 2014-08-30 2016-03-03 LG Display Co.,Ltd. Dispositif d'affichage souple muni de fil comprenant une partie renforcée, et son procédé de fabrication
EP3051333A1 (fr) * 2015-01-28 2016-08-03 Samsung Display Co., Ltd. Dispositif d'affichage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3522228A1 (fr) * 2018-02-02 2019-08-07 Samsung Display Co., Ltd Afficheur souple et afficheur tactile
US10797251B2 (en) 2018-02-02 2020-10-06 Samsung Display Co., Ltd. Flexible display apparatus and touch sensitive display apparatus
US11398534B2 (en) 2018-02-02 2022-07-26 Samsung Display Co., Ltd. Flexible display apparatus and touch sensitive display apparatus
EP3859783A4 (fr) * 2018-09-27 2022-06-22 Boe Technology Group Co., Ltd. Substrat matriciel, panneau d'affichage et appareil d'affichage

Also Published As

Publication number Publication date
US20180145125A1 (en) 2018-05-24
US20190165081A1 (en) 2019-05-30
CN108074960A (zh) 2018-05-25
CN108074960B (zh) 2023-08-22
EP3327809B1 (fr) 2019-10-30
KR102631257B1 (ko) 2024-01-31
KR20180056497A (ko) 2018-05-29
US10916616B2 (en) 2021-02-09
US10211277B2 (en) 2019-02-19

Similar Documents

Publication Publication Date Title
EP3327809B1 (fr) Afficheur
US11908854B2 (en) Display device
US11805688B2 (en) Bendable display device
KR102537445B1 (ko) 디스플레이 장치 및 그 제조 방법
US11088232B2 (en) Display device
US11043551B2 (en) Display device
KR102562901B1 (ko) 디스플레이 장치
US11335761B2 (en) Display apparatus
CN113555393A (zh) 显示装置
US20230320152A1 (en) Display apparatus
US20230422559A1 (en) Display apparatus

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20181130

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 27/32 20060101ALI20190405BHEP

Ipc: H01L 51/00 20060101AFI20190405BHEP

INTG Intention to grant announced

Effective date: 20190509

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1197099

Country of ref document: AT

Kind code of ref document: T

Effective date: 20191115

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602017008202

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: NL

Ref legal event code: FP

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200131

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200130

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200302

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200229

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191116

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602017008202

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1197099

Country of ref document: AT

Kind code of ref document: T

Effective date: 20191030

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20191130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20200731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191116

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20171116

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20201130

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20201130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20191030

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602017008202

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0051000000

Ipc: H10K0099000000

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230516

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20231024

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20231023

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20231024

Year of fee payment: 7

Ref country code: DE

Payment date: 20231023

Year of fee payment: 7