EP2973723B1 - Composants transistors à effet de champ dotés de régions protectrices - Google Patents

Composants transistors à effet de champ dotés de régions protectrices Download PDF

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EP2973723B1
EP2973723B1 EP14778304.7A EP14778304A EP2973723B1 EP 2973723 B1 EP2973723 B1 EP 2973723B1 EP 14778304 A EP14778304 A EP 14778304A EP 2973723 B1 EP2973723 B1 EP 2973723B1
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layer
region
trench
forming
source
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EP2973723A1 (fr
EP2973723A4 (fr
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Lin Cheng
Anant Agarwal
Vipindas Pala
John Palmour
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Wolfspeed Inc
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Wolfspeed Inc
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to fabrication methods of transistor devices. More particularly, the present invention relates to fabrication methods related to high power insulated gate field effect and bipolar transistors
  • Power semiconductor devices are widely used to regulate large current, high voltage, and/or high frequency signals.
  • Modern power electronic devices are generally fabricated from monocrystalline silicon semiconductor material.
  • One widely used power device is the power Metal Oxide Semiconductor (MOS) Field Effect Transistor (MOSFET).
  • MOSFET Metal Oxide Semiconductor
  • a control signal is supplied to a gate electrode that is separated from the semiconductor surface by an intervening silicon dioxide insulator.
  • Current conduction occurs via transport of majority carriers, without the presence of minority carrier injection that is used in bipolar transistor operation.
  • MOSFETS can be formed on a silicon carbide (SiC) layer.
  • Silicon carbide (SiC) has a combination of electrical and physical properties that make it attractive as a semiconductor material for high temperature, high voltage, high frequency and/or high power electronic circuits. These properties include a 3.2 eV energy bandgap, an electric breakdown of about 2.4 MV/cm, a 4.9 W/cm-K thermal conductivity, and a 2.0 ⁇ 107 cm/s electron drift velocity.
  • silicon carbide-based power electronic devices may operate at higher junction temperatures, higher power density levels, higher frequencies (e.g., radio, S band, X band), and/or with lower specific on-resistance and/or higher blocking voltages than silicon-based power electronic devices.
  • a power MOSFET fabricated in silicon carbide is described in U.S. Pat. No. 5,506,421 to Palmour entitled "Power MOSFET in Silicon Carbide" and assigned to the assignee of the present invention.
  • silicon carbide itself is theoretically capable of sustaining high reverse voltages, it may be desirable to shield certain portions or features of a silicon carbide device, such as the gate insulator, the device edge, etc., from high electric fields, as breakdown may be more likely to occur at these locations.
  • EP-2068363 relates to a transistor structure that optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on- state.
  • the AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device.
  • JP-2012/069797 concerns an insulated gate transistor having a trench-type gate electrode.
  • a method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer having the second conductivity type on the drift layer including the first region, forming a source layer on the body layer, the source layer having the first conductivity type, and forming a body contact region having the second conductivity type, the body contact region extending through the source layer and the body layer and into the first region.
  • the method further includes forming a trench in the source layer and the body layer, the trench extending into the drift layer adjacent the first region and having an inner sidewall facing away from the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
  • Forming the first region includes selectively implanting dopants into the drift layer.
  • Selectively implanting dopant atoms into the drift layer includes selectively implanting dopants at an implant energy of less than 1000 keV or in some embodiments less than about 10 keV.
  • a distance between the first region and a bottom corner of the trench may be about 0.1 microns to about 3 microns, while a vertical distance between bottom of the first region and a bottom corner of the trench may be about 0.1 microns to about 2 microns.
  • the body layer and the source layer may be formed by epitaxial regrowth.
  • the body layer may be formed by epitaxial regrowth and the source layer may be formed by ion implantation.
  • The includes doping an upper portion of the drift layer adjacent the trench with first conductivity type dopants more heavily than a lower portion of the drift layer to form a current spreading region in the upper portion of the drift layer.
  • the first region is shallower than the current spreading region.
  • the methods may forming an epitaxial channel layer on a sidewall of the trench, the epitaxial channel layer having the second conductivity type.
  • Forming the epitaxial channel layer may include forming a semiconductor layer having the second conductivity type on the source layer and on the sidewall and floor of the trench, and anisotropically etching the semiconductor layer to remove the semiconductor layer from the source layer and from the floor of the trench to thereby form a channel layer on the sidewall of the trench adjacent the source layer and the body layer.
  • Embodiments of the invention provide silicon carbide (SiC) insulated gate devices that are suitable for high power and/or high temperature applications.
  • SiC silicon carbide
  • Embodiments of the present invention provide trench UMOS structures that include highly doped well regions in the drift layer that protect the bottom corners of the UMOS trench from high electric fields in reverse blocking conditions.
  • a current spreading layer is provided at an upper surface of the drift layer that may reduce spreading resistance that may be increased due to the presence of the highly doped well regions.
  • some embodiments of the present invention provide structures that protect the lower corners of the trench against high electric fields while maintaining low on-resistance.
  • a unit cell 10 of a conventional MOSFET structure is shown in Fig. 1 .
  • the device 10 includes an n-type epitaxial drift layer 14 on an n+ 4H-SiC substrate 12.
  • the structure further includes a p-type body region 16 on the drift layer 14 and an n+ source region 24 on the p-body region 16.
  • the structure 10 further includes p+ body contact regions 15 that extend through the n+ source region 24 and into the p-type body region 16.
  • a trench 70 extends through the n+ source region 24 and the p-body region 16 and into the n-type drift layer 14.
  • a gate insulator 32 is formed on sidewall surfaces and bottom surfaces of the trench 70.
  • a doped polysilicon gate electrode 34 is on the gate insulator 32.
  • Source ohmic contacts 43 are formed on the body contact regions 15 as well as on the source region 24.
  • a drain contact 40 is on the substrate 12 opposite the drift layer 14.
  • a typical device mesa where both n+ and p+ metal contacts are made to the source region 24 and the body contact regions 15 is in the range of sub-micron to several microns wide.
  • the body contact regions 15 may be formed to extend into the drift layer 14, and may provide some protection to the lower corners of the trench 70.
  • the thickness of the source region 24 and the p-body region 16 it is difficult to control the distance between the body contact regions 15 and the bottom corners of the trench 70 so that the distance is small enough to provide electrical shielding but not so small as to undesirably increase the on-resistance of the device.
  • lateral implantation straggle may cause the body contact regions 15 to extend close enough to the trench 70 to affect the MOS threshold voltage and inversion channel mobility.
  • a unit cell 100 of a MOSFET structure according to some examples is shown in Fig. 2 .
  • the device 100 includes an epitaxial drift layer 14 having a first conductivity type on a substrate 12.
  • the substrate 12 may be a 2° to 8° off-axis 4H-SiC substrate, although other substrates or substrate materials may be used.
  • the epitaxial layers may also include silicon carbide and/or other materials.
  • the drift layer 14 may have a thickness of about 5 ⁇ m to about 200 ⁇ m, and may be doped with n-type dopants at a doping concentration of about 5 ⁇ 10 13 cm -3 to about 2 ⁇ 10 16 cm -3 . Other doping concentrations/voltage blocking ranges are also possible.
  • the device 100 further includes a second conductivity type body region 16 and a first conductivity type source region 24 that may be formed by selective implantation of opposite conductivity type dopants, respectively, into the drift layer 14. Alternatively, one or both of the body region 16 and the source region 24 may be formed by epitaxial growth on the drift layer 14.
  • the source region 24 has the same conductivity type as the drift layer (i.e., the first conductivity type), while the body region 16 has the second conductivity type.
  • the body region 16 may have a doping concentration from about 1 ⁇ 10 15 cm -3 to about 5 ⁇ 10 18 cm -3 and may have a thickness of about 0.1 ⁇ m to 10 ⁇ m. In particular embodiments, the body region 16 may have a doping concentration of about 2 ⁇ 10 18 cm -3 and may have a thickness of about 0.5 ⁇ m to 2 ⁇ m
  • a trench 70 extends through the source region 24 and the body region 16 and into the drift layer 14.
  • the device 100 further includes body contact regions 18 that extend through the source region 24 and the body region 16.
  • the body contact regions 18 have the second conductivity type.
  • Highly doped buried well regions 20 having the second conductivity type are formed at an upper surface of the drift layer 14.
  • the buried well regions 20 contact the body contact regions 18 and extend towards respective lower corners 70A, 70B of the trench 70.
  • a distance d from the buried well region 20 to a corresponding lower corner 70A, 70B of the trench may be about 0.1 ⁇ m to about 3 ⁇ m. In some embodiments, the distance d may be about 0.5 ⁇ m to 2 ⁇ m, and in some embodiments, the distance d may be about 0.8 ⁇ m to 1 ⁇ m.
  • the buried well regions 20 may be formed by selective ion implantation into the drift layer 14 before formation of the body region 16 by epitaxial regrowth. Accordingly, the buried well regions 20 may be formed using low energy implantation, which may reduce implant straggle and may provide more precise control over the locations of the buried well regions 20 and, more particularly, more precise control over the distance d between the buried well regions 20 and the lower corners 70A, 70B of the trench 70.
  • the body contact regions 18 and the buried well regions 20 may be formed by implanting a first species of dopant ion through the source layer 24 and the body layer 16 to form the body contact regions 18 and implanting a second species of dopant ion into the source layer 24 and the body layer 16 and into the drift layer 14 to form the buried well regions 20, where the second species of dopant has a greater diffusivity in the semiconductor material than the first species of dopant.
  • the structure is then annealed to cause the second species of dopant to diffuse closer to the trench corners than the first species of dopant.
  • the semiconductor material may include silicon carbide
  • the first species of dopant may include aluminum
  • the second species of dopant may include boron, which has a higher diffusivity in silicon carbide than aluminum.
  • the buried well regions 20 may have a doping concentration from about 1 ⁇ 10 18 cm -3 to about 1 ⁇ 10 21 cm -3 and may extend a depth of about 0.1 ⁇ m to 5 ⁇ m into the drift layer 14.
  • the heavily doped source layer 24 can be epitaxially grown or formed by selective ion implantation into the body layer 16.
  • the source layer 24 may have a thickness of 0.1 ⁇ m to 1 ⁇ m and may have a doping concentration in the range of 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 .
  • Source ohmic contacts 43 are formed on exposed portions of the first body contact regions 18 as well as the source region 24.
  • the source ohmic contacts 43 may include, for example, Ni, Al, Ti, Si, etc.
  • a gate insulator 32 is formed on sidewall surfaces and bottom surfaces of the trench 70.
  • the gate insulator 32 may, for example, be silicon oxide, or silicon nitric oxide or a stack of both.
  • a gate electrode 34 is on the gate insulator 32.
  • the gate electrode 34 may, for example, include doped polysilicon.
  • the gate electrode 34 may also extend up over the channel layer 34 and onto the source region 24.
  • Figures 3A to 3E are cross sectional views illustrating the fabrication of a power MOSFET device according to some examples.
  • the substrate 12 may be an off-axis SiC substrate having the 2H, 4H, 6H, 3C or 15R polytype.
  • the substrate 12 may be an n+ 2° to 8° off-axis 4H SiC substrate.
  • a drift layer 14 is formed on the substrate 12.
  • the drift layer 14 may have a thickness of about 5 ⁇ m to 200 ⁇ m, and may be doped with n-type dopants, such as nitrogen or phosphorus, at a doping concentration of about 5 ⁇ cm -3 to about 2 ⁇ 10 16 cm -3 .
  • n-type dopants such as nitrogen or phosphorus
  • the substrate may include a 4° off-axis 4H-SiC substrate and the drift layer may have a thickness of about 12 ⁇ m and may be doped with dopants at a doping concentration of about 6 ⁇ 10 15 cm -3 .
  • buried well regions 20 may be formed in the drift layer 14 by selective implantation of p-type dopant ions 13, such as aluminum ions, into the drift layer 14.
  • the p-type dopant ions may be implanted to have a uniform or non-uniform doping profile, such as a graded doping profile.
  • the p-type dopant ions may be implanted such that the buried well regions may have a doping concentration of about 1 ⁇ 10 18 cm -3 to about 1 ⁇ 10 21 cm -3 and may extend a depth of about 0.1 ⁇ m to 1 ⁇ m into the drift layer 14.
  • a body region 16 is formed on the drift layer 14.
  • the body region 16 may be doped with p-type dopants at a doping concentration of about 1 to 2 ⁇ 10 18 cm -3 , and may have a thickness of about 0.5 ⁇ m to about 2 ⁇ m.
  • the body region 16 may be formed by ion implantation and/or epitaxial growth on the drift layer 14.
  • a source region 24 is formed on the body region 16.
  • the source region 24 may be doped with n-type dopants at a doping concentration of about 1 ⁇ 10 18 cm -3 to about 1 ⁇ 10 21 cm -3 , and may have a thickness of about 0.1 ⁇ m to about 1 ⁇ m.
  • the source region 24 may be formed by ion implantation and/or epitaxial growth.
  • the doping profile in the source region 24 may be uniform in some embodiments. In other embodiments, the doping profile in the source region 24 may have a gradient and/or a delta doping profile.
  • body contact regions 18 are formed by ion implantation into the structure on a side of the epitaxial region opposite the substrate 12.
  • the body contact regions 18 may be formed to extend through the source region 24 and the body region 16 and into the buried well regions 20.
  • the body contact regions 18 may be formed using a multiple implant profile, resulting in a doping concentration of about 1 ⁇ 10 18 cm -3 to about 1 ⁇ 10 21 cm -3 .
  • the body contact region 18 may have a width of about 1 to 3 ⁇ m.
  • the implanted dopants may be activated by annealing the structure at a temperature of about 1500°C to 1800 °C with a silicon over pressure and/or covered by an encapsulation layer such as a graphite film.
  • a high temperature anneal may damage the surface of the silicon carbide epitaxy without these conditions.
  • the silicon overpressure may be provided by the presence of silane, or the close proximity of silicon carbide coated objects that provide a certain amount of silicon overpressure.
  • a graphite coating may be formed on the surface of the device.
  • a graphite coating may be applied to the top/front side of the structure in order to protect the surface of the structure from silicon out-diffusion during the anneal.
  • the graphite coating may be applied by a conventional resist coating method and may have a thickness of about 0.5 ⁇ m to 10 ⁇ m.
  • the graphite coating may be heated to form a crystalline coating on the drift layer 14.
  • the implanted ions may be activated by a thermal anneal that may be performed, for example, in an inert gas at a temperature of about 1500 °C or greater. In particular the thermal anneal may be performed at a temperature of about 1650 °C in argon for 30 minutes.
  • the graphite coating may help to protect the surface of the drift layer 14 from silicon out-diffusion during the high temperature anneal.
  • the graphite coating may then be removed, for example, by ashing and/or thermal oxidation.
  • a trench 70 is formed in the structure between the body contact regions 18.
  • the trench may be sized so that lower corners 70A, 70B of the trench are spaced about 0.1 ⁇ m to 2 ⁇ m from the edges of the respective buried well regions 20 in a lateral direction.
  • the trench 70 extends through the source layer 24 and the body layer 16 to the drift layer 14.
  • a gate insulator 32 is formed in the trench 70 by a gate oxidation process, with a final gate oxide thickness of 200-2000 ⁇ .
  • the gate insulator 32 may be formed using an annealed high temperature or a PECVD deposition process.
  • an oxide layer may be grown by a dry-wet oxidation process that includes a growth of bulk oxide in dry O2 followed by an anneal of the bulk oxide in wet O2 as described, for example, in U.S. Patent No. 5,972,801 .
  • anneal of oxide in wet O 2 refers to anneal of an oxide in an ambient containing both O2 and vaporized H 2 O.
  • An anneal may be performed in between the dry oxide growth and the wet oxide growth.
  • the dry O 2 oxide growth may be performed, for example, in a quartz tube at a temperature of up to about 1300 °C in dry O 2 for a time of about 0.5 to 2 hours. Dry oxide growth is performed to grow the bulk oxide layer to a desired thickness.
  • the temperature of the dry oxide growth may affect the oxide growth rate. For example, higher process temperatures may produce higher oxide growth rates. The maximum growth temperature may be dependent on the system used.
  • a polysilicon gate 34 may be deposited in the trench 70 and doped, for example, with boron and/or phosphorus.
  • Ni may be deposited as the n-type source ohmic contact 43 and the drain ohmic contact 40.
  • the contacts may be sintered by rapid thermal annealing (RTA).
  • Figure 4 is a cross sectional illustration of a unit cell 200 of a MOSFET structure according to an embodiment.
  • the structure of the device 200 is similar to the structure of the device 100, except that the drift layer 14 of the device 200 includes a first sub-layer 14A at the lower part of the drift layer 14 adjacent the substrate 12 and a second sub-layer 14B at the upper part of the drift layer 14 opposite the substrate 12.
  • the second sub-layer 14B has a higher doping concentration than the first sub-layer 14A.
  • the first sub-layer 14A may have a doping concentration of about 5 ⁇ 10 13 to 2 ⁇ 10 16 cm -3
  • the second sub-layer 14B may have a doping concentration of about 5 ⁇ 10 15 to 1 ⁇ 10 17 cm -3 .
  • the second sub-layer 14B has a thickness that is greater than the depth of the buried well regions 20. That is, the buried well regions 20 extend into the second sub-layer 14B but do not extend all the way to the first sub-layer 14A. In some embodiments, the second sub-layer 14B may have a thickness of about 0.5 to 3 ⁇ m.
  • the second sub-layer 14B may reduce the spreading resistance of the device that may otherwise be increased due to presence of the buried well regions 20.
  • Figures 5A to 5F are cross sectional views illustrating the fabrication of a power MOSFET device according to further examples.
  • a drift layer 14, a body layer 16 and a source layer 24 are formed by epitaxial growth on a substrate 12.
  • the drift layer 14, body layer 16, a source layer 24 and substrate 12 may be similar to the corresponding layers/regions in the device structure 100 illustrated in Figure 2 .
  • An implant mask 25 including openings 26A, 26B is formed on the source layer 24, and first dopant ions 27 are implanted through the openings 26A, 26B and into the epitaxial structure.
  • the implant energy and dose are selected to form buried well regions 120 at the surface of the drift layer 14.
  • the first dopant ions may include boron and may be implanted at a dose of greater than 5 ⁇ 10 13 cm -2 and an implantation energy greater than about 300 keV.
  • second dopant ions 29 may then be implanted through the openings 26A, 26B into the body layer 16 and the source layer 24 to form the body contact regions 18.
  • the implant energy and dose are selected to form body contact regions 18 that extend from an upper surface of the source layer 24 to the buried well regions 120.
  • the second dopant ions 29 may have a lower diffusivity in the semiconductor material than the first dopant ions 27.
  • the second dopant ions 29 may include aluminum and may be implanted at a dose of 1 ⁇ 10 15 cm -2 and an implant energy greater than 200 keV.
  • the implanted ions may be annealed as described above to activate the implants.
  • the activation anneal may be performed at a sufficient temperature and for a sufficient time to cause the second dopant ions in the buried well region 120 to diffuse outward.
  • the buried well regions 120 may extend laterally away from the body contact regions 18 by a width w that may be at least about 2 ⁇ m, although the width w could be more or less than 2 ⁇ m.
  • trench 70 is formed in the structure between the body contact regions 18.
  • the trench may be sized so that lower corners 70A, 70B of the trench are spaced about 0.1 ⁇ m to 1 ⁇ m from the edges of the respective buried well regions 120.
  • the trench 70 extends through the source layer 24 and the body layer 16 to the drift layer 14.
  • a gate insulator 32 is formed in the trench 70 by a gate oxidation process, with a final gate oxide thickness of 200-2000 ⁇ .
  • a polysilicon gate 34 may be deposited in the trench 70 and doped, for example, with boron. Ni may be deposited and sintered to form the n-type source ohmic contact 43 and the drain ohmic contact 40.
  • the IGBT device includes an n- drift epitaxial layer 214 on a p-type epitaxial layer 212.
  • the p-type epitaxial layer 212 is formed on a heavily doped p-type, 2° to 8° off-axis 4H-SiC substrate or layer 210.
  • the n- drift layer 214 may have a thickness of about 80 ⁇ m to about 200 ⁇ m, and may be doped with n-type dopants at a doping concentration of about 5 ⁇ 10 13 cm -3 to about 6 ⁇ 10 14 cm -3 for a blocking capability exceeding 10 kV.
  • the device 300 includes collector ohmic contacts 243 on a collector region 224 and an emitter contact 245 on the substrate 210.
  • the remainder of the structure is similar to the structure shown in Figure 1 .
  • Some embodiments of the present invention provide trench UMOS structures that include epitaxially regrown channel layers on the sidewalls of the trench, wherein the channel layers have the same conductivity type as the body layers.
  • an n-channel UMOS device may include a p-type epitaxial channel layer on a sidewall of the UMOS trench.
  • the epitaxially regrown channel layers may improve inversion channel mobility as well as maintain a high threshold voltage.
  • n-channel vertical-trench MOSFET structures typically include a p-type trench sidewall that is formed by a selective plasma dry etch.
  • the crystal structure of the etched surface may be very poor, which can degrade the inversion channel mobility and lead to poor MOS channel conductivity.
  • a conventional approach to overcome this problem in an n-channel device is to form a thin, lightly doped n-type channel layer by epitaxial regrowth on a vertical sidewall of the trench.
  • the n-type channel layer acts as an accumulation layer and provides a current path that connects the n-type source and drain regions of the device.
  • forward conduction of the device may be greatly improved.
  • providing an n-type channel layer on a p-type body region may lower the threshold voltage of the device, which affects the off-state blocking capability and reliability of the device, especially at high temperatures.
  • some embodiments of the present invention provide an epitaxial channel layer on a sidewall of a UMOS trench that has the opposite conductivity type from the source/drain regions (i.e. for an n-channel device, the epitaxial channel layer is p-type).
  • the gate insulator and gate are arranged so that both horizontal and vertical inversion layers are formed in the epitaxial channel layer upon application of a gate voltage, which provides a current path between the source and drain regions of the device during forward operation.
  • the device 400 includes a channel layer 30 formed on a sidewall of the trench 70.
  • the channel layer 30 may have the second conductivity type. That is, when the body region 16 is p-type, the channel layer 30 may also be p-type.
  • the channel layer 30 may be formed by epitaxial regrowth, which may allow the channel layer 30 to have a high crystal quality and/or a tightly controlled doping level.
  • a gate insulator 32 is on sidewall surfaces and bottom surfaces of the trench 70.
  • the gate insulator 32 may extend up over the channel layer 30 and onto the source region 24.
  • a gate electrode 34 is on the gate insulator 32.
  • the gate electrode 34 may, for example, include doped polysilicon.
  • the gate conductor 34 may also extend up over the channel layer 34 and onto the source region 24.
  • an inversion channel is formed at both a side surface and an upper surface of the channel layer 30, allowing charge carriers to flow from the source region 24 through the channel layer 30 and to the drift layer 14 along the path 60.
  • Forming the channel layer to have the same conductivity type as the body region 16 may increase the threshold voltage by about 1 volt, which can significantly decrease leakage current in the device.
  • the channel layer 30 formed on the sidewall of the trench 30 may provide a SiC layer with a high crystal quality, which may improve the quality of the interface between the channel layer 30 and the gate insulator 32. This may improve the inversion channel mobility, and may also maintain the threshold voltage high enough for robust off-state performance as well as improving long term reliability and high temperature stability.
  • the channel layer 30 may be formed by epitaxially growing a semiconductor layer having the same conductivity type as the body region 16 on the source layer and on the sidewall and floor of the trench 70, then anisotropically etching the semiconductor layer to remove the semiconductor layer from the source layer and from the floor of the trench to thereby form the channel layer 30 on the sidewall of the trench adjacent the source layer and the body layer.
  • IGBT and MOSFET devices having n-type drift layers the present invention is not limited thereto, and may be embodied in devices having p-type substrates and/or drift layers. Furthermore, the invention may be used in many different types of devices, including but not limited to insulated gate bipolar transistors (IGBTs), MOS controlled thyristors (MCTs), insulated gate commutated thyristors (IGCTs), junction field effect transistors (JFETs), high electron mobility transistors (HEMTs), etc.
  • IGBTs insulated gate bipolar transistors
  • MCTs MOS controlled thyristors
  • IGCTs insulated gate commutated thyristors
  • JFETs junction field effect transistors
  • HEMTs high electron mobility transistors
  • Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention.
  • the thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected.
  • embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
  • an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • n-type material has a majority equilibrium concentration of negatively charged electrons
  • p-type material has a majority equilibrium concentration of positively charged holes.
  • Some material may be designated with a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, p--, or the like), to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region.
  • such notation does not imply the existence of a particular concentration of majority or minority carriers in a layer or region.

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Claims (8)

  1. Procédé de formation d'un dispositif transistor, comprenant les étapes consistant à :
    fournir une couche flottante (14) comprenant du carbure de silicium présentant un premier type de conductivité ;
    doper une partie supérieure de la couche flottante (14B) avec des dopants du premier type de conductivité plus lourdement qu'une partie inférieure de la couche flottante (14A) pour former une région d'étalement de courant dans la partie supérieure de la couche flottante (14B) ;
    former une première région (20) dans la couche flottante (14), la première région présentant un second type de conductivité qui est opposé au premier type de conductivité, dans lequel la profondeur à laquelle la première région (20) s'étend dans la couche flottante est inférieure à une épaisseur de la partie supérieure de la couche flottante (14B) ;
    former une couche de corps (16) comprenant du carbure de silicium présentant le second type de conductivité sur la couche flottante (14) incluant la première région (20) ;
    former une couche de source (24) comprenant du carbure de silicium sur la couche de corps (16), la couche de source (24) présentant le premier type de conductivité ;
    former une région de contact de corps (18) présentant le second type de conductivité, la région de contact de corps (18) s'étendant à travers la couche de source (24) et la couche de corps (16) et jusque dans la première région (20) ;
    former une tranchée (70) dans la couche de source (24) et la couche de corps (16), la tranchée (70) s'étendant dans la couche flottante (14) adjacente à la première région (20), la tranchée (70) présentant une paroi latérale interne orientée à l'opposé de la première région (20) ;
    former un isolant de grille (32) sur la paroi latérale interne de la tranchée (70) ;
    former un contact de grille (34) sur l'isolant de grille (32) ; et
    former un contact ohmique de source (43) sur la couche de source (24) et sur la région de contact de corps (18),
    dans lequel la région de contact de corps (18) connecte de manière conductrice la première région (20) au contact ohmique de source (43),
    dans lequel la formation de la première région (20) comprend une implantation de manière sélective de dopants dans la couche flottante (14) à une énergie d'implantation inférieure à 1000 keV à une concentration de dopage comprise entre 1 ×1018 cm-3 et 1 × 1021 cm-3.
  2. Procédé selon la revendication 1, dans lequel une distance entre la première région (20) et un coin inférieur de la tranchée (70A) proche de la première région est de 0,1 micron à 2 microns.
  3. Procédé selon l'une quelconque des revendications précédentes, comprenant en outre l'étape consistant à :
    former une couche de canal épitaxiale (30) sur une paroi latérale de la tranchée, la couche de canal épitaxiale (30) présentant le second type de conductivité.
  4. Procédé selon la revendication 3, dans lequel la formation de la couche de canal épitaxiale (30) comprend les étapes consistant à :
    former une couche semi-conductrice présentant le second type de conductivité sur la couche de source (24) et sur la paroi latérale et le fond de la tranchée (70) ;
    graver de manière anisotrope la couche semi-conductrice afin de retirer la couche semi-conductrice à partir de la couche de source (24) et du fond de la tranchée (70) pour ainsi former une couche de canal (30) sur la paroi latérale de la tranchée (70) adjacente à la couche de source (24) et à la couche de corps (16).
  5. Procédé selon la revendication 1, dans lequel la formation de l'isolant de grille (32) sur la paroi latérale interne de la tranchée (70) comprend la formation de l'isolant de grille (32) par un procédé d'oxydation de grille.
  6. Procédé selon la revendication 1, dans lequel la couche flottante est fournie sur un substrat de carbure de silicium 4H hors axe de 2° à 8°.
  7. Procédé selon l'une quelconque des revendications précédentes, dans lequel une distance entre la première région (20) et un coin inférieur de la tranchée (70A) est de 0,8 micron à 1 micron.
  8. Procédé selon l'une quelconque des revendications précédentes, dans lequel la profondeur jusqu'à laquelle la première région (20) s'étend dans la couche flottante (14) est de 0,1 µm à 1 µm.
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101438620B1 (ko) * 2012-12-27 2014-09-05 현대자동차 주식회사 쇼트키 배리어 다이오드 및 그 제조 방법
KR101360070B1 (ko) * 2012-12-27 2014-02-12 현대자동차 주식회사 반도체 소자 및 그 제조 방법
KR20140085141A (ko) * 2012-12-27 2014-07-07 현대자동차주식회사 반도체 소자 및 그 제조 방법
US9142668B2 (en) 2013-03-13 2015-09-22 Cree, Inc. Field effect transistor devices with buried well protection regions
US8987825B2 (en) * 2013-06-10 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a double deep well
WO2017138505A1 (fr) * 2016-02-12 2017-08-17 パナソニック株式会社 Dispositif à semi-conducteur
US10861931B2 (en) * 2016-12-08 2020-12-08 Cree, Inc. Power semiconductor devices having gate trenches and buried edge terminations and related methods
US11069804B2 (en) 2018-08-31 2021-07-20 Alpha And Omega Semiconductor (Cayman) Ltd. Integration of HVLDMOS with shared isolation region
DE102019210681A1 (de) 2019-05-31 2020-12-03 Robert Bosch Gmbh Leistungstransistorzelle und Leistungstransistor
WO2021100206A1 (fr) * 2019-11-22 2021-05-27 株式会社デンソー Élément commutateur
CN113097305B (zh) * 2021-03-26 2022-11-08 深圳市金誉半导体股份有限公司 一种场效应管及其制备方法
CN116581150B (zh) * 2023-07-13 2023-09-05 北京昕感科技有限责任公司 非对称双沟槽SiC MOSFET元胞结构、器件及制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010258386A (ja) * 2009-04-28 2010-11-11 Fuji Electric Systems Co Ltd 炭化珪素半導体装置およびその製造方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506421A (en) 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
DE69531282T2 (de) 1994-12-20 2004-05-27 STMicroelectronics, Inc., Carrollton Isolierung durch aktive Transistoren mit geerdeten Torelektroden
US5688725A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance
DE19636302C2 (de) 1995-09-06 1998-08-20 Denso Corp Siliziumkarbidhalbleitervorrichtung und Verfahren zur Herstellung
JP3419163B2 (ja) 1995-09-06 2003-06-23 株式会社デンソー 炭化珪素半導体装置の製造方法
JP4738562B2 (ja) * 2000-03-15 2011-08-03 三菱電機株式会社 半導体装置の製造方法
JP4696335B2 (ja) 2000-05-30 2011-06-08 株式会社デンソー 半導体装置およびその製造方法
TWI313059B (fr) 2000-12-08 2009-08-01 Sony Corporatio
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
WO2002084745A2 (fr) 2001-04-11 2002-10-24 Silicon Wireless Corporation Dispositifs semi-conducteurs de puissance presentant des zones ecran de base s'etendant lateralement qui empechent de traverser la base et procedes de fabrication associes
US7736976B2 (en) 2001-10-04 2010-06-15 Vishay General Semiconductor Llc Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
SE0104164L (sv) 2001-12-11 2003-06-12 Ericsson Telefon Ab L M Högspännings-mos-transistor
JP3677489B2 (ja) * 2002-05-29 2005-08-03 Ｎｅｃエレクトロニクス株式会社 縦型電界効果トランジスタ
US6974750B2 (en) 2003-06-11 2005-12-13 International Rectifier Corporation Process for forming a trench power MOS device suitable for large diameter wafers
US6974720B2 (en) 2003-10-16 2005-12-13 Cree, Inc. Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby
US20070029573A1 (en) 2005-08-08 2007-02-08 Lin Cheng Vertical-channel junction field-effect transistors having buried gates and methods of making
KR101529331B1 (ko) 2006-08-17 2015-06-16 크리 인코포레이티드 고전력 절연 게이트 바이폴라 트랜지스터
KR101375035B1 (ko) 2006-09-27 2014-03-14 맥스파워 세미컨덕터 인크. Ｍｏｓｆｅｔ 및 그 제조 방법
JP5479915B2 (ja) 2007-01-09 2014-04-23 マックスパワー・セミコンダクター・インコーポレイテッド 半導体装置
US7575968B2 (en) 2007-04-30 2009-08-18 Freescale Semiconductor, Inc. Inverse slope isolation and dual surface orientation integration
US8022472B2 (en) 2007-12-04 2011-09-20 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US7989882B2 (en) * 2007-12-07 2011-08-02 Cree, Inc. Transistor with A-face conductive channel and trench protecting well region
US7795691B2 (en) 2008-01-25 2010-09-14 Cree, Inc. Semiconductor transistor with P type re-grown channel layer
CN102007584B (zh) * 2008-02-14 2013-01-16 马克斯半导体股份有限公司 半导体装置结构及其相关工艺
US7960781B2 (en) 2008-09-08 2011-06-14 Semiconductor Components Industries, Llc Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method
WO2010148266A2 (fr) * 2009-06-19 2010-12-23 Semisouth Laboratories, Inc. Transistors à effet de champ à jonction verticale et diodes ayant des régions à gradient et procédés de fabrication
CN102422416B (zh) 2009-09-07 2014-05-14 丰田自动车株式会社 具备具有二极管区和igbt区的半导体基板的半导体装置
JP5170074B2 (ja) 2009-12-25 2013-03-27 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2011216587A (ja) 2010-03-31 2011-10-27 Renesas Electronics Corp 半導体装置
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
JP2012069797A (ja) 2010-09-24 2012-04-05 Toyota Motor Corp 絶縁ゲート型トランジスタ
JP2012160584A (ja) 2011-02-01 2012-08-23 Sumitomo Electric Ind Ltd 半導体装置
JP2012164707A (ja) 2011-02-03 2012-08-30 Panasonic Corp 半導体装置およびその製造方法
JP2012209422A (ja) 2011-03-30 2012-10-25 Sumitomo Electric Ind Ltd Ｉｇｂｔ
JP2012253108A (ja) 2011-06-01 2012-12-20 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
JP2012253293A (ja) 2011-06-07 2012-12-20 Sumitomo Electric Ind Ltd 半導体装置
US9054183B2 (en) 2012-07-13 2015-06-09 United Silicon Carbide, Inc. Trenched and implanted accumulation mode metal-oxide-semiconductor field-effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010258386A (ja) * 2009-04-28 2010-11-11 Fuji Electric Systems Co Ltd 炭化珪素半導体装置およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ITOH A ET AL: "Excellent reverse blocking characteristics of high-voltage 4H-SiC Schottky rectifiers with boron-implanted edge termination", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 17, no. 3, 1 March 1996 (1996-03-01), pages 139 - 141, XP011430182, ISSN: 0741-3106, DOI: 10.1109/55.485193 *

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