EP2852898B1 - Method and apparatus for memory access delay training - Google Patents

Method and apparatus for memory access delay training Download PDF

Info

Publication number
EP2852898B1
EP2852898B1 EP13728588.8A EP13728588A EP2852898B1 EP 2852898 B1 EP2852898 B1 EP 2852898B1 EP 13728588 A EP13728588 A EP 13728588A EP 2852898 B1 EP2852898 B1 EP 2852898B1
Authority
EP
European Patent Office
Prior art keywords
data strobe
enable signal
signal
preamble
strobe signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP13728588.8A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2852898A1 (en
Inventor
Glenn A. Dearth
Warren R. Anderson
Anwar P. Kashem
Richard W. Reeves
Edoardo Prete
Gerald R. Talbot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP2852898A1 publication Critical patent/EP2852898A1/en
Application granted granted Critical
Publication of EP2852898B1 publication Critical patent/EP2852898B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • This disclosure relates to computer systems, and more particularly, to training delay times for signal used to synchronize reads of memory in computer system.
  • determining a time when the data is valid is an important factor. To optimize computer system performance, minimizing this value may be desired. To determine the optimal time at which data received from a memory may be read, a training procedure may be performed.
  • a data strobe signal may be returned with data from the memory during a read operation.
  • the data strobe signal is a source synchronous clock signal that may be used to synchronize the data at a receiver in a memory controller, as well as indicating that the data is valid. Training of the data strobe signal to ensure correct timing may be performed at the beginning of system operation.
  • One method to perform training of a DDR data strobe begins with performing of reads at a low operational frequency known as a seed.
  • the training procedure may then conduct a series of reads to determine an optimal time to enable the data strobe signal to observe the returned data at a first frequency known as a seed.
  • the seed may be determined based on characterizations conducted in a lab during a design phase of the computer system.
  • the training may be conducted at different frequencies until the optimal time to enable the data strobe signal is determined.
  • the resulting trained optimal time at the original frequency may be used to calculate an approximate starting time for subsequent training at a next higher frequency.
  • the resulting second trained value may be used to calculate an approximate starting time for training at a third higher frequency, and so on.
  • the method of using trained times at lower frequencies to determine starting times for training at higher frequencies can be repeated multiple times until all frequencies that will be used in normal operation have been trained.
  • US 2006/136769 A1 is disclosing a memory controller for use in dynamic RAM system which masks strobe signal to generate masked strobe signal using delayed enable signal from latch circuit.
  • a system includes a memory controller configured to receive a data strobe signal.
  • the memory controller includes a training circuit.
  • the training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first storage circuit, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.
  • a method in one embodiment, includes adjusting a phase of an enable signal relative to a data strobe signal received from a memory.
  • the phase may be adjusted until an assertion of the enable signal coincides with a preamble indication in the data strobe signal. Adjusting may be accomplished by adjusting a delay of a delay locked loop (DLL).
  • the method further includes storing an indication of the delay into a register.
  • DLL delay locked loop
  • One embodiment of a memory subsystem includes a memory coupled to a memory controller.
  • the memory controller is configured to send a read request to the memory.
  • the memory is configured to, responsive to the read request, provide data and a data strobe signal to the memory controller.
  • the memory controller includes a training unit configured to adjust a phase of an enable signal relative to the data strobe signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal, wherein said adjusting comprises adjusting a delay of a delay locked loop (DLL).
  • DLL delay locked loop
  • the memory controller is further configured to store an indication of the delay into a register.
  • Fig. 1 is a block diagram of one embodiment of a computer system 10.
  • computer system 10 includes an integrated circuit (IC) 2 coupled to a memory 6.
  • Computer system 10 may include, for example, a conventional computer system such as a laptop, desktop or server computer, or various other types of computing devices such as, for example, handheld computing devices (e.g., mobile phones or smart phones), digital televisions, tablet computing devices and the like.
  • IC 2 is a system on a chip (SoC) having a number of processor cores 11.
  • Embodiments of IC 2 may include central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), application processors, digital signal processors (DSPs) and the like.
  • CPUs central processing units
  • GPUs graphics processing units
  • APUs accelerated processing units
  • DSPs digital signal processors
  • processor cores 11 may be identical to each other (i.e. homogenous multi-core), or one or more cores may be different from others (i.e. heterogeneous multi-core).
  • Processor cores 11 may each include one or more execution units, cache memories, schedulers, branch prediction circuits, and so forth.
  • each of processor cores 11 may be configured to assert requests for access to memory 6, which may function as the main memory for computer system 10. Such requests may include read requests and/or write requests, and may be initially received from a respective processor core 11 by north bridge 12. Requests for access to memory 6 may be initiated responsive to the execution of certain instructions, and may also be initiated responsive to prefetch operations.
  • North bridge 12 in the embodiment shown may provide routing and control of communications between the various functional units of IC 2.
  • north bridge 12 may include one or more crossbar units configured to couple different functional units to one another (e.g., coupling one of the processor cores 11 to memory controller 18 during a memory access request).
  • north bridge 12 may implement various power management functions used to optimize power consumption vs. performance during the operation of IC 2.
  • I/O interface 13 is also coupled to north bridge 12 in the embodiment shown. I/O interface 13 may function as a south bridge device in computer system 10.
  • I/O interface 13 may function as a south bridge device in computer system 10.
  • peripheral buses may be coupled to I/O interface 13.
  • the bus types include a Peripheral Component Interconnect (PCI) bus, a PCI-Extended (PCI-X), a gigabit Ethernet (GBE) bus, and a Universal Serial Bus (USB).
  • PCI Peripheral Component Interconnect
  • PCI-X PCI-Extended
  • GBE gigabit Ethernet
  • USB Universal Serial Bus
  • Peripheral devices may be coupled to some or all of the peripheral buses.
  • peripheral devices include (but are not limited to) keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.
  • I/O unit 13 may assert memory access requests using direct memory access (DMA). These requests (which may include read and write requests) may be conveyed to north bridge 12 via I/O interface 13.
  • DMA direct memory access
  • IC 2 includes a graphics processing unit 14 that is coupled to display 3 of computer system 10.
  • Display 3 may be a flat-panel LCD (liquid crystal display), plasma display, a CRT (cathode ray tube), or any other suitable display type.
  • GPU 14 may perform various video processing functions and provide the processed information to display 3 for output as visual information.
  • Memory controller 18 in the embodiment shown is coupled to north bridge 12, and in some embodiments, may actually be a component of north bridge 12.
  • Memory controller 18 may receive memory requests conveyed from north bridge 12.
  • Data accessed from memory 6 responsive to a read request may be conveyed by memory controller 18 to the requesting agent via north bridge 12.
  • Responsive to a write request memory controller 18 may receive both the request and the data to be written from the requesting agent via north bridge 12. If multiple memory access requests are pending at a given time, memory controller 18 may arbitrate between these requests.
  • memory controller 18 also includes functionality to support writes of data to memory 6, although that functionality is not shown here for the sake of simplicity.
  • Memory 6 in the embodiment shown may be implemented in one embodiment as a plurality of memory modules. Each of the memory modules may include one or more memory devices (e.g., memory chips) mounted thereon. In another embodiment, memory 6 may include one or more memory devices mounted on a motherboard or other carrier upon which IC 2 may also be mounted. In yet another embodiment, at least a portion of memory 6 may be implemented on the die of IC 2 itself. Embodiments having a combination of the various implementations described above are also possible and contemplated. Memory 6 may be used to implement a random access memory (RAM) for use with IC 2 during operation.
  • RAM random access memory
  • memory 6 is implemented as one of a number of different types of double data rate (DDR) dynamic RAM (DRAM). Such types of DDR DRAM includes the original DDR standard DRAM, DDR2 DRAM, and DDR3 DRAM. It is also contemplated that memory 6 may be implemented as a future standard of DDR DRAM. Irrespective of the particular standard, memory 6 may, responsive to a read request from memory controller 18, return a data strobe signal, DQS, along with the requested data.
  • the data strobe signal is effectively a source synchronous clock signal used to synchronize the data in receiver 25 of memory controller 18. When no data is being returned from memory 6, the data strobe signal may be idle or may be tri-stated.
  • the data strobe signal may be tri-stated (i.e., placed in a high impedance state) when reads are not being performed. If the data strobe signal is sampled while tri-stated, it may lead to unpredictable behavior, including erroneous reads and corruption of the internal operation of a delay locked loop (DLL) in receiver 25. However, the method and apparatus embodiments discussed below may avoid sampling the data strobe signal when it is tri-stated.
  • DLL delay locked loop
  • memory controller 18 includes a scheduler 21 coupled to receive read commands from north bridge 12.
  • Scheduler 21 is configured to schedule the various read commands for transmission to memory 6.
  • scheduler 21 may be configured to perform arbitration of conflicting read commands.
  • Read commands may be forwarded to transmitter 23 for transmission to memory 6.
  • scheduler 21 may provide a receive enable signal ('Rx_Enable') to receiver 25 to enable reception of data from memory 6 responsive to the read command.
  • receiver 25 may include some buffering and timing circuitry to hold the assertion of the enable signal to coincide with the transmission of the data strobe signal from memory 6. This may prevent erroneous data from being received by receiver 25.
  • the timing of the assertion of the enable signal within receiver 25 may be determined by a training procedure performed by training unit 30. Training unit 30 and the corresponding training procedure are discussed in further detail below.
  • FIG. 2 a block diagram of one embodiment of memory controller 18. It is noted that not all of the components of memory controller 18 are shown here, and thus other components (including those discussed above) may be included in various embodiments.
  • memory controller 18 includes a receiver 25 coupled to receive data conveyed from memory 6.
  • the data may be synchronized to a received data strobe signal ('RDQS') based on the data strobe signal conveyed from memory 6 (the received data strobe signal may essentially be the same signal as the data strobe signal provided from memory 6, although they are referred to separately here due to the presence of buffer 33).
  • the received data strobe signal may be gated via logic gate 34 (implemented as an AND gate in this embodiment) using an enable signal ('Rx_enable'). When the enable signal is asserted, the received data strobe is enabled to pass to delay locked loop (DLL) 251 of receiver 25.
  • DLL delay locked loop
  • DLL 251 may in turn provide a corresponding clock signal to flip-flop 39 (or a group of flip-flops) to synchronize the incoming data. Otherwise, when the enable signal is not asserted, the received data strobe is not provided to DLL 251, thereby preventing unintentional data reception in receiver 25. When the enable signal is de-asserted, sampling of a tri-stated data strobe signal is thus avoided, which may prevent the potential for erroneous operation as discussed above.
  • controlling when the enable signal is asserted and de-asserted may ensure that the data strobe signal is sampled at the proper time to ensure correct operation, i.e., when the data strobe signal is actively toggling between a high state and a low state, such as in the pattern shown in Fig. 3 .
  • the enable signal is based on a received enable signal ('Rx_enable_p) from the same domain as the clock signal provided to DLL 35 ('pclk').
  • the received enable signal is provided to a first in, first out memory (FIFO) 29.
  • Read and write pointers of FIFO 29 are synchronized to the pclk signal, which may be generated by a phase locked loop (PLL) internal to memory controller 18 and is used to synchronize operations therein.
  • PLL phase locked loop
  • the output of FIFO 29 is coupled to a storage circuit, (flip-flop 32 in this embodiment), which is coupled to receive a clock signal from DLL 35.
  • DLL 35 in the embodiment shown is coupled to receive the pclk signal as an input clock, and is configured to provide a delayed version of the pclk signal to flip-flop 32. Accordingly, the Rx_enable signal provided to logic gate 34 may be synchronized to a delayed version of the pclk signal as output by DLL 35.
  • the enable signal may be asserted at a particular point in time. If the enable signal is asserted too early, thereby allowing the received data strobe signal to pass to DLL 251, receiver 25 may erroneously receive data. If the enable signal is asserted too late, data returned from memory 6 may not be received by receiver 25. Thus, training may be conducted to determine the optimal time for assertion of the enable signal.
  • memory controller 18 includes a training unit 30, which comprises a flip-flop 31, a phase detector 37, and training control logic 38.
  • the RDQS signal is received on a data input of flip-flop 31.
  • the clock input of flip-flop 31 is coupled to receive the enable signal output from flip-flop 32.
  • the output of flip-flop 31 is provided to phase detector 37. Based on the output signal received from flip-flop 31, phase detector 37 may determine the phase of the enable signal, Rx_enable, relative to the received data strobe signal, RDQS.
  • phase detector 37 may determine the phase of the enable signal, Rx_enable, relative to the received data strobe signal, RDQS.
  • FIFO 29 may provide a logic high to the D input of flip-flop 32 such that the Rx_enable signal is asserted responsive to the preamble. Accordingly, it is the read producing the preamble that may cause the sampling of the RDQS signal by flip-flop 31.
  • Training of the enable signal may be conducted under the control of training control logic 38.
  • a training signal ('Train') provided to training control logic 38 may be asserted.
  • Training control logic 38 may direct phase detector 37 in performing the training algorithm.
  • Information provided by phase detector 37 may be used by training control logic 38 in determining the various steps to be performed in the training algorithm.
  • phase detector 37 in the embodiment shown includes one or more signals that cause a value stored in control register 36 to increment or decrement.
  • the output of control register 38 may be an indication provided to DLL 35 that is used to set the delay of the pclk signal in order to generate the clock signal provided to flip-flop 32.
  • phase detector 37 may be used to effectively control the phase relationship between the enable and received data strobe signals. More particularly, phase detector 37 in the embodiment shown may increase the delay provided by DLL 32 by incrementing the value stored in control register 36. Reduction of the delay provided by DLL may be performed by phase detector 37 decrementing the value stored in control register 36. In general, changing the delay provided by DLL 32 may change the phase relationship between the received data strobe signal and the enable signal.
  • phase detector 37 may cause the delay of DLL 32 to change based on the output signal provided by flip-flop 31 during some portions of the algorithm, and based on direct control from training control logic 38 during other portions of the algorithm.
  • Fig. 3 is a timing diagram illustrating one embodiment of a training algorithm that may be performed by training unit 30.
  • Training may be initiated by asserting the train signal to training control logic 38.
  • Step 0 of the algorithm continuous reads may be initiated in performing the training procedure, with the reads being punctuated by a preamble.
  • the reads are indicated by the cycling of the received data strobe signal between logic 1 and logic 0.
  • the preamble in the illustrated example is indicated by a number of consecutive logic 0's (three in this case) between logic 1's.
  • data read operations may occur in bursts that receive a limited number of data bits, after which the data strobe signal may be tri-stated (i.e.
  • each read operation may be preceded by a time when the data strobe is driven low. This time is known as a preamble. If read operations occur back to back, the incoming data strobe will show a waveform that looks like a clock and no preamble is generated. More particularly, the bursts may be punctuated by preambles as shown, which may be short enough in duration to prevent the data strobe signal from becoming tri-stated. Otherwise, if the amount of time between reads is greater than the duration of the preamble, the data strobe signal may be tri-stated by the memory.
  • Step 1 of the algorithm is to locate any rising edge of the received data strobe signal (it is noted that embodiments are possible and contemplated wherein falling edges are located instead). This may be accomplished by cycling the enable signal, measuring the phase difference between the enable signal and the received data strobe signal (which is also cycling), and adjusting the phase difference until it is zero. Once a rising edge has been found, training control logic 38 directs phase detector 37 to subtract one half unit interval of the data strobe signal from the delay of DLL 36. As used herein, the unit interval may be one half the period of the received data strobe signal. Thus, if the data strobe signal has a duty cycle of 50%, the unit interval may be the equivalent of the duty cycle.
  • training control logic 38 may direct phase detector 37 to begin adjusting the phase of the enable signal by one unit interval increments until the end of the preamble is found (Step 3).
  • the phase adjustment is performed by incrementing. However, decrementing instead of incrementing may also be used to accomplish the same objective.
  • the phase relationship may be reported to training control logic 38, which may retain and monitor a history of the measurements. Based on the history, training control logic 38 may determine when the enable signal is aligned with a first falling edge of a first post-preamble cycle of the received data strobe signal.
  • phase detector 37 may instruct phase detector 37 to adjust the phase detector to subtract delay until the phase of the enable signal occurs within the preamble (Step 4).
  • the enable signal may be aligned to an approximate midpoint of the preamble.
  • phase detector 37 may record an indication of the phase of the enable signal relative to the received data strobe signal in control register 36. At this point the training is complete. For future operations in a mission (i.e. normal) mode, assertion of the enable signal may occur during a preamble prior to a first rising edge of the data strobe signal during one or more consecutive reads of data from memory 6.
  • Fig. 4 a flow diagram illustrating one embodiment of a method for training the delay of an enable signal relative to a data strobe signal. While method 400 may be performed using the hardware embodiments described above in reference to Figs. 1 and 2 , it is noted that other hardware embodiments capable of performing this method are also possible and contemplated.
  • Method 400 begins with the initiation of training by performing multiple series of consecutive memory reads, with the reads being punctuated by a preamble (block 405).
  • the reads may be synchronized to a data strobe signal, which include a preamble (e.g., multiple consecutive logic 0's between alternating cycles of 1's and 0's).
  • Reads may be performed in a series, followed by a preamble, then another series, and so on.
  • an edge (a rising edge in this particular case) of the data strobe signal may be located by adjusting the phase of a rising edge of an enable signal until there is zero phase difference with the rising edge of the data strobe (block 410).
  • the rising edge to which the enable signal is aligned to at this point may be any rising edge of the data strobe signal.
  • a half of one unit interval may be subtracted from the phase of the enable signal and then the phase may be subsequently adjusted in one unit interval increments (block 415). Adjusting may include incrementing or decrementing. If the end of preamble has not been found (block 420, no), then adjustments continue at block 415. Once the end of the preamble has been found (block 420, yes), a final phase adjustment may be made to place the assertion of the enable signal at a point that is within the preamble (block 425). In one embodiment, the final phase adjustment may place the assertion of the enable signal at or near a midpoint of the preamble. After the final phase adjustment is complete, an indication of the corresponding delay value is stored in a control register (block 430). This value may be used to set the delay of a delay locked loop during normal operations.
  • a computer accessible storage medium 500 may include any non-transitory storage media accessible by a computer during use to provide instructions and/or data to the computer.
  • a computer accessible storage medium 500 may include storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray.
  • Storage media may further include volatile or non-volatile memory media such as RAM (e.g.
  • SDRAM synchronous dynamic RAM
  • DDR double data rate SDRAM
  • LPDDR2, etc. low-power DDR SDRAM
  • RDRAM Rambus DRAM
  • SRAM static RAM
  • ROM Flash memory
  • Flash memory non-volatile memory (e.g. Flash memory) accessible via a peripheral interface such as the Universal Serial Bus (USB) interface
  • Storage media may include microelectromechanical systems (MEMS), as well as storage media accessible via a communication medium such as a network and/or a wireless link.
  • MEMS microelectromechanical systems
  • the data 505 representative of the system 10 and/or portions thereof carried on the computer accessible storage medium 500 may be a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate the hardware comprising the system 10.
  • the database 505 may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL.
  • HDL high level design language
  • the description may be read by a synthesis tool which may synthesize the description to produce a netlist comprising a list of gates from a synthesis library.
  • the netlist comprises a set of gates which also represent the functionality of the hardware comprising the system 10.
  • the netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks.
  • the masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system 10.
  • the database 505 on the computer accessible storage medium 500 may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.
  • GDS Graphic Data System
  • the computer accessible storage medium 500 carries a representation of the system 10
  • other embodiments may carry a representation of any portion of the system 10, as desired, including IC 2, any set of agents (e.g., processing cores 11, I/O interface 13, north bridge 12, etc.) or portions of agents.
  • agents e.g., processing cores 11, I/O interface 13, north bridge 12, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Memory System (AREA)
  • Dram (AREA)
EP13728588.8A 2012-05-22 2013-05-22 Method and apparatus for memory access delay training Active EP2852898B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/477,642 US8760946B2 (en) 2012-05-22 2012-05-22 Method and apparatus for memory access delay training
PCT/US2013/042281 WO2013177315A1 (en) 2012-05-22 2013-05-22 Method and apparatus for memory access delay training

Publications (2)

Publication Number Publication Date
EP2852898A1 EP2852898A1 (en) 2015-04-01
EP2852898B1 true EP2852898B1 (en) 2017-08-02

Family

ID=48614140

Family Applications (1)

Application Number Title Priority Date Filing Date
EP13728588.8A Active EP2852898B1 (en) 2012-05-22 2013-05-22 Method and apparatus for memory access delay training

Country Status (7)

Country Link
US (1) US8760946B2 (zh)
EP (1) EP2852898B1 (zh)
JP (1) JP5819027B2 (zh)
KR (1) KR101549648B1 (zh)
CN (1) CN104335197B (zh)
IN (1) IN2014DN10277A (zh)
WO (1) WO2013177315A1 (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140181452A1 (en) * 2012-12-26 2014-06-26 Nvidia Corporation Hardware command training for memory using read commands
US9824772B2 (en) * 2012-12-26 2017-11-21 Nvidia Corporation Hardware chip select training for memory using read commands
US9607714B2 (en) 2012-12-26 2017-03-28 Nvidia Corporation Hardware command training for memory using write leveling mechanism
US9378169B2 (en) 2012-12-31 2016-06-28 Nvidia Corporation Method and system for changing bus direction in memory systems
US9190129B2 (en) * 2013-05-31 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Continuous tuning of preamble release timing in a double data-rate memory device interface
US9478268B2 (en) * 2014-06-12 2016-10-25 Qualcomm Incorporated Distributed clock synchronization
KR20160147517A (ko) 2015-06-15 2016-12-23 에스케이하이닉스 주식회사 반도체시스템
KR102472123B1 (ko) 2016-03-16 2022-11-30 에스케이하이닉스 주식회사 반도체 시스템 및 그의 동작 방법
US10331195B2 (en) * 2016-06-06 2019-06-25 Qualcomm Incorporated Power and performance aware memory-controller voting mechanism
US10103837B2 (en) 2016-06-23 2018-10-16 Advanced Micro Devices, Inc. Asynchronous feedback training
US10749756B2 (en) 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane
KR102536657B1 (ko) * 2016-07-12 2023-05-30 에스케이하이닉스 주식회사 반도체 장치 및 반도체 시스템
US10311236B2 (en) 2016-11-22 2019-06-04 Advanced Micro Devices, Inc. Secure system memory training
KR102649888B1 (ko) 2016-11-29 2024-03-22 에스케이하이닉스 주식회사 트레이닝 장치 및 이를 포함하는 반도체 시스템
KR102671708B1 (ko) * 2016-12-16 2024-06-04 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10545866B1 (en) * 2017-06-30 2020-01-28 Cadence Design Systems, Inc. Method and system for efficient re-determination of a data valid window
JP6890055B2 (ja) * 2017-06-30 2021-06-18 ルネサスエレクトロニクス株式会社 半導体装置
KR102273191B1 (ko) 2017-09-08 2021-07-06 삼성전자주식회사 스토리지 장치 및 그것의 데이터 트레이닝 방법
KR102447499B1 (ko) * 2017-10-19 2022-09-26 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
CN108922570B (zh) * 2018-07-13 2020-11-13 豪威科技(上海)有限公司 读dqs信号的相位偏移检测方法、训练方法、电路及系统
JP2020046918A (ja) * 2018-09-19 2020-03-26 キオクシア株式会社 記憶装置及び制御方法
KR102691395B1 (ko) * 2018-12-20 2024-08-05 에스케이하이닉스 주식회사 메모리 시스템, 메모리 시스템의 동작 방법 및 메모리 콘트롤러
US10622982B1 (en) * 2019-01-10 2020-04-14 Western Digital Technologies, Inc. Measurement, calibration and tuning of memory bus duty cycle
CN113450852B (zh) 2020-03-25 2022-04-12 长鑫存储技术有限公司 半导体存储器的训练方法及相关设备
KR20210136203A (ko) 2020-05-06 2021-11-17 삼성전자주식회사 저장 장치 및 그것의 리트레이닝 방법
JP2022146543A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 半導体記憶装置、メモリシステム、および方法
JP7384543B2 (ja) * 2021-04-19 2023-11-21 ▲騰▼▲訊▼科技（深▲セン▼）有限公司 クロック同期システム、信号同期制御方法、記憶媒体及びコンピュータプログラム
US11967960B2 (en) * 2021-07-30 2024-04-23 Advanced Micro Devices, Inc. Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
US12068021B2 (en) * 2021-12-28 2024-08-20 Micron Technology, Inc. Low power clock injection during idle mode operations
CN116501268B (zh) * 2023-06-28 2024-02-27 牛芯半导体(深圳)有限公司 应用于ddr phy的数据读取方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100543910B1 (ko) * 2003-05-30 2006-01-23 주식회사 하이닉스반도체 디지털 지연고정루프 및 그의 제어 방법
US20050050375A1 (en) 2003-08-29 2005-03-03 Mark Novak Memory interface system and method
KR100605588B1 (ko) * 2004-03-05 2006-07-28 주식회사 하이닉스반도체 반도체 기억 소자에서의 지연 고정 루프 및 그의 클럭록킹 방법
US7543172B2 (en) 2004-12-21 2009-06-02 Rambus Inc. Strobe masking in a signaling system having multiple clock domains
US7457175B1 (en) 2006-10-23 2008-11-25 3Par, Inc. Dual data rate memory strobe checker
WO2008079910A2 (en) 2006-12-20 2008-07-03 Rambus Inc. Strobe acquisition and tracking
US7886174B2 (en) 2007-06-27 2011-02-08 Intel Corporation Memory link training
US7924637B2 (en) 2008-03-31 2011-04-12 Advanced Micro Devices, Inc. Method for training dynamic random access memory (DRAM) controller timing delays
KR101040242B1 (ko) * 2008-10-13 2011-06-09 주식회사 하이닉스반도체 데이터 스트로브 신호 생성장치 및 이를 이용하는 반도체 메모리 장치
US8385144B2 (en) 2011-02-25 2013-02-26 Lsi Corporation Utilizing two algorithms to determine a delay value for training DDR3 memory
JP5733126B2 (ja) * 2011-09-15 2015-06-10 富士通セミコンダクター株式会社 メモリインタフェース回路及びタイミング調整方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
JP5819027B2 (ja) 2015-11-18
KR20140147898A (ko) 2014-12-30
JP2015520902A (ja) 2015-07-23
CN104335197A (zh) 2015-02-04
EP2852898A1 (en) 2015-04-01
US8760946B2 (en) 2014-06-24
CN104335197B (zh) 2017-04-19
KR101549648B1 (ko) 2015-09-03
IN2014DN10277A (zh) 2015-08-07
US20130315014A1 (en) 2013-11-28
WO2013177315A1 (en) 2013-11-28

Similar Documents

Publication Publication Date Title
EP2852898B1 (en) Method and apparatus for memory access delay training
US8880831B2 (en) Method and apparatus to reduce memory read latency
EP3105761B1 (en) Memory physical layer interface logic for generating dynamic random access memory (dram) commands with programmable delays
US20120284576A1 (en) Hardware stimulus engine for memory receive and transmit signals
US9430027B2 (en) Power-management for integrated circuits
US11994930B2 (en) Optimizing power in a memory device
US20130064025A1 (en) Dynamic data strobe detection
US20060200642A1 (en) System and method for an asynchronous data buffer having buffer write and read pointers
US20110040902A1 (en) Compensation engine for training double data rate delays
US8422319B2 (en) System and method for gate training in a memory system
US10083736B1 (en) Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage
EP2808801B1 (en) Multiple data rate memory with read timing information
US8520455B2 (en) Method and apparatus for training a DLL in a memory subsystem
JP2009163758A (ja) クロックの異なるバス間におけるデータ転送
US10629255B2 (en) Processing system and method for data strobe signal
US9183125B2 (en) DDR receiver enable cycle training
US20180061465A1 (en) System and Method for Calibrating Memory Using Credit-Based Segmentation Control
US20230112432A1 (en) Dynamic setup and hold times adjustment for memories
US9891853B1 (en) Memory calibration abort
WO2023064729A1 (en) Dynamic setup and hold times adjustment for memories
CN118103908A (zh) 存储器的动态设置时间和保持时间调节

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20141125

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20151223

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20170221

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 915201

Country of ref document: AT

Kind code of ref document: T

Effective date: 20170815

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602013024371

Country of ref document: DE

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20170802

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 915201

Country of ref document: AT

Kind code of ref document: T

Effective date: 20170802

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20171102

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20171102

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20171202

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20171103

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

RAP2 Party data changed (patent owner data changed or rights of a patent transferred)

Owner name: ADVANCED MICRO DEVICES, INC.

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

RAP2 Party data changed (patent owner data changed or rights of a patent transferred)

Owner name: ADVANCED MICRO DEVICES, INC.

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602013024371

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20180503

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20180531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180531

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180522

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180531

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180522

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180522

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20130522

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

Ref country code: MK

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170802

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170802

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230530

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240523

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240520

Year of fee payment: 12