EP2813820A1 - Appareil de mesure, procédé de mesure et appareil de traitement - Google Patents

Appareil de mesure, procédé de mesure et appareil de traitement Download PDF

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Publication number
EP2813820A1
EP2813820A1 EP14171884.1A EP14171884A EP2813820A1 EP 2813820 A1 EP2813820 A1 EP 2813820A1 EP 14171884 A EP14171884 A EP 14171884A EP 2813820 A1 EP2813820 A1 EP 2813820A1
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Prior art keywords
signal
data
clock
measurement data
cycle
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EP14171884.1A
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German (de)
English (en)
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EP2813820B1 (fr
Inventor
Takafumi Ito
Yoshiyuki Okada
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
    • G01D5/32—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light
    • G01D5/34—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells
    • G01D5/347—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells using displacement encoding scales
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
    • G01D5/24471—Error correction

Definitions

  • the present invention relates to a measuring apparatus, a measuring method, and a processing apparatus.
  • an incremental encoder and an absolute encoder each having a different output format are present as measuring apparatuses for measuring positions and angles.
  • Examples of a linear encoder for position measurement include an incremental linear encoder for measuring a relative position (change in position or displacement) and an absolute linear encoder for measuring an absolute position.
  • examples of a rotary encoder for angle measurement include an incremental rotary encoder for measuring a relative angle (change in angle or displacement) and an absolute rotary encoder for measuring an absolute angle.
  • an optical encoder and a magnetic encoder each having a different operation principle are present.
  • a scale is irradiated with light emitted from a light source, and light transmitted through the scale or light reflected therefrom is received by a photoelectric conversion element.
  • the light source and the photoelectric conversion element are mounted on an object to be moved or rotated and the scale is mounted on a fixing side serving as a reference or vice versa.
  • evenly spaced transmission films or reflection films are machined on a scale and received light intensity is a sine wave having a constant cycle.
  • a signal processing device counts the wave number of the detected sine wave signals. The phase in a cycle is finely divided so as to improve measurement resolution and accuracy.
  • an absolute encoder a transmission film or a reflection film having the pseudorandom code is machined on a scale so as to detect received light intensity associated with the pseudorandom code.
  • the signal processing device calculates an absolute position or an absolute angle for the pseudorandom code using a reference table.
  • the phase of the pseudorandom code is finely divided so as to improve measurement resolution and accuracy.
  • measurement data for positions or angles obtained by these encoders are transmitted to a host system depending on a data request signal from an external host system.
  • the host system is an industrial apparatus using an encoder and executes positioning control of the object based on measurement data obtained from the encoder.
  • a measurement error caused by a measurement delay time i.e., a measurement error caused by the product of a moving speed and a delay time may occur when the object is moving.
  • H8-261794 discloses an encoder that estimates the amount of movement of an object in a delay time required for outputting position data using previously-sampled position data so as to correct currently-sampled position data.
  • Japanese Patent Laid-Open No. 2007-71865 discloses an encoder output interpolation method that measures a time from A/D conversion sampling to data request in response to a data request made from the outside and then interpolates position data before and after the data request so as to output position data.
  • the encoder disclosed in Japanese Patent Laid-Open No. 2007-71865 requires position data before and after the data request.
  • a time interval for outputting position data is coarse, interpolation accuracy of position data may deteriorate, resulting in a difficulty in outputting an accurate position or angle.
  • the cycle of a data request signal output from the host system is shortened, the amount of output data from the encoder increases, resulting in an increase in a computation load on the host system. Consequently, the host system is complicated and expensive.
  • the present invention provides, for example, a measuring apparatus advantageous in terms of precision with which displacement of an object is measured.
  • the present invention in its first aspect provides a measuring apparatus as specified in claims 1 to 7.
  • the present invention in its second aspect provides a processing apparatus as specified in claim 8.
  • the present invention in its third aspect provides a measuring method as specified in claim 9.
  • the measuring apparatus of the present embodiment is so-called an encoder that detects a signal which varies with displacement of an object (object to be measured) so as to measure the displacement thereof.
  • an encoder that detects a signal which varies with displacement of an object (object to be measured) so as to measure the displacement thereof.
  • a description will be given by taking an example of an optical absolute encoder for measuring the change in position or the displacement of an object.
  • the measuring apparatus of the present invention is not limited to an encoder for measuring the change in position or the displacement of an object but may also be applicable to an encoder or an incremental encoder for measuring the change in angle or the displacement of an object.
  • FIG. 1 is a block diagram illustrating a configuration of the signal processing system of an encoder 100 according to the present embodiment.
  • a host system 500 that transmits a signal (hereinafter referred to as "data request signal") for requesting position data (measurement data) to the encoder 100 and receives position data measured at the timing of a data request.
  • the host system 500 corresponds to a processing apparatus (hereinafter, also used as the meaning of controller) that uses position data obtained from the encoder 100.
  • processing apparatus specifically refers to a measuring apparatus for measuring the characteristics of an object, an inspecting apparatus for (non-destructive) inspecting an object, a machining apparatus for machining an object, and the like.
  • the host system 500 may be a data collecting and analyzing unit, which is provided in a measuring apparatus or an inspecting apparatus, for simply collecting/analyzing position data or may also be a controller, which is provided in a machining apparatus, for executing positioning control based on the obtained position data.
  • the control band of positioning control is about several tens to hundreds of Hz.
  • the cycle of a data request is from 1 ms to 100 ⁇ s, that is, has a frequency of about 1 kHz to 10 kHz.
  • the host system 500 acquires position data in 100 ⁇ s, and then executes control computation such as PID control based on the position data.
  • control computation such as PID control
  • the host system must perform control computation at a time interval shorter than 100 ⁇ s, resulting in an increase in computation load. Consequently, the host system is required to exhibit high performance, resulting in an increase in cost and complication of the host system itself.
  • the cycle of a data request is reasonably from 1 ms to 100 ⁇ s.
  • the host system 500 operates an actuator based on the result calculated by control computation so as to cause it to perform positioning.
  • the host system 500 When the host system 500 is a data collecting and analyzing unit, accurate position data at a time point at which the encoder 100 outputs a data request signal is necessary information (to be acquired). In contrast, when the host system 500 is a controller for executing positioning control, positioning control is executed on a clock cycle next or subsequent to a clock cycle in which the encoder 100 outputs a data request signal, accurate position data at a time point of performing positioning control is necessary information.
  • a description will be firstly given on assumption that the host system 500 collects (acquires) position data, and then, a description will be given of a case where the host system 500 executes positioning control based on the acquired position data.
  • FIG. 2 is a diagram illustrating a configuration of the optical system of the encoder 100 and the intensity (received light intensity) of light to be detected in association with each other.
  • the encoder 100 includes, for example, a detector 10, a light source 12, a collimator lens 14, and a scale 16.
  • the detector 10 may be a photoelectric conversion element such as a CMOS image sensor, a CCD sensor, or the like but is not limited thereto.
  • the detector 10 may be changed in various ways depending on a measurement method.
  • the light source 12 is, for example, an LED that collimates light into collimated light via the collimator lens 14 and then illuminates the scale 16 with the collimated light.
  • the pseudorandom code (e.g., M-series cyclic code) is machined on the scale 16.
  • the scale 16 is a plate member extending in one direction in the case of a linear encoder for measuring a position such as the encoder 100 but may also by a discshaped member in the case of a rotary encoder for measuring an angle.
  • Light emitted from the scale 16 by transmission through or reflection from the scale 16 has a received light intensity by the pseudorandom code, and the detector 10 receives the light.
  • the received light intensity is a signal(s) having strengths (amplitudes) reflecting the pseudorandom code formed on the scale 16.
  • the light source 12 and the detector 10 are mounted on an object to be moved (or to be rotated) and the scale 16 is mounted on a fixing side serving as a reference or vice versa.
  • a current-voltage converter (not shown) is provided downstream of the detector 10 and converts the received light intensity into a voltage signal. Furthermore, a voltage amplifier is provided downstream of the detector 10 as required and amplifies a signal to a predetermined voltage level.
  • An A/D converter 20 A/D-converts a signal from the detector 10 and converts an analog signal into a digital signal.
  • a signal processing device 200 is a high speed digital signal processor, such as an FPGA, an ASIC, a DSP, or the like for processing a digital signal received from the A/D converter 20, where FPGA is an abbreviation for Field-Programmable Gate Array, ASIC is an abbreviation for Application Specific Integrated Circuit, and DSP is an abbreviation for Digital Signal Processor.
  • the signal processing device 200 includes a position operation device 30, a position correction device 40, a position data output device 50, a time difference measuring device 60, and a synchronous high-speed clock generator 70.
  • the position operation device (operation device) 30 Upon receiving a signal from the A/D converter 20, the position operation device (operation device) 30 calculates position data. For example, in the absolute encoder, the position operation device 30 reproduces the pseudorandom code represented by 0 and 1 using a signal(s) having strengths (amplitudes) reflecting the pseudorandom code as shown in FIG. 2 . Then, the position operation device 30 determines the absolute position for the detected pseudorandom code with reference to the reference table of the absolute positions for pseudorandom codes (not shown) stored therein. Furthermore, the position operation device 30 finely divides the phase of the pseudorandom code so as to improve measurement resolution.
  • the synchronous high-speed clock generator (clock generator) 70 generates a meas signal 111, a meas_start signal 110, an ad_start signal 116, and a data_out_start signal 120.
  • the synchronous high-speed clock generator 70 also generates a clock signal (clk signal 112: see FIG. 3 ) for use in computation by the position operation device 30 and the position correction device 40.
  • FIG. 3 is a block diagram illustrating a configuration of the synchronous high-speed clock generator 70.
  • the synchronous high-speed clock generator 70 includes three counters (first counter 71, second counter 72, and third counter 73), two comparators (first comparator 74 and second comparator 75), an AND logic circuit (AND circuit) 76, a counter value holding circuit 77, and a phase synchronizing device (PLL) 78.
  • a data_req signal 210 is input as a data request signal from the host system 500 to the synchronous high-speed clock generator 70.
  • the data_req signal 210 is an intermittent signal having one cycle of combining a term (first term) of a clock signal having a predetermined frequency and a term (second term) for which the voltage becomes constant (constant value) for a predetermined time.
  • the data_req signal 210 may be a signal based on the BiSS-C open protocol.
  • the first term is referred to as a "clock (CLK) term”
  • the second term is referred to as "timeout (Timeout) term”.
  • the data_req signal 210 is divided into signals to be input to the PLL 78, the AND logic circuit 76, the first counter 71, and the second counter 72.
  • the synchronous high-speed clock generator 70 generates the meas signal 111 using a phase synchronizing device based on the data_req signal 210.
  • the meas signal 111 is a high speed clock signal (first clock signal) for position measurement in synchronization with the data_req signal 210.
  • the phase synchronizing device is, for example, a PLL (Phase Locked Loop: hereinafter referred to as "PLL 78").
  • PLL 78 Phase Locked Loop
  • the data_req signal 210 is an intermittent signal including a timeout term.
  • the first counter 71 counts the high term of the data_req signal 210 using a clock signal 115 from an oscillator 80, and is reset when the data_req signal 210 is low.
  • FIG. 4 is a diagram illustrating the operation of the first counter 71, where time is plotted on the horizontal axis and the number of counts is plotted on the vertical axis.
  • the cycle of the data_req signal 210 is 100 ⁇ s.
  • the clock term of the data_req signal 210 is 88.05 ⁇ s and the frequency of the clock signal in the clock term is 10 MHz.
  • the timeout term of the data_req signal 210 is 11.95 ⁇ s.
  • the frequency of the clock signal 115 output from the oscillator 80 is 200 MHz.
  • the first counter 71 does not perform counting in a low term (50 ns) in the clock term of the data_req signal 210.
  • the data_req signal 210 becomes low at a time point at which the first counter 71 has counted up to 10 counts in a high term (50 ns), and then, the first counter 71 is reset.
  • the count operation of the first counter 71 has a sawtooth-shaped profile as shown in FIG. 4 .
  • the clock frequency of the data_req signal 210 in the clock term is 0.1 MHz
  • the count operation of the first counter 71 has a sawtooth-shaped profile at every 1000 counts.
  • the first counter 71 Since the data_req signal 210 is high in the timeout term, the first counter 71 continues counting. The time for one cycle of the data_req signal 210 elapses at a time point at which the first counter 71 has counted up to 2390 counts, and then the data_req signal 210 becomes low, so that the first counter 71 is reset.
  • the first comparator 74 compares the count value of the first counter 71 with a threshold value set in the first comparator 74, and outputs high when the count value is greater than the threshold value.
  • the threshold value set in the first comparator 74 is set to a value such that the count value in the clock term never exceeds the threshold value but only the count value in the timeout term exceeds the threshold value. In the example shown in FIG. 4 , the threshold value set in the first comparator 74 is 2000 counts.
  • the AND logic circuit 76 executes logical "AND" computation between the output of the first comparator 74 and the low of the data_req signal 210. As described above, the first comparator 74 outputs high during the timeout term of the data_req signal 210. After the first comparator 74 outputs high, the data_req signal 210 becomes low at a time point at which the timeout term ends, i.e., at a time point at which the time for one cycle of the data_req signal 210 has elapsed. The AND logic circuit 76 is synchronized with a time point at which the time for one cycle of the data_req signal 210 has elapsed so as to output high. The output of the AND logic circuit 76 is used as a reset signal to the second counter 72, a start signal to the counter value holding circuit 77, and a start signal to the third counter 73, all of which will be described below.
  • the second counter 72 counts the low term of the data_req signal 210 using the clock signal 115 from the oscillator 80.
  • the second counter 72 is reset based on the output of the AND logic circuit 76.
  • FIG. 5 is a diagram illustrating the operation of the second counter 72, where time is plotted on the horizontal axis and the number of counts is plotted on the vertical axis. Note that the conditions for the data_req signal 210 and the clock signal 115 from the oscillator 80 are the same as those as set forth in the description of the operation of the first counter 71.
  • the second counter 72 counts up to 10 counts in a low term (50 ns) in the clock term of the data_req signal 210, and then holds the count value without further counting in the high term (50 ns).
  • the second counter 72 further counts up to 20 counts which is incremented by 10 counts in the next low term (50 ns).
  • the count operation of the second counter 72 has a stepwise profile as shown in FIG. 5 .
  • the clock frequency of the data_req signal 210 in the clock term is 0.1 MHz
  • the count operation of the second counter 72 has a stepwise profile at every 1000 counts. Since the data_req signal 210 is high in the timeout term, the second counter 72 continues to hold the count value without further counting.
  • the count value is set as the final count value. Under the above conditions, the final count value is 8810 counts. Then, the second counter 72 is reset at a time point at which the AND logic circuit 76 outputs high, i.e., at a time point at which the time for one cycle of the data_req signal 210 has elapsed.
  • the counter value holding circuit 77 holds the final count value, for example, a count value at a time point at which the output of the AND logic circuit 76 is set as a start signal.
  • the output of the second counter 72 may be input in a delayed manner such that the counter value holding circuit 77 does not hold a count value obtained after the second counter 72 is reset.
  • the counter value holding circuit 77 may also be adapted to hold a count value using the output of the first comparator 74 as a start signal.
  • obtained final count value is a value indicating the length of the clock term of the data_req signal 210.
  • the final count value is used as a threshold value for the second comparator 75 to be described below.
  • the third counter 73 starts counting from a time point at which the time for one cycle of the data_req signal 210 has elapsed, i.e., a time point at which a data request has been made after the output of the AND logic circuit 76 was input as a start signal for the counting.
  • the clock signal 115 from the oscillator 80 is input as a clock serving as a reference for counting to the third counter 73 as in the first counter 71 and the second counter 72.
  • the second comparator 75 compares the count value of the third counter 73 with a threshold value set in the second comparator 75.
  • the threshold value set in the second comparator 75 is set to the final count value output from the counter value holding circuit 77.
  • the second comparator 75 outputs low in a term during which the count value of the third counter 73 does not exceed the threshold value set in the second comparator 75, i.e., in the clock term of the data_req signal 210.
  • the second comparator 75 outputs high in a term during which the count value of the third counter 73 exceeds the threshold value set in the second comparator 75, i.e., in the timeout term of the data_req signal 210.
  • the third counter 73 is reset at a time point at which the second comparator 75 outputs high. Then, the third counter 73 stops counting until a start signal is input again, i.e., until the time for one cycle of the data_req signal 210 elapses. It should be noted that the second comparator 75 continuously outputs high until the second comparator 75 is reset by receiving the output of the AND logic circuit 76, i.e., until the time for one cycle of the data_req signal 210 elapses. The output of the second comparator 75 is used by the PLL 78 as a control signal for switching a sample operation and a hold operation. Hereinafter, the output of the second comparator 75 is referred to as a sample_hold signal 117.
  • the PLL 78 performs a sample operation in a term during which the sample_hold signal 117 is low, i.e., in the clock term of the data_req signal 210. On the other hand, the PLL 78 performs a hold operation in a term during which the sample_hold signal 117 is high, i.e., in the timeout term of the data_req signal 210.
  • FIG. 6 is a block diagram illustrating a configuration of the PLL 78.
  • the PLL 78 includes a phase comparator 781, a sample and hold switch 782, a loop filter 783, a voltage control oscillator 784, a first frequency divider 785, a second frequency divider 786, a third frequency divider 787, a first delay circuit 788, and a second delay circuit 789.
  • the phase comparator 781 constitutes a feedback loop so as to compare an input signal (the data_req signal 210) with an output signal (a clk signal 112). Then, the phase comparator 781 performs phase comparison between an input signal and an output signal and then outputs the phase difference as a phase difference signal.
  • the loop filter 783 is an integrating circuit for removing short cycle fluctuations.
  • the voltage control oscillator (VCO) 784 adjusts an oscillation frequency based on a phase difference signal input from the loop filter 783 so as to output the clk signal 112.
  • the clk signal 112 is a clock signal for use in computation by the position operation device 30 and the position correction device 40 as described above.
  • the sample and hold switch 782 is turned ON in the clock term of the data_req signal 210, i.e., in a term during which the sample_hold signal 117 is low, so that the feedback loop is configured for the phase comparator 781.
  • the PLL 78 performs a sample operation.
  • the output signal to be fed back is frequency-divided by the first frequency divider 785, and then is input to the phase comparator 781 so as to compare it with the clock signal of the data_req signal 210.
  • the voltage control oscillator 784 outputs a signal multiplied by the clock frequency of the data_req signal 210.
  • the voltage control oscillator 784 outputs a signal having a frequency of 200 MHz in synchronization with a clock signal.
  • the PLL 78 can output a high-frequency second clock signal (the clk signal 112) in synchronization with the clock signal of the data_req signal 210.
  • the sample and hold switch 782 is turned OFF in the timeout term of the data_req signal 210, i.e., in a term during which the sample_hold signal 117 is high, so that the feedback loop is not configured for the phase comparator 781.
  • the PLL 78 performs a hold operation.
  • the voltage control oscillator 784 since no new phase difference signal is input to the voltage control oscillator 784, the voltage control oscillator 784 continuously outputs a signal having an oscillation frequency adjusted in the clock term of the data_req signal 210.
  • the PLL 78 can output a second clock signal (the clk signal 112) in synchronization with the clock signal of the data_req signal 210 without being affected by a fixed voltage for a predetermined time in the timeout term.
  • the clk signal 112 is not limited to the one generated by the PLL 78 but may also be generated by an external clock such as the oscillator 80 or the like.
  • the clk signal 112 is asynchronous with the data_req signal 210 and there is sync deviation of 5 ns between the clk signal 112 and the data_req signal 210 for one cycle at the maximum when the frequency of the clk signal 112 is 200 MHz.
  • a measurement error caused by sync deviation is very small, so that the influence of sync deviation can be ignored.
  • the PLL 78 causes the second frequency divider 786 to frequency-divide the clk signal 112 so as to generate the meas signal 111 which is a high speed clock signal for position measurement in synchronization with the data_req signal 210.
  • the meas signal 111 is a signal having a frequency of 100 kHz in synchronization with the data_req signal 210.
  • the PLL 78 causes the first delay circuit 788 to delay the meas signal 111 by the time from the start of position measurement to the end of position measurement by the detector 10 so as to generate the ad_start signal 116 which is a start signal for A/D conversion by the A/D converter 20.
  • the PLL 78 causes the third frequency divider 787 to frequency-divide the clk signal 112 so as to generate the meas_start signal 110 which a signal in synchronization with the data_req signal 210 and having the same frequency as that of the data_req signal 210.
  • the meas_start signal 110 is a signal having a frequency of 10 kHz in synchronization with the data_req signal 210. Furthermore, the PLL 78 causes the second delay circuit 789 to delay the meas_start signal 110 by a predetermined time so as to generate the data_out_start signal 120 which is a start signal for outputting data from the position data output device 50 shown in FIG. 1 .
  • the PLL generally requires a predetermined time until the phase is locked to the input.
  • the PLL 78 is configured to return an error signal to a data request until the stable operation is obtained with phase locked loop.
  • the output of the phase comparator 781 is monitored so as to check whether or not the PLL 78 is in stable operation with phase locked loop. For example, when the output of the phase comparator 781 is substantially zero, it is found that the PLL 78 is in stable operation with phase locked loop.
  • the detector 10 performs position measurement with respect to each cycle of the meas signal 111 received from the synchronous high-speed clock generator 70. Also, the A/D converter 20 starts A/D conversion using the ad_start signal 116 received from the synchronous high-speed clock generator 70.
  • the time difference measuring device 60 measures a correction delay time (Tsp) for correcting position data based on the meas_start signal 110 and the meas signal 111 received from the synchronous high-speed clock generator 70 so as to output the correction delay time (Tsp) as a time_delay signal 114.
  • Tsp correction delay time
  • the position correction device (correction device) 40 calculates a speed-related signal from the amount of change (the displacement amount) in at least two position data per unit time (with respect to each cycle of the meas signal 111) using the time_delay signal 114. Then, the position correction device 40 corrects position data which has been calculated by the position operation device 30 using the product of the calculated signal and the correction delay time.
  • the corrected correction position data is temporarily stored in the position data output device 50, is synchronized with the data_out_start signal 120 received from the synchronous high-speed clock generator 70, and then is output as a data_out signal 220 to the host system 500.
  • FIG. 7 is a timing chart illustrating the operation timing of the respective units.
  • data_req refers to the data_req signal 210.
  • the data request cycle "Treq” time interval among the data_req 1, the data_req 2, and the data_req 3 is assumed to be 100 ⁇ s.
  • the range "CLK” represented by the two-way arrow indicates the clock term of the data_req signal 210.
  • the range "Timeout” represented by the two-way arrow indicates the timeout term of the data_req signal 210.
  • the range "Wait” represented by the two-way arrow indicates a wait time (hereinafter referred to as "Wait time”) from a time point at which a data request has been made to a time point at which measurement data is actually output. These values are determined by the communication protocol between the host system 500 and the encoder 100.
  • the term “clk” refers to the clk signal 112 having a frequency of 200 MHz.
  • the term “meas (100 kHz)” refers to the meas signal 111 having a frequency of 100 MHz.
  • meas_start refers to the meas_start signal 110 having a cycle of 100 ⁇ s which is the same as the data request cycle "Treq".
  • CMOS_Charge is a time at which position data is actually acquired by the detector 10, for example, a time at which light is received by a CMOS image sensor.
  • the CMOS_Charge is started by the meas signal 111, and the detector 10 acquires position data with respect to each cycle of the meas signal 111.
  • the term “ad” refers to a time from the start of A/D conversion of the analog data output from the detector 10 by the A/D converter 20 upon receiving the ad_start signal 116 to the end of A/D conversion.
  • calc refers to a time during which position data is computed by the position operation device 30 based on the digital data output from the A/D converter 20.
  • Position_out refers to a time at which position data is output from the position operation device 30.
  • a description will be given of a case where a processing time from the start of position measurement to the end of computation of correction position data is shorter than the Wait time.
  • the host system 500 may be desired for the host system 500 to obtain position data at the time point of the data_req 3 in FIG. 7 based on the assumption that the processing time from the start of position measurement to the end of computation of correction position data is 10 ⁇ s and the Wait time is 30 ⁇ s.
  • the processing up to position data computation ends during the Wait time, and thus, position data P3_1 acquired at the time point of the data_req 3 is output as it is.
  • the encoder 100 outputs the position data measured at the time point of the data_req 3 without performing correction processing.
  • the host system 500 is a controller that executes positioning control using the acquired position data.
  • position data, which is actually used for control for a measurement request made at the time point of the data_req 3 is the one at the time point of a data_req 4 which is the next clock timing.
  • position data subject to correction upon control P4'_1, which predicts position data P4_1 at the time point of the data_req 4 for a measurement request made at the time point of the data_req 3 needs to be output.
  • the term "Velocity_calc” refers to a time for computing the moving speed of an object at the time point of acquisition of current position data based on the currently acquired position data and the previously acquired position data.
  • Formula (1) is represented as the following Formula (2).
  • the position measurement cycle is 10 ⁇ s (from the frequency 100 kHz of the meas signal 111).
  • V ⁇ 3 _ 1 m / s P ⁇ 3 _ 1 m - P ⁇ 2 _ 10 m / 10 ⁇ s
  • control use Position out refers to a time for computing and outputting position data subject to correction upon control based on the moving speed.
  • the position data subject to correction upon control P4'_1 is determined by the following Formula (4).
  • a time difference from a time point of control is 100 ⁇ s.
  • P ⁇ 4 ⁇ ⁇ _ 1 m P ⁇ 3 _ 1 m + V ⁇ 3 _ 1 m / s ⁇ 100 ⁇ s
  • FIG. 8 is a timing chart in this case corresponding to FIG. 7 .
  • the processing up to output of the position data P3_1 at the time point of the data_req 3 does not end during the Wait time in contrast to the case shown in FIG. 7 .
  • the encoder 100 cannot output the position data P3_1 as it is.
  • position data subject to correction upon measurement P3'_1, which predicts the position data P3_1 at the time point of the data_req 3 needs to be output.
  • Tsp is a time difference between a time point at which measurement of current position data is started and a time point at which a data request has been made.
  • Tsp is input as the time_delay signal 114 from the time difference measuring device 60 to the position correction device 40.
  • the time difference measuring device 60 counts the number of clocks of the meas signal 111 during the data request cycle "Treq". In this manner, the time difference measuring device 60 can recognize how many clocks of the meas signal 111 are included during the data request cycle "Treq". Given that the number of clocks is referred to as "the total number of clocks", the total number of clocks in the example shown in FIG. 8 is 10.
  • the position correction device 40 adds information indicating data measured at the nth number of clocks from a time point at which a data request has been made to position data information, where the nth number of clocks is defined as a current clock number. For example, in position data P2_10 shown in FIG. 8 , the current clock number is 10.
  • the position correction device 40 can recognize the fact that the position data information is an nth clock prior to a time point at which a data request has been made using the following Formula (6).
  • the clock is referred to as "the reference clock number for correction value computation".
  • Reference clock number for correction value computation total number of clocks + 1 - current clock number
  • the position data P2_10 is position data measured at one clock prior to a time point at which a data request has been made.
  • Tsp thus determined is substituted into Formula (5), so that position data subject to correction upon measurement can be determined.
  • the position data output device 50 outputs position data subject to correction upon measurement, which is most proximate in time to a time point at which a data request for the data_req 3 has been made among position data subject to correction upon measurement determined in Formula (9), to the host system 500.
  • Tsp is a time difference between a time point at which the detector 10 starts measurement and a time point at which a data request has been made
  • the light-receiving time of the detector 10 may also be taken into account in order to perform more detailed correction.
  • the light-receiving time of the detector 10 may be determined from the design value or may also be determined by actual measurement.
  • Position data subject to correction upon control m position data subject to correction upon measurement m + moving speed m / s ⁇ time difference from a time point of control s
  • an object has an acceleration varying as shown in FIG. 9 .
  • time is plotted on the horizontal axis and gravity acceleration is plotted on the vertical axis.
  • an object is in a variable acceleration operation in a trapezoidal profile such that acceleration linearly increases (the object accelerates) from 0G to 1G in a time from 0 to 5 ms, acceleration is a constant 1G in a time from 5 to 10 ms, and acceleration linearly decreases (the object decelerates) from 1G to 0G in a time from 10 to 15 ms.
  • FIG. 14 is a timing chart illustrating the operation timing of the respective units of the conventional encoder corresponding to FIGs. 7 and 8 .
  • the conventional encoder there is no meas signal which is a clock signal for use in for position measurement as can be seen from comparison of FIGs. 7 and 8 , so that position measurement is performed with respect to each cycle of a data request.
  • FIG. 14 shows the case where the processing time from the start of position measurement to the end of computation of correction position data is longer than the Wait time.
  • Tsp 100 ⁇ s which is the same as the data request cycle "Treq".
  • P ⁇ 3 ⁇ ⁇ _ 1 m P ⁇ 2 _ 1 m + V ⁇ 2 _ 1 m / s ⁇ 100 ⁇ s
  • FIGs. 10A and 10B are graph illustrating a positional error obtained for an object which is in acceleration operation shown in FIG. 9 .
  • FIG. 10A is a graph illustrating a positional error pertaining to correction upon measurement.
  • the conventional error amount shown by the solid line in FIG. 10A is plotted on the vertical axis at the left side with respect to time plotted on the horizontal axis.
  • the error amount is proportional to a magnitude of the acceleration of the object and is 98 nm at maximum.
  • Tsp is 10 ⁇ s and a positional error for an object which is in operation shown in FIG. 9 , which is a difference between the position data subject to correction upon measurement determined by Formula (5) and the actual position, is represented by the chain-dotted line in FIG. 10A .
  • the error amount shown by a chain-dotted line is plotted on the vertical axis at the right side with respect to time plotted on the horizontal axis.
  • the scale of the vertical axis at the right side relative to the vertical axis at the left side plotting the error amount in the conventional case is 1/10.
  • the error amount is 0.98 nm at maximum and is significantly reduced to about 1/100 as compared with the conventional case.
  • it is found that highly-accurate position data subject to correction upon measurement having a positional error of 1 nm or less is obtained.
  • the host system 500 is a controller that executes positioning control using the acquired position data.
  • position data, which is actually used for control, for a request made at the time point of the data_req 3 is, for example, the one at the time point of a data_req 4 which is the next clock timing.
  • the encoder needs to output the position data subject to correction upon control P4'_1 which predicts position data P4_1 at the time point of the data_req 4.
  • the position data subject to correction upon control P4'_1 is determined by the following Formula (14) with reference to the above Formula (11).
  • FIG. 10B is a graph illustrating a positional error pertaining to correction upon control.
  • the conventional error amount shown by the solid line in FIG. 10B is proportional to a magnitude of the acceleration of the object and is 294 nm at maximum.
  • Tsp is 10 ⁇ s and a positional error for an object which is in operation shown in FIG. 9 , which is a difference between the position data subject to correction upon measurement determined by Formula (11) and the actual position, is represented by the chain-dotted line in FIG. 10B .
  • the error amount is 64.6 nm at maximum and is reduced to about 1/4.5 as compared with the conventional case.
  • Tsp may vary depending on the processing speed of the position operation device 30 or the like. Thus, a description will be given below of how a positional error amount varies depending on a magnitude of Tsp.
  • FIG. 11A is a graph illustrating a positional error amount [nm] with respect to Tsp [ ⁇ s] for position data subject to correction upon measurement.
  • Tsp positional error amount
  • the error amount is 0.98 nm as described above which is about 1/100 as compared with the conventional case.
  • the encoder 100 can output the acquired position data as it is, so that the error amount is 0 nm.
  • FIG. 11B is a graph illustrating a positional error amount [nm] with respect to Tsp [ ⁇ s] for position data subject to correction upon control.
  • Tsp positional error amount
  • the error amount is 64.6 nm as described above which is about 1/4.5 as compared with the conventional case.
  • Tsp is 0 ⁇ m
  • an object moves for a time until the host system 500 performs control, so that the error amount is 53.9 nm which is about 1/5.5 as compared with the conventional case.
  • the encoder 100 generates and uses a high speed clock for position measurement in synchronization with the cycle of a data request signal so as to perform position or angle measurement in a cycle shorter than the cycle of the data request signal.
  • it has conventionally been difficult to output an accurate position or angle if the cycle of a data request signal is not shortened, whereas there is no need to shorten the cycle of a data request signal in the encoder 100.
  • a measuring apparatus and a measuring method which are advantageous, for example, in terms of displacement measurement accuracy of the object which displaces at high speed may be provided.
  • a processing apparatus which is advantageous in terms of high-accuracy processing such as measurement, inspection, machining of an object may be provided.
  • FIG. 12 is a block diagram illustrating a configuration of the signal processing system of an encoder 300 according to the present embodiment.
  • a feature of the encoder 300 according to the present embodiment lies in the fact that, although the encoder 100 according to the first embodiment includes the oscillator 80, the encoder 300 does not include the oscillator but receives an input of a clk_IN signal 230 from the host system 500.
  • the other aspects of the construction of the encoder 300 which are basically the same as those of the encoder 100 according to the first embodiment, are denoted by the same reference numerals in FIG. 12 , and description thereof is omitted.
  • the clk_IN signal 230 is a clock signal in synchronization with the data_req signal 210 transmitted from the host system 500.
  • the encoder 300 receives the clk_IN signal 230 from the host system 500, and the synchronous high-speed clock generator 70 generates the meas signal 111 based on the clk_IN signal 230.
  • the synchronous high-speed clock generator 70 also generates a clock signal for use in computation by the position operation device 30 and the position correction device 40. More specifically, the clk_IN signal 230 is firstly input to the PLL 78 provided in the synchronous high-speed clock generator 70.
  • the PLL 78 can constantly generate a new clock signal in synchronization with the clk_IN signal 230 in a sample operation. Thus, in the present embodiment, there is no need to provide the sample and hold switch 782 in the PLL 78. For example, when the frequency of the clk_IN signal 230 is 100 kHz and the frequency division ratio (1/N) of the first frequency divider 785 is 1/2000, the voltage control oscillator 784 outputs the clk signal 112 having a frequency of 200 MHz in synchronization with the clk_IN signal 230.
  • the synchronous high-speed clock generator 70 imposes a delay on the clk signal 112 by frequency division so as to generate the meas signal 111, the ad_start signal 116, the meas_start signal 110, and the data_out_start signal 120.
  • FIG. 13 is a timing chart illustrating the operation timing of the respective units in the present embodiment, which corresponds to FIG. 7 in the first embodiment.
  • FIG. 13 is different from FIG. 7 in that there are a "clk_IN” signal and a “clk (PLL generate) signal instead of a "clk” signal and a “meas (100 kHz)" signal.
  • the term “clk_IN” refers to the clk_IN signal 230, and the synchronous high-speed clock generator 70 generates a clk (PLL generate) based on clk_IN.
  • clk_IN may have a frequency of 100 kHz and clk (PLL generate) may have a frequency of 200 MHz.
  • the synchronous high-speed clock generator 70 frequency-divides the clk (PLL generate) so that the meas signal 111 can be generated.
  • the meas signal 111 has a frequency of 100 kHz which is the same as that of clk_IN but is not shown in FIG. 13 (clock timing is the same as that of clk_IN). Then, the detector 10 in the encoder 300 performs position measurement with respect to each cycle of the meas signal 111.
  • FIG. 13 shows the case where a processing time from the start of position measurement to the end of computation of correction position data is shorter than the Wait time.
  • a processing time from the start of position measurement to the end of computation of correction position data is longer than the Wait time, the same is applicable by replacing clk_IN and clk (PLL generate) with meas (100 kHz) and clk, respectively, in FIG. 8 in the first embodiment.
  • the encoder 300 receives a clock signal in synchronization with the cycle of a data request signal from the host system 500, and thus, the oscillator 80 is not required as compared with the first embodiment.
  • the present embodiment is advantageous in that the configuration and signal processing may be simplified while providing the same effects as those of the first embodiment.
  • the frequencies of the respective clock signals exemplified in the above embodiments are not limited to these values but may vary within the range of scope thereof. While, in the above embodiments, a description has been given on the assumption that the meas signal 111 is a continuous clock signal, the meas signal 111 may also be an intermittent signal provided that a plurality of position measurement timings is given to the detector 10 during a data request cycle. Furthermore, while the data_req signal 210 which is a data request signal has a periodicity as described above, the data_req signal 210 may not have a periodicity provided that measurement data acceptable in terms of accuracy can be acquired.

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EP14171884.1A 2013-06-12 2014-06-11 Appareil de mesure, procédé de mesure et appareil de traitement Not-in-force EP2813820B1 (fr)

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JP6779081B2 (ja) * 2016-09-28 2020-11-04 キヤノン株式会社 記録素子基板、記録ヘッド、および記録装置
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