EP2746876B1 - Herstellungstechniken zur Verbesserung der Druckgleichförmigkeit in anodisch gebundenen Dampfzellen und Mikroplättchenstruktur dazu - Google Patents

Herstellungstechniken zur Verbesserung der Druckgleichförmigkeit in anodisch gebundenen Dampfzellen und Mikroplättchenstruktur dazu Download PDF

Info

Publication number
EP2746876B1
EP2746876B1 EP13181421.2A EP13181421A EP2746876B1 EP 2746876 B1 EP2746876 B1 EP 2746876B1 EP 13181421 A EP13181421 A EP 13181421A EP 2746876 B1 EP2746876 B1 EP 2746876B1
Authority
EP
European Patent Office
Prior art keywords
wafer
diameter
sacrificial
vapor
vapor cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP13181421.2A
Other languages
English (en)
French (fr)
Other versions
EP2746876A3 (de
EP2746876A2 (de
Inventor
Daniel W. Younger
Jeff A. Ridley
Son T. Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/662,850 external-priority patent/US8941442B2/en
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Publication of EP2746876A2 publication Critical patent/EP2746876A2/de
Publication of EP2746876A3 publication Critical patent/EP2746876A3/de
Application granted granted Critical
Publication of EP2746876B1 publication Critical patent/EP2746876B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
    • G04F5/14—Apparatus for producing preselected time intervals for use as timing standards using atomic clocks
    • G04F5/145—Apparatus for producing preselected time intervals for use as timing standards using atomic clocks using Coherent Population Trapping

Definitions

  • Chip-Scale Atomic Clocks include vapor cells that contain vapors of an alkali metal such as rubidium (Rb).
  • the vapor cells also typically contain a buffer gas, such as an argon-nitrogen buffer gas blend.
  • the standard technique for fabricating the vapor cells involves anodically bonding two glass wafers on opposing sides of a silicon wafer having a plurality of cell structures that define cavities. The alkali metal vapor and buffer gas are trapped in the cavities of the cell structures between the two glass wafers.
  • the anodic bond joint starts at the locations between the wafers that are initially in contact and spreads out as the electrostatic potential brings the surfaces together. This lag of the bond front from one area to the next can lead to pressure differences in the vapor cells. Additionally, the presence of a low boiling temperature material like Rb requires the bonding to take place at as low a temperature as possible, otherwise the vapor generated can foul the bond surface. Thus, a high voltage needs to be applied as the wafers are heating, to allow the bond to form as soon as possible. This can result in vapor cells sealing at different times, and thus at different temperatures, which can result in pressure differences in the vapor cells, even on cells that are fabricated side-by-side on the same wafer.
  • the voltage that is applied to accomplish anodic bonding can create a breakdown of the gas, causing a discharge or arc through the gas to ground, essentially shorting out the bonding process.
  • EP 1 591 846 A2 discloses an apparatus comprising a dye structure having a first outside layer, a middle layer and a second outside layer.
  • the middle layer comprises a cavity that holds an alkali metal, and one of the first outside layer and the second outside layer comprises a channel that leads to the cavity.
  • a method of fabricating one or more vapor cells comprises forming one or more vapor cell dies in a first wafer having a first diameter, and anodically bonding a second wafer to a first side of the first wafer over the vapor cell dies, the second wafer having a second diameter.
  • a third wafer is positioned over the vapor cell dies on a second side of the first wafer opposite from the second wafer, with the third wafer having a third diameter.
  • a sacrificial wafer is placed over the third wafer, with the sacrificial wafer having a diameter that is larger than the first, second and third diameters.
  • a metallized bond plate is located over the sacrificial wafer.
  • the third wafer is anodically bonded to the second side of the first wafer when a voltage is applied to the metallized bond plate while the sacrificial wafer is in place.
  • Fabrication techniques are provided for enhancing gas pressure uniformity in anodically bonded vapor cells used in Chip-Scale Atomic Clocks (CSACs).
  • the vapor cells are fabricated with a pair of optically clear glass wafers that are anodically bonded to opposing sides of a substrate such as a silicon wafer having a plurality of cell structures.
  • the vapor cells are fabricated prior to assembly within a physics package for the CSAC.
  • a design feature is incorporated into a wafer surface that creates interconnected vent channels that provide a path from each vapor cell die in the wafer to the perimeter of the wafer.
  • the vent channels allow gas near the interior of the wafer to be in substantially continuous pressure-equilibrium with gas outside of the wafer during anodic bonding.
  • the anodic bonding process is modified to continually ramp pressure upward as temperature is ramped upward.
  • FIG. 1 illustrates a CSAC physics package 100 according to one embodiment, which can employ a vapor cell fabricated according to the present approach.
  • the physics package 100 includes an enclosure 102, which houses various mechanical and electronic components of physics package 100. These components can be fabricated as wafer-level micro-electro-mechanical systems (MEMS) devices prior to assembly in enclosure 102.
  • the CSAC components in physics package 100 include a laser die 110 such as a vertical-cavity surface-emitting laser (VCSEL), a quarter wave plate 120 in optical communication with laser die 110, a vapor cell 130 in optical communication with quarter wave plate 120, and an optical detector 140 in optical communication with vapor cell 130.
  • VCSEL vertical-cavity surface-emitting laser
  • a laser beam 112 emitted from laser die 110 is directed to pass through quarter wave plate 120 and vapor cell 130 to optical detector 140 during operation of physics package 100.
  • quarter wave plate 120, vapor cell 130, and optical detector 140 can be mounted within package 102 at various tilt angles with respect to the optical path of laser beam 112. Tilting these components reduces reflective coupling back into the VCSEL, enhancing CSAC stability.
  • a lower scaffold 150 is attached to a base surface 104 in enclosure 102.
  • the lower scaffold 150 includes a lower tier 152 that supports laser die 110, a middle tier 154 that supports quarter wave plate 120 above laser die 110, and an upper tier 156 that supports vapor cell 130 above quarter wave plate 120.
  • An upper scaffold structure 160 is attached to a top surface 106 in enclosure 102.
  • the optical detector 140 is affixed to upper scaffold structure 160 above vapor cell 130.
  • the vapor cell 130 includes a pair of optically clear wafers 132 and 134 such as glass wafers, which are anodically bonded to opposing sides of a substrate 136 such as a silicon wafer.
  • exemplary glass wafers include Pyrex glass or similar glasses.
  • At least one chamber 138 defined within vapor cell 130 provides an optical path between laser die 110 and optical detector 140 for laser beam 112.
  • wafer 132 is initially anodically bonded to a base side of substrate 136, after which rubidium or other alkali metal (either in liquid or solid form) is deposited into chamber 138.
  • the wafer 134 is then anodically bonded to the opposing side of substrate 136 to form vapor cell 130.
  • Such bonding typically is accomplished at temperatures from about 250 °C to about 400 °C.
  • the bonding process is performed with the wafers 132, 134, and substrate 136, either under high vacuum or backfilled with a buffer gas, such as an argon-nitrogen gas mixture.
  • the manufacturing equipment containing the components for vapor cell 130 is evacuated, after which the buffer gas is backfilled into chamber 138.
  • the buffer gas is backfilled into chamber 138.
  • the glass wafers which contain mobile ions such as sodium, are brought into contact with the silicon wafer, with an electrical contact to both the glass and silicon wafers.
  • Both the glass and silicon wafers are heated to at least about 200 °C, and a glass wafer electrode is made negative, by at least about 200 V, with respect to the silicon wafer.
  • This causes the sodium in the glass to move toward the negative electrode, and allows for more voltage to be dropped across the gaps between the glass and silicon, causing more intimate contact.
  • oxygen ions are released from the glass and flow toward the silicon, helping to form a bridge between the silicon in the glass and the silicon in the silicon wafer, which forms a very strong bond.
  • the anodic bonding process can be operated with a wide variety of background gases and pressures, from well above atmospheric to high vacuum. Higher gas pressures improve heat transfer, and speed up the process. In the case of Rb vapor cells, it is desirable to form a bond at as low a temperature as possible, in the presence of a buffer gas.
  • the anodic bonding process can be is enhanced by applying a higher voltage during the bonding process, but higher voltage in the presence of a gas can cause arcing.
  • Arcing is a function of the gas type, pressure and distance between electrodes. Arcing can be mitigated by creating a larger path to ground, thus increasing the potential needed to cause the arc.
  • the gas type and pressure cannot be altered, then increasing the distance between electrodes can provide a way for applying higher voltage.
  • This can be done by using a sacrificial glass wafer that is inserted between the upper glass wafer of the vapor cell and a high voltage source.
  • the sacrificial glass wafer has a larger diameter than the vapor cell wafers. This allows for the applied voltage to be much higher at the start of the process, which provides for a much improved bonding environment.
  • the applied higher voltage can be from about 800 volts to about 1200 volts.
  • the sacrificial glass wafer is of the same type as the vapor cell glass wafers used to bond to silicon, and as such allows the passage of current through the mobile ions.
  • the distance from the high voltage electrode and the top surface of the silicon wafer, which is near ground potential is increased. This allows for higher voltage bonding without arcing.
  • the excess sodium that would normally pool on top of the upper glass wafer of the vapor cell is minimized, due to the ability of the sodium ions to pass into the sacrificial glass wafer. This almost eliminates the pitting normally seen on a glass wafer, creating a cleaner light path through the glass. Further details with respect to the sacrificial glass wafer are described hereafter with respect to Figure 5 .
  • Figure 2 illustrates one embodiment of a vapor cell die 200 for a CSAC physics package that has been formed on a wafer layer.
  • the vapor cell die 200 includes a silicon substrate 205 in which a first chamber 210, a second chamber 220, and at least one connecting pathway 215 have been formed.
  • the chambers 210, 220, and pathway 215 are sealed within vapor cell die 200 between glass wafers (such as glass wafers 132, 134) using anodic bonding as described above.
  • chamber 210 comprises part of the optical path for the physics package and needs to be kept free of contaminants and precipitates.
  • the rubidium or other alkali metal (shown generally at 235) is deposited as a liquid or solid into chamber 220.
  • the connecting pathway 215 establishes a "tortuous path" (illustrated generally at 230) for the alkali metal vapor molecules to travel from second chamber 220 to first chamber 210. Because of the dynamics of gas molecules, the alkali metal vapor molecules do not flow smoothly through pathway 215, but rather bounce off of the walls of pathway 215 and frequently stick to the walls.
  • second chamber 220 is isolated from pathway 215 except for a shallow trench 245 to further slow migration of alkali metal vapor from the second chamber 220.
  • the anodic bond joint starts at the locations between the wafers that are initially in contact and spreads out as the electrostatic potential brings the surfaces together. This lag of the bond front from one area to the next can lead to pressure differences if there is no path for gas to move out from between the wafers as the bond fronts move together. This can result in poor buffer gas uniformity in the fabricated vapor cells.
  • a low melting temperature material like Rb requires the bonding to take place at as low a temperature as possible, otherwise the vapor generated can foul the bond surface.
  • a high voltage needs to be applied as the wafers are heating, to allow the bond to form as soon as possible. This can result in vapor cells sealing at different times, and thus at different temperatures, which can also produce pressure differences in the fabricated vapor cells.
  • the problem of poor buffer gas uniformity in fabricated vapor cells can be solved using the techniques discussed hereafter.
  • vent channels are formed in a surface of the silicon wafer in order to provide pathways for gas to escape to a perimeter of the wafer during anodic bonding.
  • Figure 3 shows a wafer 300 for fabricating vapor cells used in a CSAC.
  • the wafer 300 includes a plurality of vapor cell dies 302 and interconnected vent channels 304 that surround vapor cell dies 302.
  • the vapor cell dies 302 and vent channels 304 are located in an interior surface region 306 of wafer 300.
  • the vent channels 304 can be formed with the same processes used to form vapor cell dies 302.
  • the vent channels 304 provide at least one pathway for gas from each vapor cell die to travel outside of a perimeter 308 of wafer 300.
  • the vent channels 304 allow gas toward the interior surface region 306 to be in substantially continuous pressure-equilibrium with gas outside of perimeter 308 during anodic bonding of glass wafers to opposing sides of wafer 300.
  • the anodic bonding process is modified to continually ramp pressure upward as temperature (measured in degrees Kelvin, or degrees absolute) is ramped upward.
  • anodic bonding of a first wafer such as a silicon wafer is carried out by increasing a temperature of the first wafer at predetermined rate during anodic bonding of the first wafer to a second wafer such as a glass wafer.
  • the silicon wafer has a plurality of dies each with at least one chamber.
  • a gas pressure between the first and second wafers is also increased at a predetermined rate while the temperature is increasing during anodic bonding.
  • the pressure is increased from about 100 torr (13332.2 Pa) to about 600 torr (79993.2 Pa).
  • the pressure can have a starting value of about 100-300 torr (13332.2-39996.6 Pa), and an ending value of about 500-600 torr (66661 - 79993.2 Pa).
  • utilizing the vent channels in the wafer surface along with pressure ramping allows vapor cells that are sealed later in the process, and thus at higher temperature, to also have a higher gas pressure.
  • the vapor cells sealed at a higher temperature will drop in pressure more than those sealed at a lower temperature.
  • the later sealing vapor cells can be compensated so the final pressure of all vapor cells is about the same at room temperature.
  • the ideal gas law ensures than n (the molar density of the gas in the cells) will remain constant across the wafer.
  • FIG. 4 illustrates a CSAC physics package 400 according to another embodiment.
  • the physics package 400 includes an enclosure 402, which houses various mechanical and electronic components of the CSAC. These components can be fabricated as wafer-level micro-electro-mechanical systems (MEMS) devices prior to assembly in physics package 400.
  • the CSAC components in physics package 400 include a laser die 410 such as a vertical-cavity surface-emitting laser (VCSEL), a quarter wave plate 420 in optical communication with laser die 410, a vapor cell 430 in optical communication with quarter wave plate 420, and a first photodetector 440 in optical communication with vapor cell 430.
  • a laser beam 412 emitted from laser die 410 is directed to pass through quarter wave plate 420 and vapor cell 430 to optical detector 440 during operation of the CSAC.
  • the enclosure 402 includes a body 403 that defines a cavity 404 for holding the components of physics package 400.
  • the enclosure 402 also includes a lid 405 configured to fit over cavity 404 to enclose the components therein.
  • a solder 406 can be used to seal lid 405 to body 403.
  • the cavity 404 is defined by a side surface 407 and a base surface 411 in body 403.
  • the side surface 407 has a lower step 408 and an upper step 409, which along with base surface 411 support various components of the CSAC in a raised position as described further hereafter.
  • the enclosure 402 can be made of a ceramic material such as a high temperature co-fired ceramic (HTCC) material, for example.
  • HTCC high temperature co-fired ceramic
  • the various components of physics package 400 are positioned at different levels within enclosure 402 by a set of scaffold structures.
  • the scaffold structures generally include a membrane such as a tether suspended between a frame, and a stiffening member such as a die attached to the membrane.
  • the frame and stiffening member can be composed of silicon and the membrane can be composed of polyimide, for example.
  • a lower scaffold structure 450 is attached to base surface 411 in body 403.
  • the lower scaffold structure 450 includes a scaffold die 452 coupled to a tether 454 that is attached to a frame 455.
  • the laser die 410 is mounted to an upper surface of die 452 along with other electronic components, including a second photodetector 442 and a resistor 444 such as a surface mount technology (SMT) resistor.
  • SMT surface mount technology
  • a middle scaffold structure 460 includes a scaffold die 462 coupled to a tether 464 that is attached to a frame 465.
  • the scaffold die 462 has an opening therethrough to permit passage of laser beam 412.
  • the middle scaffold structure 460 has a tilting feature 466 on which quarter wave plate 420 is mounted, such as with an adhesive.
  • quarter wave plate 420 can be mounted on tilting feature 466 at a preselected tilt angle with respect to the optical path of laser beam 412.
  • the middle scaffold structure 460 has an upper surface 467 on which vapor cell 430 is mounted, such as with an adhesive.
  • the middle scaffold structure 460 is attached to a spacer 470 on a lower surface 472 thereof with an adhesive such as an epoxy or other suitable attachment method.
  • An upper scaffold structure 480 is positioned over spacer 470, and includes a scaffold die 482 coupled to a tether 484 that is attached to a frame 485.
  • the photodetector 440 is attached to die 482 above vapor cell 430.
  • the vapor cell 430 is also attached to die 482 through a plurality of solder balls 484, which keep photodetector 440 and vapor cell 430 spaced apart from each other.
  • the upper scaffold structure 480 is attached to an upper surface 474 of spacer 470 with an adhesive such as an epoxy or other suitable attachment method.
  • the spacer 470 which can be in the shape of a washer, defines an aperture 476 in which vapor cell 430 is located.
  • the spacer 470 includes interconnect wiring 477 to provide electrical contacts for upper scaffold structure 480 and middle scaffold structure 460.
  • the spacer 70 also includes magnetic coil windings 478 that provide a bias field for vapor cell 430.
  • the spacer 470 is mounted to upper step 409 of enclosure 402 with an adhesive such as an epoxy.
  • a plurality of metal stud bumps 479 such as gold stud bumps, provide electrical connections from spacer 470 to enclosure 402 and to scaffold structures 460, 480.
  • the spacer 470 can be made of a ceramic material such as a low temperature co-fired ceramic (LTCC) material.
  • LTCC low temperature co-fired ceramic
  • the vapor cell 430 includes a pair of optically clear glass wafers, including a lower glass wafer 432 and an upper glass wafer 434 that are anodically bonded to opposing sides of a substrate such as a silicon wafer 436. At least one chamber 438 within vapor cell 430 provides an optical path between laser die 410 and photodetector 440 for laser beam 412.
  • lower glass wafer 432 is initially anodically bonded to a base side of substrate 436, after which rubidium or other alkali metal is deposited into chamber 438.
  • the upper glass wafer 434 is then anodically bonded to the opposing side of substrate 436 to form vapor cell 430.
  • the bonding process is performed with the wafers glass 432, 434 and silicon wafer 436 either under high vacuum or optionally backfilled with a buffer gas.
  • FIG. 5 shows a wafer configuration 500 used in the enhanced anionic bonding approach.
  • a vapor cell 502 has been partially formed and includes a first wafer 504 such as a silicon wafer, and a second wafer 506 such as a glass wafer that is anodically bonded to one side of first wafer 504.
  • a third wafer 508 such as a glass wafer is positioned on an opposing side of first wafer 504. As shown in Figure 5 , the first wafer 504, second wafer 506, and third wafer 508 all have substantially the same diameter D-1.
  • a sacrificial wafer 510 such as a sacrificial glass wafer is inserted between third wafer 508 and a metallized bond plate 512 that connects to a high voltage source.
  • the sacrificial wafer 510 has a diameter D-2 that is larger than diameter D-1.
  • D-2 the distance from an exposed portion 514 of metallized bond plate 512 to the bonding surface of the silicon wafer, which is near ground potential, is increased.
  • the diameter D-2 of sacrificial wafer 510 is sufficiently large so as to prevent arcing when third wafer 508 is anodically bonded to first wafer 504.
  • FIG. 6 illustrates one embodiment of a vapor cell die 600 for a CSAC physics package that has been formed on a wafer layer.
  • the vapor cell die 600 includes a substrate 605 such as a silicon substrate in which a first chamber 610, a second chamber 615, and at least one connecting pathway 620 have been formed.
  • the chambers 610, 615, and pathway 620 can be sealed within vapor cell die 600 between glass wafers using anodic bonding as described above.
  • the first chamber 610 comprises part of the optical path for the CSAC.
  • the connecting pathway 620 establishes a "tortuous path" for the alkali metal vapor molecules to travel from second chamber 615 to first chamber 610.
  • vent channels can be formed in a surface of the silicon wafer in order to provide pathways for gas to escape to a perimeter of the wafer during anodic bonding.
  • Figure 7 illustrates another embodiment of this approach, in which a silicon wafer 700 is used for fabricating vapor cells.
  • the wafer 700 includes a plurality of vapor cell dies 702 and interconnected vent channels 704 that surround vapor cell dies 702.
  • the vapor cell dies 702 and vent channels 704 are located in an interior surface region 706 of wafer 700.
  • the vent channels 704 can be formed with the same processes used to form vapor cell dies 702.
  • vent channels 704 provide multiple pathways for gas from each vapor cell die to travel outside of a perimeter 708 of wafer 700.
  • the vent channels 704 allow gas toward the interior surface region 706 to be in substantially continuous pressure-equilibrium with gas outside of perimeter 708 during anodic bonding of glass wafers to opposing sides of wafer 700.

Landscapes

  • Life Sciences & Earth Sciences (AREA)
  • Ecology (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
  • Ceramic Products (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Fluid Pressure (AREA)

Claims (10)

  1. Verfahren zum Herstellen einer oder mehrerer Dampfzellen, (430; 502), das Verfahren Folgendes umfassend:
    Ausbilden eines oder mehrerer Dampfzellenchips (200; 302; 600; 702) in einem ersten Wafer (504), der einen Innenflächenbereich und einen Umfang aufweist, wobei der erste Wafer einen ersten Durchmesser (D-1) aufweist;
    anodisches Verbinden eines zweiten Wafers (506) an einer ersten Seite des ersten Wafers (504) über den Dampfzellenchips, wobei der zweite Wafer (506) einen zweiten Durchmesser (D-1) aufweist;
    Positionieren eines dritten Wafers (508) über den Dampfzellenchips auf einer zweiten Seite des ersten Wafers (504), die dem zweiten Wafer (506) entgegengesetzt ist, wobei der dritte Wafer (508) einen dritten Durchmesser (D-1) aufweist;
    Platzieren eines Opfer-Wafers (510) über dem dritten Wafer (508), wobei der Opfer-Wafer (510) einen Durchmesser (D-2) aufweist, der größer ist als der erste, der zweite und der dritte Durchmesser;
    Anordnen einer metallisierten Verbindungsplatte (512) über dem Opfer-Wafer (510); und
    anodisches Verbinden des dritten Wafers (508) an der zweiten Seite des ersten Wafers (504), wenn eine Spannung an die metallisierte Verbindungsplatte (512) angelegt wird, während sich der Opfer-Wafer (510) am Ort befindet.
  2. Verfahren nach Anspruch 1, wobei der erste Wafer (504) einen Silizium-Wafer umfasst, der zweite und der dritte Wafer (506; 508) jeweils einen Glas-Wafer umfassen und der Opfer-Wafer (510) einen Glas-Wafer umfasst.
  3. Verfahren nach Anspruch 1, wobei der Durchmesser des Opfer-Wafers (510) ausreichend groß ist, um einen Überschlag zu verhindern, wenn die Spannung an die metallisierte Verbindungsplatte (512) angelegt wird.
  4. Verfahren nach Anspruch 1, weiterhin umfassend Ausbilden eines oder mehrerer miteinander verbundener Luftkanäle (304; 704) in dem ersten Wafer, wobei die Luftkanäle (304; 704) mindestens einen Weg für Gas aus dem einen oder den mehreren Dampfzellenchips (302; 702) bereitstellen, um außerhalb des Umfangs des ersten Wafers zu gelangen.
  5. Verfahren nach Anspruch 4, wobei die Luftkanäle (704) ermöglichen, dass sich Gas zu dem Innenflächenbereich des ersten Wafers hin während des anodischen Verbindens des zweiten und des dritten Wafers an dem ersten Wafer im Wesentlichen in einem kontinuierlichen Druckgleichgewicht mit Gas außerhalb des Umfangs des ersten Wafers befindet.
  6. Verfahren nach Anspruch 1, wobei die eine oder die mehreren Dampfzellen für ein Atomuhr-Physikpaket im Chip-Maßstab (100; 400) konfiguriert sind.
  7. Verfahren nach Anspruch 1, wobei der eine oder die mehreren Dampfzellenchips jeweils ein Substrat mit einer ersten Kammer (210; 610), einer zweiten Kammer (220; 615) und mindestens einem Verbindungsweg (215; 620) zwischen der ersten und der zweiten Kammer umfassen.
  8. Verfahren nach Anspruch 1, wobei während des anodischen Verbindens eine Temperatur des ersten Wafers (504) mit einer vorgegebenen Rate linear ansteigt und ein Gasdruck mit einer vorgegebenen Rate linear ansteigt, während die Temperatur linear ansteigt.
  9. Wafer-Konfiguration (500) zum Herstellen von Dampfzellen (430, 502), Folgendes umfassend:
    einen ersten Wafer (504), umfassend mehrere Dampfzellenchips (200; 302; 600; 702), wobei der erste Wafer (504) einen Innenflächenbereich und einen Umfang aufweist, wobei der erste Wafer (504) einen ersten Durchmesser (D-1) aufweist;
    einen zweiten Wafer (506), der an einer ersten Seite des ersten Wafers (504) über den Dampfzellenchips anodisch verbunden ist, wobei der zweite Wafer (506) einen zweiten Durchmesser (D-1) aufweist, der im Wesentlichen der gleiche ist wie der erste Durchmesser;
    einen dritten Wafer (508), der über den Dampfzellenchips auf einer zweiten Seite des ersten Wafers (504) angeordnet ist, die dem zweiten Wafer (506) entgegengesetzt ist, wobei der dritte Wafer (508) einen dritten Durchmesser (D-1) aufweist, der im Wesentlichen der gleiche ist wie der erste und der zweite Durchmesser; und
    einen Opfer-Wafer (510), der über dem dritten Wafer (508) angeordnet ist, wobei der Opfer-Wafer (510) einen Durchmesser (D-2) aufweist, der größer ist als der erste, der zweite und der dritte Durchmesser;
    wobei der Durchmesser (D-2) des Opfer-Wafers (510) ausreichend groß ist, um einen Überschlag zu verhindern, wenn der dritte Wafer anodisch an den ersten Wafer (504) gebunden wird.
  10. Wafer-Konfiguration nach Anspruch 9, weiterhin umfassend eine metallisierte Verbindungsplatte (512), wobei der Opfer-Wafer (510) zwischen dem dritten Wafer (508) und der metallisierten Verbindungsplatte (512) angeordnet ist.
EP13181421.2A 2012-10-29 2013-08-22 Herstellungstechniken zur Verbesserung der Druckgleichförmigkeit in anodisch gebundenen Dampfzellen und Mikroplättchenstruktur dazu Active EP2746876B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/662,850 US8941442B2 (en) 2010-02-04 2012-10-29 Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells

Publications (3)

Publication Number Publication Date
EP2746876A2 EP2746876A2 (de) 2014-06-25
EP2746876A3 EP2746876A3 (de) 2018-01-10
EP2746876B1 true EP2746876B1 (de) 2019-04-10

Family

ID=49028964

Family Applications (1)

Application Number Title Priority Date Filing Date
EP13181421.2A Active EP2746876B1 (de) 2012-10-29 2013-08-22 Herstellungstechniken zur Verbesserung der Druckgleichförmigkeit in anodisch gebundenen Dampfzellen und Mikroplättchenstruktur dazu

Country Status (3)

Country Link
EP (1) EP2746876B1 (de)
JP (1) JP6198522B2 (de)
CN (1) CN103792838B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6488599B2 (ja) 2014-09-08 2019-03-27 セイコーエプソン株式会社 量子干渉装置、原子セルの製造方法および電子機器
JP6852377B2 (ja) * 2016-12-12 2021-03-31 株式会社村田製作所 原子発振器および電子機器
CN107128871B (zh) * 2017-05-10 2019-04-05 中国电子科技集团公司第四十九研究所 一种基于mems原子芯片的物理封装件及其封装方法
US10544039B2 (en) * 2017-09-08 2020-01-28 Texas Instruments Incorporated Methods for depositing a measured amount of a species in a sealed cavity
JP2019165332A (ja) * 2018-03-19 2019-09-26 株式会社リコー 電子デバイスおよび原子発振器
JP7232510B2 (ja) * 2019-01-31 2023-03-03 国立研究開発法人情報通信研究機構 量子光学装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005016965A (ja) * 2003-06-23 2005-01-20 Sumitomo Precision Prod Co Ltd パッケージおよびその製造方法、ならびに振動ジャイロおよびその製造方法
US7400207B2 (en) * 2004-01-06 2008-07-15 Sarnoff Corporation Anodically bonded cell, method for making same and systems incorporating same
US7292111B2 (en) * 2004-04-26 2007-11-06 Northrop Grumman Corporation Middle layer of die structure that comprises a cavity that holds an alkali metal
WO2006036268A2 (en) * 2004-07-16 2006-04-06 Sarnoff Corporation Chip-scale atomic clock (csac) and method for making same
JP5121493B2 (ja) * 2008-02-21 2013-01-16 セイコーインスツル株式会社 圧電振動子の製造方法
JP2009212416A (ja) * 2008-03-06 2009-09-17 Epson Toyocom Corp ガスセルの製造方法及びガスセル
JP2009215099A (ja) * 2008-03-10 2009-09-24 Konica Minolta Holdings Inc 陽極接合方法及び液滴吐出ヘッドの製造方法
CN101407372B (zh) * 2008-11-07 2011-01-12 清华大学 一种原子蒸气泡的制作方法
CN101598772B (zh) * 2009-06-26 2011-12-07 中北大学 微型原子蒸汽泡制作方法
JP5421690B2 (ja) * 2009-08-12 2014-02-19 セイコーインスツル株式会社 パッケージの製造方法
US8299860B2 (en) * 2010-02-04 2012-10-30 Honeywell International Inc. Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells
US20110187464A1 (en) * 2010-02-04 2011-08-04 Honeywell International Inc. Apparatus and methods for alkali vapor cells
US8242851B2 (en) * 2010-02-04 2012-08-14 Honeywell International Inc. Processes for stabilizing a VCSEL in a chip-scale atomic clock
JP2012191138A (ja) * 2011-03-14 2012-10-04 Seiko Epson Corp ガスセルユニット、原子発振器および電子装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
EP2746876A3 (de) 2018-01-10
CN103792838B (zh) 2017-08-11
CN103792838A (zh) 2014-05-14
EP2746876A2 (de) 2014-06-25
JP2014088308A (ja) 2014-05-15
JP6198522B2 (ja) 2017-09-20

Similar Documents

Publication Publication Date Title
EP2362281B1 (de) Herstellungstechniken zur Verbesserung der Druckgleichförmigkeit in anodisch gebundenen Dampfzellen
US8941442B2 (en) Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells
EP2746876B1 (de) Herstellungstechniken zur Verbesserung der Druckgleichförmigkeit in anodisch gebundenen Dampfzellen und Mikroplättchenstruktur dazu
EP1591846B1 (de) Mittelschicht für Matrizeanordnung mit einem alkalimetalgefüllten Hohlraum
US6900702B2 (en) MEMS frequency standard for devices such as atomic clock
US7204737B2 (en) Hermetically sealed microdevice with getter shield
US10266392B2 (en) Environment-resistant module, micropackage and methods of manufacturing same
KR20160053935A (ko) 수직형 피드스루들을 이용한 웨이퍼-레벨 허메틱 패키징 방법
US6939778B2 (en) Method of joining an insulator element to a substrate
US7524704B2 (en) Method for encapsulating a component, especially an electric or electronic component, by means of an improved solder seam
US9718674B2 (en) Thin capping for MEMS devices
Du et al. CMOS compatible hermetic packages based on localized fusion bonding of fused silica
KR101529543B1 (ko) 멤즈 소자의 진공 패키징 방법
JP2010243365A (ja) 赤外線センサ装置の製造方法
EP4375232A1 (de) Verfahren zum bonden einer mikroelektromechanischen vorrichtung
Yufeng et al. MEMS vacuum packaging technology and applications
EP2736071B1 (de) Verkapselung mit Getter auf Waferebene

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20130822

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: HONEYWELL INTERNATIONAL INC.

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

RIC1 Information provided on ipc code assigned before grant

Ipc: G04F 5/14 20060101AFI20171201BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20181016

GRAJ Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted

Free format text: ORIGINAL CODE: EPIDOSDIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

INTG Intention to grant announced

Effective date: 20190222

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 1119537

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190415

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602013053574

Country of ref document: DE

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20190410

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1119537

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190410

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190710

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190910

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190710

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190711

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190810

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602013053574

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602013053574

Country of ref document: DE

26N No opposition filed

Effective date: 20200113

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20190822

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190822

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190831

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190831

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20190831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190822

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190822

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20130822

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190410

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230525

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230824

Year of fee payment: 11