EP2457155A4 - Ordinateur à faible consommation d' énergie et grande vitesse sans goulet d' étranglement de mémoire - Google Patents

Ordinateur à faible consommation d' énergie et grande vitesse sans goulet d' étranglement de mémoire

Info

Publication number
EP2457155A4
EP2457155A4 EP10802066.0A EP10802066A EP2457155A4 EP 2457155 A4 EP2457155 A4 EP 2457155A4 EP 10802066 A EP10802066 A EP 10802066A EP 2457155 A4 EP2457155 A4 EP 2457155A4
Authority
EP
European Patent Office
Prior art keywords
high speed
lower energy
speed computer
memory bottleneck
energy comsumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP10802066.0A
Other languages
German (de)
English (en)
Other versions
EP2457155A1 (fr
EP2457155B1 (fr
Inventor
Tadao Nakamura
Michael J Flynn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to EP17180711.8A priority Critical patent/EP3255555B1/fr
Publication of EP2457155A1 publication Critical patent/EP2457155A1/fr
Publication of EP2457155A4 publication Critical patent/EP2457155A4/fr
Application granted granted Critical
Publication of EP2457155B1 publication Critical patent/EP2457155B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
EP10802066.0A 2009-07-21 2010-07-20 Ordinateur à faible consommation d' énergie et grande vitesse sans goulet d' étranglement de mémoire Active EP2457155B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP17180711.8A EP3255555B1 (fr) 2009-07-21 2010-07-20 Ordinateur de faible consommation d'énergie et à grande vitesse sans goulot d'étranglement de mémoire

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22732509P 2009-07-21 2009-07-21
PCT/JP2010/004642 WO2011010445A1 (fr) 2009-07-21 2010-07-20 Ordinateur à faible consommation d’énergie et grande vitesse sans goulet d’étranglement de mémoire

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP17180711.8A Division EP3255555B1 (fr) 2009-07-21 2010-07-20 Ordinateur de faible consommation d'énergie et à grande vitesse sans goulot d'étranglement de mémoire
EP17180711.8A Division-Into EP3255555B1 (fr) 2009-07-21 2010-07-20 Ordinateur de faible consommation d'énergie et à grande vitesse sans goulot d'étranglement de mémoire

Publications (3)

Publication Number Publication Date
EP2457155A1 EP2457155A1 (fr) 2012-05-30
EP2457155A4 true EP2457155A4 (fr) 2014-07-23
EP2457155B1 EP2457155B1 (fr) 2017-10-11

Family

ID=43498927

Family Applications (2)

Application Number Title Priority Date Filing Date
EP17180711.8A Active EP3255555B1 (fr) 2009-07-21 2010-07-20 Ordinateur de faible consommation d'énergie et à grande vitesse sans goulot d'étranglement de mémoire
EP10802066.0A Active EP2457155B1 (fr) 2009-07-21 2010-07-20 Ordinateur à faible consommation d' énergie et grande vitesse sans goulet d' étranglement de mémoire

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP17180711.8A Active EP3255555B1 (fr) 2009-07-21 2010-07-20 Ordinateur de faible consommation d'énergie et à grande vitesse sans goulot d'étranglement de mémoire

Country Status (6)

Country Link
US (2) US8949650B2 (fr)
EP (2) EP3255555B1 (fr)
JP (1) JP5417674B2 (fr)
KR (1) KR101424020B1 (fr)
CN (1) CN102483697B (fr)
WO (1) WO2011010445A1 (fr)

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KR20130010915A (ko) * 2012-10-23 2013-01-29 김성동 챕터 데이터가 저장될 수 있는 캐쉬 메모리 어레이를 구비하는 3차원 반도체 장치 및 그 동작 방법
TWI557749B (zh) * 2013-06-13 2016-11-11 中村維男 直接轉移跨步記憶體及使用該記憶體之電腦系統
WO2015125960A1 (fr) * 2014-02-24 2015-08-27 株式会社ニコン Dispositif de traitement d'informations, caméra numérique et processeur
US9513921B2 (en) * 2014-06-23 2016-12-06 Mill Computing, Inc. Computer processor employing temporal addressing for storage of transient operands
CN104777936B (zh) * 2015-04-16 2016-08-24 京东方科技集团股份有限公司 触控驱动单元和电路、显示面板及显示装置
CN108352837A (zh) * 2015-11-13 2018-07-31 株式会社半导体能源研究所 半导体装置、电子构件及电子设备
CN111651206B (zh) * 2016-04-26 2024-05-07 中科寒武纪科技股份有限公司 一种用于执行向量外积运算的装置和方法
US10909037B2 (en) * 2017-04-21 2021-02-02 Intel Corpor Ation Optimizing memory address compression
CN109426518B (zh) * 2017-08-29 2021-02-19 杭州旗捷科技有限公司 单核处理器设备的并行写码方法、电子设备、存储介质
JP7228590B2 (ja) * 2017-11-24 2023-02-24 フラウンホッファー－ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー．ファオ データバス
WO2019146623A1 (fr) * 2018-01-23 2019-08-01 Tadao Nakamura Mémoire à défilement et système informatique
KR102543177B1 (ko) * 2018-03-12 2023-06-14 삼성전자주식회사 고 대역폭 메모리 장치 및 이 장치를 포함하는 시스템 장치
US10996885B2 (en) 2018-03-12 2021-05-04 Samsung Electronics Co., Ltd. High bandwidth memory device and system device having the same
CN116049093A (zh) * 2018-12-10 2023-05-02 杭州海存信息技术有限公司 分离的三维处理器
US11853758B2 (en) 2019-09-27 2023-12-26 Intel Corporation Techniques for decoupled access-execute near-memory processing
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See also references of WO2011010445A1 *

Also Published As

Publication number Publication date
EP3255555B1 (fr) 2020-01-29
CN102483697B (zh) 2015-06-10
EP2457155A1 (fr) 2012-05-30
JP5417674B2 (ja) 2014-02-19
JP2012533784A (ja) 2012-12-27
US20120117412A1 (en) 2012-05-10
EP3255555A1 (fr) 2017-12-13
US9361957B2 (en) 2016-06-07
CN102483697A (zh) 2012-05-30
KR101424020B1 (ko) 2014-07-28
WO2011010445A1 (fr) 2011-01-27
EP2457155B1 (fr) 2017-10-11
US20150149718A1 (en) 2015-05-28
US8949650B2 (en) 2015-02-03
KR20120048596A (ko) 2012-05-15

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