EP2449586B1 - Elektronische vorrichtung - Google Patents

Elektronische vorrichtung Download PDF

Info

Publication number
EP2449586B1
EP2449586B1 EP10744841.7A EP10744841A EP2449586B1 EP 2449586 B1 EP2449586 B1 EP 2449586B1 EP 10744841 A EP10744841 A EP 10744841A EP 2449586 B1 EP2449586 B1 EP 2449586B1
Authority
EP
European Patent Office
Prior art keywords
metallization
layer thickness
region
metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP10744841.7A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2449586A2 (de
Inventor
Jürgen SCHULZ-HARDER
Andreas Meyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rogers Germany GmbH
Original Assignee
Rogers Germany GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rogers Germany GmbH filed Critical Rogers Germany GmbH
Publication of EP2449586A2 publication Critical patent/EP2449586A2/de
Application granted granted Critical
Publication of EP2449586B1 publication Critical patent/EP2449586B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact

Definitions

  • the invention relates to electronic devices or to electronic circuits and / or a module according to the preamble of patent claim 1.
  • DCB process Direct Copper Bond Technology
  • metal layers or sheets for example copper sheets or foils
  • ceramic or ceramic layers specifically using metal - or copper sheets or metal or copper foils which have a layer or a coating (melting layer) made of a chemical compound of the metal and a reactive gas, preferably oxygen, on their surface sides.
  • this layer or this coating (melting layer) forms a eutectic with a melting temperature below the melting temperature of the metal (e.g. copper), so that by placing the foil on the ceramic and heating all the layers, these can be bonded to one another, namely by melting of the metal or copper essentially only in the area of the melted layer or oxide layer.
  • the so-called active soldering process is also known ( DE 22 13 1 15 ; EP-A-153 618 )
  • active soldering process for connecting metal layers or metal foils which form metallizations, in particular also copper layers or copper foils with ceramic material.
  • this method which is also used specifically for the production of metal-ceramic substrates, a connection between a metal foil, for example copper foil, and a ceramic substrate, for example aluminum nitride ceramic, is used at a temperature between approx. 800-1000 ° C
  • a hard solder is produced which, in addition to a main component such as copper, silver and / or gold, also contains an active metal.
  • This active metal which is, for example, at least one element from the group Hf, Ti, Zr, Nb, Ce, creates a connection between the solder and the ceramic by chemical reaction, while the connection between the solder and the metal is a metallic hard solder connection .
  • a copper-ceramic substrate is known, an intermediate layer being arranged between the ceramic support and a copper layer.
  • the intermediate layer protrudes in sections from the intermediate layer.
  • the DE 697 30 388 T2 describes a printed circuit board with a three-stage structure of the metallization.
  • the JP 9 283 703 discloses a metal-ceramic substrate with a metallization that has a stepped profile.
  • the object of the invention is to show electronic devices which, with regard to the cooling of power components, ie components that also generate considerable power loss and thus high heat during operation, are optimized. To achieve this object, electronic devices are designed in accordance with claim 1.
  • the inventive design takes into account not only optimal cooling of power components in electronic devices, circuits or modules, but also the increase in the reliability and service life of such devices, namely by the fact that the special design of the at least one power component carrying the first Metallization area this acts as a heat spreader that optimizes the cooling effect, but at the same time the volume of the metallic material in this metallization area is reduced to such an extent that temperature changes that occur during operation of a device, for example when switching loads, do not destroy the substrate and / or the components through thermally induced mechanical forces. Further developments of the invention are the subject of the subclaims.
  • the electronic device generally designated 1 in the figures consists essentially of a metal insulating layer substrate 2 with a preferably ceramic insulating layer 3, on the surface side of which a metallization 4 or 5 is provided.
  • the upper metallization 4 is structured, as shown in FIG Figure 1 is indicated with the two metallization areas 4.1 and 4.2.
  • the lower metallization 5 is formed continuously, ie it extends up to a free edge area Over the entire lower surface side of the insulating layer 3.
  • Suitable ceramics for the insulating layer 3 consist, for example, of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4) and / or silicon carbide (SiC) or of aluminum oxide and zirconium oxide (Al2O3 + ZrO2).
  • the thickness of the insulating layer 3 is in the order of magnitude between approximately 0.15 mm and 1 mm.
  • Suitable materials for the metallizations 4 and 5 or for the metallization areas 4.1 and 4.2 of the metallization 4 are, for example, copper, copper alloys or aluminum, aluminum alloys.
  • the metallizations 4 and 5 or, according to the invention, the metallization regions 4.1 and 4.2 are connected to the insulating layer 3 by DCB bonding.
  • the component 7 is a power component, for example a power semiconductor component or chip (IC), e.g. Transistor, diode, triac thyristor, etc. with increased power loss and with increased cooling requirement, while component 6 is such a low power and thus also low power loss, for example a semiconductor circuit or chip (IC) for driving component 7.
  • IC power semiconductor component or chip
  • a special feature of the device 1 or the metal insulating layer substrate 2 is that, according to the invention, the structured metallization 4 is essentially only in a sub-area 4.2.1 below the respective power component 7, ie in the embodiment shown below the component 7 has increased layer thickness D, otherwise the layer thickness d of the metallization 4 and its metallization areas 4.1 and 4.2, also of the sub-area 4.2.2, is significantly reduced and, according to the invention, is approximately equal to the layer thickness d of the lower metallization 5.
  • the metallization area 4.2 can thus be described in terms of its shape in such a way that, according to the invention, it consists of the sub-area 4.2.1 with the layer thickness D and the area surrounding it There is partial or edge area 4.2.2 with a smaller layer thickness d, the metallization area 4.2 according to the invention being designed in one piece or monolithically with these partial areas.
  • the metallization area 4.2 is designed step-shaped at its edge 8, namely in such a way that the component 7 from the edge of the uppermost step or from the edge of the sub-area 4.2.1 has a distance a1 which is at least equal to or slightly greater than the difference b of the layer thicknesses D and d, ie a1 ⁇ b.
  • the width a2 of the step formed by the stepped edge 8 is at least equal to the layer thickness d.
  • This formation or shaping of the metallization area 4.2 ensures that it can act in an optimal manner as a heat spreader for optimal cooling of the component 7, as shown in FIG Figure 2 is indicated by the broken lines 9, which run at an angle of 45 ° with respect to the plane of the surface sides of the insulating layer 3 or of the metal-insulating layer substrate 2.
  • this configuration sets the metal volume of the metallization area 4.2 and thus also the mechanical stresses between the metallization 4 or the metallization area 4.2 and the insulating layer 3 caused by temperature changes to a value that does not impair the service life of the device 1.
  • the layer thicknesses d and D that the layer thickness, in particular of the metallization 4 outside the power component 7, is selected so that a sufficiently large cross section is achieved for the conductor tracks generated by the structuring of the metallization 4 or for the currents to be expected, while the layer thickness D of the metallization 4 below the power component 7 is chosen to be sufficiently large for optimal cooling and, in particular, for optimal heat spread.
  • the layer thicknesses D and d are chosen so that their difference b is equal to or greater than d / 2.
  • the relationship applies that the sum of the distances a1 and a2 is at least equal, but preferably is greater than the layer thickness D that the metallization area 4.2 has under the component 7, that is, a1 + a2> D.
  • the layer thickness d of the metallization 4 outside of the sub-area 4.2.1 and the metallization 5 is, for example, in the order of magnitude between 0.05 mm and 0.8 mm, the layer thickness D is then e.g. on the order of between 0.1 mm and 1.6 mm.
  • the area under the component 7 is approximately 5mm 2 to 180mm 2 , preferably 9mm 2 to 150mm 2 , which is sufficient for the arrangement of conventional semiconductor components such as power transistors and diodes, in particular also for those semiconductor components which, as integrated semiconductor circuits, consist of a control or switching element and a diode.
  • the device 1 is at least thermally connected to a cooler or a heat sink via the metallization 5, as shown in FIG Figure 1 is indicated with the broken line.
  • the cooler 10 is, for example, a passive cooler that transfers the heat loss to the environment, for example to the surrounding air, via cooling surfaces, for example in the form of cooling fins, or an active cooler through which a cooling medium, for example a liquid cooling medium, can flow Cooling channel formed.
  • connection between the metallization 5 and the cooler 10 is implemented, for example, by gluing, sintering, soldering, DCB bonding.
  • connection between the metallization 5 and the cooler 10 is implemented, for example, by gluing, sintering, soldering, DCB bonding.
  • the described design of the metal insulating layer substrate 2 also has the advantage that the reduced layer thickness of the metallization 4 outside the sub-area 4.2.1 enables fine structuring, in particular of the metallization area 4.1, for the formation of finely structured conductor tracks, contact surfaces, etc. This also makes it possible, in particular, to create complex circuits that have a large number of components, in particular also have active components, together with at least one power component compact, ie to be implemented on a metal insulating layer substrate 2 with small dimensions.
  • the Figure 3 shows in positions a) - c) the steps of a manufacturing method for manufacturing the metal insulating layer substrate 2.
  • a metal layer in the form of a metal foil 4 ' (eg copper or aluminum foil) is first applied to the top of the insulating layer 3 the layer thickness D and on the underside of the insulating layer 3 a metal layer in the form of a metal foil 5 '(for example copper or aluminum foil) with the layer thickness d.
  • the metal foil 4 ' is masked with a lacquer or photoresist or etching resist 11 where the metallization 4 of the finished substrate 2 should have the layer thickness D (position a))
  • the metal foil 4 ′ is then etched away until it then has the layer thickness d corresponding to position b) outside the etching resist 11.
  • the entire surface of the remaining metal foil 4 ' is covered with the etching resist 11, specifically except for those areas where the metallization 4 is not provided, i.e. i.a. except for the spaces between the metallization areas 4.1 and 4.2, so that after another etching and removal of the etching resist 11, the structuring of the metallization 4 is achieved (position c)).
  • the metal foil 5 'forming the metallization 5 and having the layer thickness d is protected during the entire structuring process, for example by covering it with the etching resist 11 or in another suitable manner.
  • the Figure 4 shows in positions a) - c) the steps of a manufacturing process in which metal layers in the form of metal foils 4 'and 5' (e.g. copper or aluminum foil) with the layer thickness d are initially applied to both surface sides of the insulating layer 3 (position a) ).
  • metal layers in the form of metal foils 4 'and 5' e.g. copper or aluminum foil
  • the metal foil 4 ' is structured in the foil area 4a', which forms the metallization area 4.1, and in the foil area 4b '.
  • An additional metal layer 4b ′′ is then applied to the foil area 4b 'in a suitable process, for example by galvanic and / or chemical deposition and / or by thermal spraying and / or in a plasma process, in such a way that the foil area 4b' and of the additional metal layer 4b ′′, the shaping required for the metallization area 4.2 is achieved.
  • the metal of the additional metal layer 4b is, for example, the metal of the metal foil 4 ', for example copper, copper alloy, aluminum or aluminum alloy.
  • a metal different from the metal foil 4' can also be used for the additional metal layer 4b.
  • the additional metal layer 4b ′′ can also be produced by laser sintering using a metallic sintered material as the sintered layer.
  • the metal foil 5 'forming the metallization 5 is in turn protected during the entire process, for example by covering it with a protective layer or in some other way.
  • the Figure 5 shows in items a) - c) the steps of a manufacturing process in which metal layers in the form of metal foils 4 'and 5' (eg copper or aluminum foil) with the layer thickness d are initially applied to both surface sides of the insulating layer 3.
  • the metal foil 4 is then structured into the foil regions 4a 'and 4b', for example by masking and etching (positions a) and b)).
  • the additional metal layer 4b ′′ in the form of a metal plate is applied to the film region 4b ′, which is for example by DIRECT bonding or DCB bonding, by soldering, preferably by brazing with the metal layer 4b 'is connected and so together with the film area 4b' forms the sub-area 4.2.1.
  • the metal plate forming the metal layer 4b ′′ is applied in particular when the metal insulating layer substrate is produced together with a large number of other substrates using a large-format ceramic plate in multiple use, using a mask and / or in which the further metal layer 4b "Forming platelet is part of a molded part produced, for example, by punching from a metal foil, in which the respective platelet is held via at least one web which, after connecting the platelet to the metal layer 4b ', for example mechanically or in some other suitable manner, e.g. Is separated by lasers.
  • the metallization 4 only forms two metallization areas 4.1 and 4.2.
  • the metallization 4 can of course also have several metallization areas 4.1 of a smaller layer thickness and in particular also several metallization areas 4.2 for several power components 7.
  • the electronic device or its metal-insulating layer substrate has only one or more metallization areas 4.2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
EP10744841.7A 2009-07-02 2010-06-29 Elektronische vorrichtung Active EP2449586B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009033029A DE102009033029A1 (de) 2009-07-02 2009-07-02 Elektronische Vorrichtung
PCT/DE2010/000745 WO2011000360A2 (de) 2009-07-02 2010-06-29 Elektronische vorrichtung

Publications (2)

Publication Number Publication Date
EP2449586A2 EP2449586A2 (de) 2012-05-09
EP2449586B1 true EP2449586B1 (de) 2020-10-21

Family

ID=42983560

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10744841.7A Active EP2449586B1 (de) 2009-07-02 2010-06-29 Elektronische vorrichtung

Country Status (7)

Country Link
US (1) US8749052B2 (ja)
EP (1) EP2449586B1 (ja)
JP (1) JP2012531728A (ja)
KR (1) KR20120098575A (ja)
CN (1) CN102484104B (ja)
DE (1) DE102009033029A1 (ja)
WO (1) WO2011000360A2 (ja)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5860599B2 (ja) * 2011-03-01 2016-02-16 昭和電工株式会社 絶縁回路基板、パワーモジュール用ベースおよびその製造方法
US9206418B2 (en) 2011-10-19 2015-12-08 Nugen Technologies, Inc. Compositions and methods for directional nucleic acid amplification and sequencing
DE102012102611B4 (de) * 2012-02-15 2017-07-27 Rogers Germany Gmbh Metall-Keramik-Substrat sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
TW201410085A (zh) * 2012-05-02 2014-03-01 Ceramtec Gmbh 製造具充金屬之通路的陶瓷基材的陶瓷電路板的方法
EP2838325B1 (en) * 2013-08-16 2021-06-16 NGK Insulators, Ltd. Ceramic circuit board and electronic device
WO2015104954A1 (ja) * 2014-01-10 2015-07-16 古河電気工業株式会社 電子回路装置
JP6192561B2 (ja) * 2014-02-17 2017-09-06 三菱電機株式会社 電力用半導体装置
JP6341822B2 (ja) 2014-09-26 2018-06-13 三菱電機株式会社 半導体装置
US11437304B2 (en) 2014-11-06 2022-09-06 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9408301B2 (en) * 2014-11-06 2016-08-02 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9397017B2 (en) 2014-11-06 2016-07-19 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
WO2016163135A1 (ja) * 2015-04-08 2016-10-13 三菱電機株式会社 電子モジュール及び電子装置
JP6370257B2 (ja) 2015-04-27 2018-08-08 三菱電機株式会社 半導体装置
EP3306655B1 (en) * 2015-05-27 2021-06-23 NGK Electronics Devices, Inc. Substrate for power modules, substrate assembly for power modules, and method for producing substrate for power modules
JP6582783B2 (ja) * 2015-09-16 2019-10-02 富士電機株式会社 半導体装置
EP3210957B1 (de) 2016-02-26 2019-01-02 Heraeus Deutschland GmbH & Co. KG Kupfer-keramik-verbund
EP3210956B1 (de) 2016-02-26 2018-04-11 Heraeus Deutschland GmbH & Co. KG Kupfer-keramik-verbund
JP6540587B2 (ja) * 2016-04-28 2019-07-10 三菱電機株式会社 パワーモジュール
JP6687109B2 (ja) * 2016-05-19 2020-04-22 三菱マテリアル株式会社 パワーモジュール用基板
EP3261119A1 (en) * 2016-06-21 2017-12-27 Infineon Technologies AG Power semiconductor module components and additive manufacturing thereof
KR101872257B1 (ko) 2016-06-29 2018-06-28 박남철 마그넷 발전기
KR101872262B1 (ko) 2016-07-06 2018-08-02 박남철 마그넷 발전기
JP7125931B2 (ja) 2017-03-31 2022-08-25 ローム株式会社 パワーモジュールおよびその製造方法
CN108964297A (zh) * 2017-05-17 2018-12-07 德昌电机(深圳)有限公司 一种电机、控制电路板及应用该电机的引擎冷却模组
EP3595002A1 (de) * 2018-07-12 2020-01-15 Heraeus Deutschland GmbH & Co KG Metall-keramik-substrat mit einer zur direkten kühlung geformten folie als substratunterseite
DE102018212272A1 (de) * 2018-07-24 2020-01-30 Robert Bosch Gmbh Keramischer Schaltungsträger und Elektronikeinheit
DE102018123681A1 (de) 2018-09-26 2020-03-26 Rogers Germany Gmbh Trägersubstrat für elektrische, insbesondere elektronische Bauteile und Verfahren zum Herstellen eines Trägersubstrats
JP7147502B2 (ja) 2018-11-19 2022-10-05 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法
DE102019108594A1 (de) 2019-04-02 2020-10-08 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Subtrats und ein solches Metall-Keramik-Substrat.
DE102019113308A1 (de) 2019-05-20 2020-11-26 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und Metall-Keramik- Substrat, hergestellt mit einem solchen Verfahren
US11387373B2 (en) * 2019-07-29 2022-07-12 Nxp Usa, Inc. Low drain-source on resistance semiconductor component and method of fabrication
DE102019126954A1 (de) 2019-10-08 2021-04-08 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats, Lötsystem und Metall-Keramik-Substrat, hergestellt mit einem solchen Verfahren
DE102019135099A1 (de) 2019-12-19 2021-06-24 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und Metall-Keramik-Substrat, hergestellt mit einem solchen Verfahren
DE102019135171A1 (de) 2019-12-19 2021-06-24 Rogers Germany Gmbh Lotmaterial, Verfahren zur Herstellung eines solchen Lotmaterials und Verwendung eines solchen Lotmaterials zur Anbindung einer Metallschicht an eine Keramikschicht
DE102019135097A1 (de) 2019-12-19 2021-06-24 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und Metall-Keramik-Substrat, hergestellt mit einem solchen Verfahren
DE102019135146B4 (de) 2019-12-19 2022-11-24 Rogers Germany Gmbh Metall-Keramik-Substrat
DE102020202607A1 (de) * 2020-02-28 2021-09-02 Siemens Aktiengesellschaft Elektronikmodul, Verfahren zur Herstellung eines Elektronikmoduls und Industrieanlage
DE102020106521A1 (de) 2020-03-10 2021-09-16 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung eines Elektronikmoduls
DE102020111698A1 (de) 2020-04-29 2021-11-04 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und ein Metall-Keramik-Substrat hergestellt mit einem solchen Verfahren
DE102020111700A1 (de) 2020-04-29 2021-11-04 Rogers Germany Gmbh Trägersubstrat und Verfahren zur Herstellung eines Trägersubstrats
DE102020111697A1 (de) 2020-04-29 2021-11-04 Rogers Germany Gmbh Trägersubstrat und Verfahren zur Herstellung eines Trägersubstrats
DE102020112276A1 (de) * 2020-05-06 2021-11-11 Danfoss Silicon Power Gmbh Leistungsmodul
DE102020205979A1 (de) 2020-05-12 2021-11-18 Robert Bosch Gesellschaft mit beschränkter Haftung Leistungsmodul mit einer Wärmesenke
DE102020119209A1 (de) 2020-07-21 2022-01-27 Rogers Germany Gmbh Leistungsmodul und Verfahren zur Herstellung eines Leistungsmoduls
DE102020119208A1 (de) 2020-07-21 2022-01-27 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und Metall-Keramik-Substrat hergestellt mit einem solchen Verfahren
DE102020120188A1 (de) 2020-07-30 2022-02-03 Rogers Germany Gmbh Verfahren zur Herstellung eines Trägersubstrats und ein Trägersubstrat hergestellt mit einem solchen Verfahren
DE102020120189A1 (de) * 2020-07-30 2022-02-03 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und ein Metall-Keramik-Substrat hergestellt mit einem solchen Verfahren
CN115004359A (zh) * 2020-08-28 2022-09-02 富士电机株式会社 半导体装置
DE102021100463A1 (de) 2021-01-13 2022-07-14 Rogers Germany Gmbh Verfahren zum Herstellen eines Metall-Keramik-Substrats und Metall-Keramik-Substrat hergestellt mit einem solchen Verfahren
WO2022162875A1 (ja) * 2021-01-29 2022-08-04 サンケン電気株式会社 半導体パワーモジュール
DE102021107690A1 (de) 2021-03-26 2022-09-29 Rogers Germany Gmbh Verfahren zur Herstellung eines Metall-Keramik-Substrats und Metall-Keramik-Substrat hergestellt mit einem solchen Verfahren
DE102021107872A1 (de) 2021-03-29 2022-09-29 Rogers Germany Gmbh Trägersubstrat für elektrische, insbesondere elektronische Bauteile und Verfahren zum Herstellen eines Trägersubstrats
DE102021125557A1 (de) 2021-10-01 2023-04-06 Rogers Germany Gmbh Metall-Keramik-Substrat und Verfahren zur Herstellung eines Metall-Keramik-Substrats
DE102021126529A1 (de) 2021-10-13 2023-04-13 Rogers Germany Gmbh Verfahren zur Herstellung von Metall-Keramik-Substraten und Metall-Keramik-Substrat, hergestellt mit einem solchen Verfahren
DE102022104156A1 (de) 2022-02-22 2023-08-24 Rogers Germany Gmbh Metall-Keramik-Substrat und Verfahren zur Herstellung eines Metall-Keramik-Substrats
EP4273928A1 (en) * 2022-05-02 2023-11-08 Infineon Technologies AG A semiconductor package comprising power and logic on a single ceramic plate
EP4294135A1 (de) * 2022-06-14 2023-12-20 CeramTec GmbH Metallische struktur als vorprodukt für elektrische schaltungen und verfahren zur herstellung einer elektrischen schaltung
DE102022119688B3 (de) 2022-08-05 2024-02-08 Rogers Germany Gmbh Verfahren zum Herstellen eines Metall-Keramik-Substrats und Anlage für ein solches Verfahren
DE102022122799A1 (de) 2022-09-08 2024-03-14 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung eines solchen Elektronikmoduls
DE102022129493A1 (de) 2022-11-08 2024-05-08 Rogers Germany Gmbh Metall-Keramik-Substrat und Verfahren zur Herstellung von Metall-Keramik-Substraten

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283703A (ja) * 1996-04-18 1997-10-31 Nippon Inter Electronics Corp 複合半導体装置
US20070128772A1 (en) * 2003-04-15 2007-06-07 Denki Kagaku Kogyo Kabushiki Kaisha Metal-base circuit board and its manufacturing method
DE102007014433A1 (de) * 2006-03-23 2007-10-04 Ceramtec Ag Innovative Ceramic Engineering Trägerkörper für Bauelemente oder Schaltungen

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2213115C3 (de) 1972-03-17 1975-12-04 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum hochfesten Verbinden von Keramiken aus Karbiden, einschließlich des Diamanten, Boriden, Nitriden oder Suiziden mit Metall nach dem Trocken-Lötverfahren
US3766634A (en) 1972-04-20 1973-10-23 Gen Electric Method of direct bonding metals to non-metallic substrates
US3744120A (en) 1972-04-20 1973-07-10 Gen Electric Direct bonding of metals with a metal-gas eutectic
JPH0810710B2 (ja) 1984-02-24 1996-01-31 株式会社東芝 良熱伝導性基板の製造方法
DE3922485C1 (ja) 1989-07-08 1990-06-13 Doduco Gmbh + Co Dr. Eugen Duerrwaechter, 7530 Pforzheim, De
EP0525644A1 (en) * 1991-07-24 1993-02-03 Denki Kagaku Kogyo Kabushiki Kaisha Circuit substrate for mounting a semiconductor element
JPH07202063A (ja) * 1993-12-28 1995-08-04 Toshiba Corp セラミックス回路基板
US6232657B1 (en) * 1996-08-20 2001-05-15 Kabushiki Kaisha Toshiba Silicon nitride circuit board and semiconductor module
JP3512977B2 (ja) 1996-08-27 2004-03-31 同和鉱業株式会社 高信頼性半導体用基板
US6207221B1 (en) * 1997-03-01 2001-03-27 Jürgen Schulz-Harder Process for producing a metal-ceramic substrate and a metal-ceramic substrate
US6261703B1 (en) * 1997-05-26 2001-07-17 Sumitomo Electric Industries, Ltd. Copper circuit junction substrate and method of producing the same
JP4756200B2 (ja) * 2000-09-04 2011-08-24 Ｄｏｗａメタルテック株式会社 金属セラミックス回路基板
JP2002203942A (ja) * 2000-12-28 2002-07-19 Fuji Electric Co Ltd パワー半導体モジュール
EP1239515B1 (fr) * 2001-03-08 2019-01-02 ALSTOM Transport Technologies Substrat pour circuit électronique de puissance et module électronique de puissance utilisant un tel substrat
JP2004128510A (ja) * 2002-10-05 2004-04-22 Semikron Elektron Gmbh 向上された絶縁強度を有するパワー半導体モジュール
DE10261402A1 (de) * 2002-12-30 2004-07-15 Schulz-Harder, Jürgen, Dr.-Ing. Wärmesenke in Form einer Heat-Pipe sowie Verfahren zum Herstellen einer solchen Wärmesenke
DE10327530A1 (de) * 2003-06-17 2005-01-20 Electrovac Gesmbh Vorrichtung mit wenigstens einer von einem zu kühlenden Funktionselement gebildeten Wärmequelle, mit wenigstens einer Wärmesenke und mit wenigstens einer Zwischenlage aus einer thermischen leitenden Masse zwischen der Wärmequelle und der Wärmesenke sowie thermische leitende Masse, insbesondere zur Verwendung bei einer solchen Vorrichtung
JP4765110B2 (ja) * 2005-03-31 2011-09-07 Ｄｏｗａメタルテック株式会社 金属−セラミックス接合基板およびその製造方法
JP4595665B2 (ja) * 2005-05-13 2010-12-08 富士電機システムズ株式会社 配線基板の製造方法
DE102005032076B3 (de) * 2005-07-08 2007-02-08 Infineon Technologies Ag Verfahren zum Herstellen eines Schaltungsmoduls

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283703A (ja) * 1996-04-18 1997-10-31 Nippon Inter Electronics Corp 複合半導体装置
US20070128772A1 (en) * 2003-04-15 2007-06-07 Denki Kagaku Kogyo Kabushiki Kaisha Metal-base circuit board and its manufacturing method
DE102007014433A1 (de) * 2006-03-23 2007-10-04 Ceramtec Ag Innovative Ceramic Engineering Trägerkörper für Bauelemente oder Schaltungen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
D.M. SU: "SPEC NO: DSAA9073", 16 April 2009 (2009-04-16), XP055628470, Retrieved from the Internet <URL:http://www.farnell.com/datasheets/513004.pdf> [retrieved on 20191003] *

Also Published As

Publication number Publication date
US20120134115A1 (en) 2012-05-31
CN102484104A (zh) 2012-05-30
CN102484104B (zh) 2016-01-27
EP2449586A2 (de) 2012-05-09
WO2011000360A2 (de) 2011-01-06
JP2012531728A (ja) 2012-12-10
DE102009033029A1 (de) 2011-01-05
US8749052B2 (en) 2014-06-10
KR20120098575A (ko) 2012-09-05
WO2011000360A3 (de) 2011-03-17

Similar Documents

Publication Publication Date Title
EP2449586B1 (de) Elektronische vorrichtung
EP2132772A2 (de) Wärmesenke sowie bau- oder moduleinheit mit einer wärmesenke
EP3559989B1 (de) Trägersubstrat für elektrische bauteile und verfahren zur herstellung eines trägersubstrats
DE102006009159A1 (de) Verfahren zum Herstellen eines Verbundsubstrates sowie Verbundsubstrat
DE102012103786B4 (de) Metall-Keramik-Substrat sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
DE102012102090A1 (de) Thermoelektrisches Generatormodul, Metall-Keramik-Substrat sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
EP1514459B1 (de) Metall-keramik-substrat für elektische schaltkreise- oder module, verfahren zum herstellen eines solchen substrates sowie modul mit einem solchen substrat
DE102013102540B4 (de) Metall-Keramik-Substrat, Modulanordnung sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
DE102013105528A1 (de) Metall-Keramik-Substrat sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
DE102015114521B4 (de) Verfahren zum Auflöten eines Isoliersubstrats auf einen Träger
DE19956565A1 (de) Verfahren zum Herstellen einer Wärmesenke für elektrische Bauelemente sowie Wärmesenke oder Kühler für elektrische Bauelemente
DE102004058806B4 (de) Verfahren zur Herstellung von Schaltungsstrukturen auf einem Kühlkörper und Schaltungsstruktur auf einem Kühlkörper
DE19614501C2 (de) Verfahren zum Herstellen eines Keramik-Metall-Substrates sowie Keramik-Metall-Substrat
DE102006011743A1 (de) Verfahren zum Herstellen von Peltier-Modulen sowie Peltier-Modul
EP0862209B1 (de) Verfahren zum Herstellen eines Metall-Keramik-Substrates
DE10229711B4 (de) Halbleitermodul mit Mikrokühler
EP3682474B1 (de) Verbund aus mehreren adapterelementen und verfahren zur herstellung eines solchen verbunds
DE102012104903B4 (de) Verfahren zum Herstellen von Metall-Keramik-Substraten sowie nach diesem Verfahren hergestelltes Metall-Keramik-Substrat
DE10301682B4 (de) Temperaturbelastbarer Shunt-Widerstand und Verfahren zur Herstellung eines solchen Shunt-Widerstandes
EP4073837B1 (de) Elektronikmodul, verfahren zur herstellung eines elektronikmoduls und industrieanlage
EP1515595B1 (de) Schaltungsträger
EP3901996A2 (de) Verfahren zur verbindung von komponenten bei der herstellung leistungselektronischer module oder baugruppen mit direktem bonden glatter metallischer oberflächenschichten sowie entsprechendes leistungselektronsiches modul und entsprechende leistungselektronische baugruppe
EP3595002A1 (de) Metall-keramik-substrat mit einer zur direkten kühlung geformten folie als substratunterseite
WO2020233987A1 (de) Adapterelement zum anbinden eines elektronikbauteils an ein kühlkörperelement, system mit einem solchen adapterelement und verfahren zum herstellen eines solchen adapterelements
DE102015115133B3 (de) Verfahren zum Verbinden eines Kühlkörpers mit wenigstens einem Schaltungsträger durch Aufschrumpfen

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20111214

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20140324

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ROGERS GERMANY GMBH

TPAC Observations filed by third parties

Free format text: ORIGINAL CODE: EPIDOSNTIPA

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

TPAC Observations filed by third parties

Free format text: ORIGINAL CODE: EPIDOSNTIPA

TPAC Observations filed by third parties

Free format text: ORIGINAL CODE: EPIDOSNTIPA

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20200528

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 502010016781

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1326726

Country of ref document: AT

Kind code of ref document: T

Effective date: 20201115

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20201021

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210222

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210121

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210122

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210121

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210221

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502010016781

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

26N No opposition filed

Effective date: 20210722

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20210629

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20210630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210629

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210630

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210629

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210629

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210221

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210630

REG Reference to a national code

Ref country code: AT

Ref legal event code: MM01

Ref document number: 1326726

Country of ref document: AT

Kind code of ref document: T

Effective date: 20210629

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210629

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20100629

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230503

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20230320

Year of fee payment: 14

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201021