EP2449586B1 - Elektronische vorrichtung - Google Patents

Elektronische vorrichtung Download PDF

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Publication number
EP2449586B1
EP2449586B1 EP10744841.7A EP10744841A EP2449586B1 EP 2449586 B1 EP2449586 B1 EP 2449586B1 EP 10744841 A EP10744841 A EP 10744841A EP 2449586 B1 EP2449586 B1 EP 2449586B1
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EP
European Patent Office
Prior art keywords
metallization
layer thickness
region
metal
layer
Prior art date
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Active
Application number
EP10744841.7A
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German (de)
English (en)
French (fr)
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EP2449586A2 (de
Inventor
Jürgen SCHULZ-HARDER
Andreas Meyer
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Rogers Germany GmbH
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Rogers Germany GmbH
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Publication of EP2449586B1 publication Critical patent/EP2449586B1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact

Definitions

  • the invention relates to electronic devices or to electronic circuits and / or a module according to the preamble of patent claim 1.
  • DCB process Direct Copper Bond Technology
  • metal layers or sheets for example copper sheets or foils
  • ceramic or ceramic layers specifically using metal - or copper sheets or metal or copper foils which have a layer or a coating (melting layer) made of a chemical compound of the metal and a reactive gas, preferably oxygen, on their surface sides.
  • this layer or this coating (melting layer) forms a eutectic with a melting temperature below the melting temperature of the metal (e.g. copper), so that by placing the foil on the ceramic and heating all the layers, these can be bonded to one another, namely by melting of the metal or copper essentially only in the area of the melted layer or oxide layer.
  • the so-called active soldering process is also known ( DE 22 13 1 15 ; EP-A-153 618 )
  • active soldering process for connecting metal layers or metal foils which form metallizations, in particular also copper layers or copper foils with ceramic material.
  • this method which is also used specifically for the production of metal-ceramic substrates, a connection between a metal foil, for example copper foil, and a ceramic substrate, for example aluminum nitride ceramic, is used at a temperature between approx. 800-1000 ° C
  • a hard solder is produced which, in addition to a main component such as copper, silver and / or gold, also contains an active metal.
  • This active metal which is, for example, at least one element from the group Hf, Ti, Zr, Nb, Ce, creates a connection between the solder and the ceramic by chemical reaction, while the connection between the solder and the metal is a metallic hard solder connection .
  • a copper-ceramic substrate is known, an intermediate layer being arranged between the ceramic support and a copper layer.
  • the intermediate layer protrudes in sections from the intermediate layer.
  • the DE 697 30 388 T2 describes a printed circuit board with a three-stage structure of the metallization.
  • the JP 9 283 703 discloses a metal-ceramic substrate with a metallization that has a stepped profile.
  • the object of the invention is to show electronic devices which, with regard to the cooling of power components, ie components that also generate considerable power loss and thus high heat during operation, are optimized. To achieve this object, electronic devices are designed in accordance with claim 1.
  • the inventive design takes into account not only optimal cooling of power components in electronic devices, circuits or modules, but also the increase in the reliability and service life of such devices, namely by the fact that the special design of the at least one power component carrying the first Metallization area this acts as a heat spreader that optimizes the cooling effect, but at the same time the volume of the metallic material in this metallization area is reduced to such an extent that temperature changes that occur during operation of a device, for example when switching loads, do not destroy the substrate and / or the components through thermally induced mechanical forces. Further developments of the invention are the subject of the subclaims.
  • the electronic device generally designated 1 in the figures consists essentially of a metal insulating layer substrate 2 with a preferably ceramic insulating layer 3, on the surface side of which a metallization 4 or 5 is provided.
  • the upper metallization 4 is structured, as shown in FIG Figure 1 is indicated with the two metallization areas 4.1 and 4.2.
  • the lower metallization 5 is formed continuously, ie it extends up to a free edge area Over the entire lower surface side of the insulating layer 3.
  • Suitable ceramics for the insulating layer 3 consist, for example, of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4) and / or silicon carbide (SiC) or of aluminum oxide and zirconium oxide (Al2O3 + ZrO2).
  • the thickness of the insulating layer 3 is in the order of magnitude between approximately 0.15 mm and 1 mm.
  • Suitable materials for the metallizations 4 and 5 or for the metallization areas 4.1 and 4.2 of the metallization 4 are, for example, copper, copper alloys or aluminum, aluminum alloys.
  • the metallizations 4 and 5 or, according to the invention, the metallization regions 4.1 and 4.2 are connected to the insulating layer 3 by DCB bonding.
  • the component 7 is a power component, for example a power semiconductor component or chip (IC), e.g. Transistor, diode, triac thyristor, etc. with increased power loss and with increased cooling requirement, while component 6 is such a low power and thus also low power loss, for example a semiconductor circuit or chip (IC) for driving component 7.
  • IC power semiconductor component or chip
  • a special feature of the device 1 or the metal insulating layer substrate 2 is that, according to the invention, the structured metallization 4 is essentially only in a sub-area 4.2.1 below the respective power component 7, ie in the embodiment shown below the component 7 has increased layer thickness D, otherwise the layer thickness d of the metallization 4 and its metallization areas 4.1 and 4.2, also of the sub-area 4.2.2, is significantly reduced and, according to the invention, is approximately equal to the layer thickness d of the lower metallization 5.
  • the metallization area 4.2 can thus be described in terms of its shape in such a way that, according to the invention, it consists of the sub-area 4.2.1 with the layer thickness D and the area surrounding it There is partial or edge area 4.2.2 with a smaller layer thickness d, the metallization area 4.2 according to the invention being designed in one piece or monolithically with these partial areas.
  • the metallization area 4.2 is designed step-shaped at its edge 8, namely in such a way that the component 7 from the edge of the uppermost step or from the edge of the sub-area 4.2.1 has a distance a1 which is at least equal to or slightly greater than the difference b of the layer thicknesses D and d, ie a1 ⁇ b.
  • the width a2 of the step formed by the stepped edge 8 is at least equal to the layer thickness d.
  • This formation or shaping of the metallization area 4.2 ensures that it can act in an optimal manner as a heat spreader for optimal cooling of the component 7, as shown in FIG Figure 2 is indicated by the broken lines 9, which run at an angle of 45 ° with respect to the plane of the surface sides of the insulating layer 3 or of the metal-insulating layer substrate 2.
  • this configuration sets the metal volume of the metallization area 4.2 and thus also the mechanical stresses between the metallization 4 or the metallization area 4.2 and the insulating layer 3 caused by temperature changes to a value that does not impair the service life of the device 1.
  • the layer thicknesses d and D that the layer thickness, in particular of the metallization 4 outside the power component 7, is selected so that a sufficiently large cross section is achieved for the conductor tracks generated by the structuring of the metallization 4 or for the currents to be expected, while the layer thickness D of the metallization 4 below the power component 7 is chosen to be sufficiently large for optimal cooling and, in particular, for optimal heat spread.
  • the layer thicknesses D and d are chosen so that their difference b is equal to or greater than d / 2.
  • the relationship applies that the sum of the distances a1 and a2 is at least equal, but preferably is greater than the layer thickness D that the metallization area 4.2 has under the component 7, that is, a1 + a2> D.
  • the layer thickness d of the metallization 4 outside of the sub-area 4.2.1 and the metallization 5 is, for example, in the order of magnitude between 0.05 mm and 0.8 mm, the layer thickness D is then e.g. on the order of between 0.1 mm and 1.6 mm.
  • the area under the component 7 is approximately 5mm 2 to 180mm 2 , preferably 9mm 2 to 150mm 2 , which is sufficient for the arrangement of conventional semiconductor components such as power transistors and diodes, in particular also for those semiconductor components which, as integrated semiconductor circuits, consist of a control or switching element and a diode.
  • the device 1 is at least thermally connected to a cooler or a heat sink via the metallization 5, as shown in FIG Figure 1 is indicated with the broken line.
  • the cooler 10 is, for example, a passive cooler that transfers the heat loss to the environment, for example to the surrounding air, via cooling surfaces, for example in the form of cooling fins, or an active cooler through which a cooling medium, for example a liquid cooling medium, can flow Cooling channel formed.
  • connection between the metallization 5 and the cooler 10 is implemented, for example, by gluing, sintering, soldering, DCB bonding.
  • connection between the metallization 5 and the cooler 10 is implemented, for example, by gluing, sintering, soldering, DCB bonding.
  • the described design of the metal insulating layer substrate 2 also has the advantage that the reduced layer thickness of the metallization 4 outside the sub-area 4.2.1 enables fine structuring, in particular of the metallization area 4.1, for the formation of finely structured conductor tracks, contact surfaces, etc. This also makes it possible, in particular, to create complex circuits that have a large number of components, in particular also have active components, together with at least one power component compact, ie to be implemented on a metal insulating layer substrate 2 with small dimensions.
  • the Figure 3 shows in positions a) - c) the steps of a manufacturing method for manufacturing the metal insulating layer substrate 2.
  • a metal layer in the form of a metal foil 4 ' (eg copper or aluminum foil) is first applied to the top of the insulating layer 3 the layer thickness D and on the underside of the insulating layer 3 a metal layer in the form of a metal foil 5 '(for example copper or aluminum foil) with the layer thickness d.
  • the metal foil 4 ' is masked with a lacquer or photoresist or etching resist 11 where the metallization 4 of the finished substrate 2 should have the layer thickness D (position a))
  • the metal foil 4 ′ is then etched away until it then has the layer thickness d corresponding to position b) outside the etching resist 11.
  • the entire surface of the remaining metal foil 4 ' is covered with the etching resist 11, specifically except for those areas where the metallization 4 is not provided, i.e. i.a. except for the spaces between the metallization areas 4.1 and 4.2, so that after another etching and removal of the etching resist 11, the structuring of the metallization 4 is achieved (position c)).
  • the metal foil 5 'forming the metallization 5 and having the layer thickness d is protected during the entire structuring process, for example by covering it with the etching resist 11 or in another suitable manner.
  • the Figure 4 shows in positions a) - c) the steps of a manufacturing process in which metal layers in the form of metal foils 4 'and 5' (e.g. copper or aluminum foil) with the layer thickness d are initially applied to both surface sides of the insulating layer 3 (position a) ).
  • metal layers in the form of metal foils 4 'and 5' e.g. copper or aluminum foil
  • the metal foil 4 ' is structured in the foil area 4a', which forms the metallization area 4.1, and in the foil area 4b '.
  • An additional metal layer 4b ′′ is then applied to the foil area 4b 'in a suitable process, for example by galvanic and / or chemical deposition and / or by thermal spraying and / or in a plasma process, in such a way that the foil area 4b' and of the additional metal layer 4b ′′, the shaping required for the metallization area 4.2 is achieved.
  • the metal of the additional metal layer 4b is, for example, the metal of the metal foil 4 ', for example copper, copper alloy, aluminum or aluminum alloy.
  • a metal different from the metal foil 4' can also be used for the additional metal layer 4b.
  • the additional metal layer 4b ′′ can also be produced by laser sintering using a metallic sintered material as the sintered layer.
  • the metal foil 5 'forming the metallization 5 is in turn protected during the entire process, for example by covering it with a protective layer or in some other way.
  • the Figure 5 shows in items a) - c) the steps of a manufacturing process in which metal layers in the form of metal foils 4 'and 5' (eg copper or aluminum foil) with the layer thickness d are initially applied to both surface sides of the insulating layer 3.
  • the metal foil 4 is then structured into the foil regions 4a 'and 4b', for example by masking and etching (positions a) and b)).
  • the additional metal layer 4b ′′ in the form of a metal plate is applied to the film region 4b ′, which is for example by DIRECT bonding or DCB bonding, by soldering, preferably by brazing with the metal layer 4b 'is connected and so together with the film area 4b' forms the sub-area 4.2.1.
  • the metal plate forming the metal layer 4b ′′ is applied in particular when the metal insulating layer substrate is produced together with a large number of other substrates using a large-format ceramic plate in multiple use, using a mask and / or in which the further metal layer 4b "Forming platelet is part of a molded part produced, for example, by punching from a metal foil, in which the respective platelet is held via at least one web which, after connecting the platelet to the metal layer 4b ', for example mechanically or in some other suitable manner, e.g. Is separated by lasers.
  • the metallization 4 only forms two metallization areas 4.1 and 4.2.
  • the metallization 4 can of course also have several metallization areas 4.1 of a smaller layer thickness and in particular also several metallization areas 4.2 for several power components 7.
  • the electronic device or its metal-insulating layer substrate has only one or more metallization areas 4.2.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
EP10744841.7A 2009-07-02 2010-06-29 Elektronische vorrichtung Active EP2449586B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009033029A DE102009033029A1 (de) 2009-07-02 2009-07-02 Elektronische Vorrichtung
PCT/DE2010/000745 WO2011000360A2 (de) 2009-07-02 2010-06-29 Elektronische vorrichtung

Publications (2)

Publication Number Publication Date
EP2449586A2 EP2449586A2 (de) 2012-05-09
EP2449586B1 true EP2449586B1 (de) 2020-10-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP10744841.7A Active EP2449586B1 (de) 2009-07-02 2010-06-29 Elektronische vorrichtung

Country Status (7)

Country Link
US (1) US8749052B2 (ja)
EP (1) EP2449586B1 (ja)
JP (1) JP2012531728A (ja)
KR (1) KR20120098575A (ja)
CN (1) CN102484104B (ja)
DE (1) DE102009033029A1 (ja)
WO (1) WO2011000360A2 (ja)

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WO2011000360A3 (de) 2011-03-17
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DE102009033029A1 (de) 2011-01-05
JP2012531728A (ja) 2012-12-10
WO2011000360A2 (de) 2011-01-06
US20120134115A1 (en) 2012-05-31
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US8749052B2 (en) 2014-06-10
CN102484104A (zh) 2012-05-30

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