EP2243159A2 - Procédé de frittage sous pression à basse température - Google Patents
Procédé de frittage sous pression à basse températureInfo
- Publication number
- EP2243159A2 EP2243159A2 EP09709504A EP09709504A EP2243159A2 EP 2243159 A2 EP2243159 A2 EP 2243159A2 EP 09709504 A EP09709504 A EP 09709504A EP 09709504 A EP09709504 A EP 09709504A EP 2243159 A2 EP2243159 A2 EP 2243159A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- heat sink
- sink plate
- substrate
- pressure sintering
- sintering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000005245 sintering Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 37
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052709 silver Inorganic materials 0.000 claims abstract description 8
- 239000004332 silver Substances 0.000 claims abstract description 8
- 238000005516 engineering process Methods 0.000 claims abstract description 5
- 239000011159 matrix material Substances 0.000 claims abstract 2
- 230000000712 assembly Effects 0.000 claims description 10
- 238000000429 assembly Methods 0.000 claims description 10
- 238000001816 cooling Methods 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000003892 spreading Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000000748 compression moulding Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000005253 cladding Methods 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000462 isostatic pressing Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Definitions
- the invention relates to a method for pressure sintering.
- Electronic assemblies of power electronics with one or more semiconductor devices are typically fabricated by means of bonds, soldering or the silver pressure sintering technique of the unprotected semiconductor on a primary circuit substrate.
- ceramic circuit carriers are preferably used
- DCB substrates or direct copper bonded substrates
- the substrates consist of a core of alumina or aluminum nitride with expansion coefficients of 7-8ppm / K and about 4 ppm / K.
- the substrate may also be a purely ceramic solution in the form of thick-film hybrid supports of aluminum oxide or aluminum nitride with metallized or mounted conductor tracks.
- a direct mounting of one or more semiconductors on a metal stamped grid can be carried out as a circuit carrier.
- US 2004-026778 A1 shows the direct mounting of the semiconductor on sections of the stamped grid without an insulating substrate.
- the semiconductors are electrically connected to one another and to the metallic conductor tracks of the substrate or to the stamped grid.
- the assembled substrate or the lead frame is usually constructed with a bonding layer (gluing, pressure contact with thermal paste, soldering or pressure sintering) on a heat sink plate (eg utility model of the applicant 200 05 746 Ul).
- a bonding layer glue, pressure contact with thermal paste, soldering or pressure sintering
- a heat sink plate eg utility model of the applicant 200 05 746 Ul.
- multiple substrate assemblies in series and parallel
- the heat sink plate ensures optimum energy buffering with the heat capacity of the selected material (preferably copper).
- the heat sink plate reduces the dynamic thermal resistance (Zth).
- the thermal conductivity of the heat spreader plate is decisive and its dimension enlarged compared to the substrate. This leads to an advantageous thermal resistance (Rth).
- thermosetting plastic To achieve high electrical insulation between the potential-carrying components (bonding wires, semiconductors and printed conductors) and achieve very high mechanical strength or robustness, there are products in which the assembly are coated with a thermosetting plastic.
- This production technique consists of filling the module body in a full volume by means of transfer molding with a duroplastic hard glassy polymer material (for example Henkel Loctite Hysol). This is done with individual semiconductor components (for example in TO 220 package forms from ST-Microelectronics IRF-540) and with transistor groups, e.g. US 2005/0067719 Al.
- Assemblies can be mounted on a common heat sink plate.
- The- This cost-saving production and test step is not possible during assembly by means of silver pressure sintering, because the quasi-isostatic pressing of the assembly during the sintering process would destroy the bonding wires of the electrically wired assembly.
- the pretested substrate assemblies be first of all formed into a robust, mechanically loadable assembly (mold module) by compression molding in the manner described.
- Such a compression molded assembly may be uniaxial or quasi-isostatic
- Presses are connected by pressure sintering with a heat sink plate by silver-sintering. In this structure, therefore, only well-tested substrate assemblies are processed.
- This sintering process can be carried out with at least one module module, but can also be carried out simultaneously with several module modules on only one heat sink plate.
- Disadvantage 2 Deformation of the coated assembly with integrated heat sink plate due to large expansion differences
- the described process of compression molding has the disadvantage for the entire assembly that a renewed heating to about 170 ° C-200 ° C is made (thermal activation of the polymer cross-linking).
- the already connected stack consisting of the materials heat sink plate, connecting layer, substrate, connecting layer and semiconductor, deforms according to their individual thermal expansion coefficients.
- the layer adhesions and shear strengths of the bonding layers ensure a permanent superimposed overall deformation.
- the preferred heat sink material is copper, and the high coefficient of thermal expansion of the copper (18 ppm / K) results in hollow deformation of the stack of material over a flat heat sink surface onto which the final assembly is assembled at the end user.
- Heat sink plates fulfill their function among other things by heat spreading and material-dependent, also the increase of the total heat capacity.
- the heat sink plate must occupy a larger area than the substrate plate connected thereto.
- a thermoset wrapping must be made
- the heat sink plate in a robust wall thickness include, so that the heat sink plate appears flush on one side of the enclosure.
- the costs of the thermosetting molding compound are relatively high, so that the thermally required size of the heat sink plate is generally inadmissibly reduced.
- the heat spreader plates are mounted by adhesive layer.
- Heat sink plates are sometimes also externally mounted by means of thermal paste below substrate modules (molded or frame-based).
- this form-fitting assembly is disadvantageous because of the low thermal conductivity of pastes (1-5 W / mK) and the long-term stability of the pastes and their function (pump out effect).
- the process chain of production is changed so that the electronic assembly without the heat sink plate (and without sintering connection layer to the heat sink plate) is molded with the thermosetting coating mass.
- the coefficient of expansion of the mold cladding mass now exclusively adapted to the thermally dominant ceramic substrate (4 to 6 ppm / K) and is now well below the thermal expansion coefficient of the heat sink plate, for example made of copper (18 ppm / K).
- thermoset A deformation due to mismatch of the thermoset and the assembled substrate is no longer available.
- the volume of the coated substrate is significantly lower and the material and energy consumption is correspondingly more economical and ecological (compare FIGS. 1a, 1b with FIGS. 2a, 2b).
- a heat sink plate can be equipped in a sintering with a plurality of electrically sheathed individually wrapped assemblies.
- 1a shows the integration of the heat sink plate according to the prior art in the formumhüllten body, with the disadvantage that the volume is large compared to the externally mounted heat sink plate and the heat sink plate has no more spreading function
- FIG. 1b is that of FIG. 1a, but viewed from the side of the heat sink plate, FIG.
- FIG. 2a shows an external cohesive mounting of the heat sink plate to the finished molded body, with the advantage that the duroplastic volume is small compared to the volume in FIG. 1 and the connecting layer is a thermally highly conductive sintered silver layer
- FIG. 2b shows an external cohesive mounting of the areal enlarged heat sink plate to the finished molded body, with the advantages that the duroplastic volume is small compared to the volume in FIG. 1, the connecting layer is a thermally highly conductive sintered silver layer, the heat spread is further optimized (compared to FIG ) and a simple mounting option to a heat sink by eg screws (given,
- FIG. 3 shows an external cohesive mounting of the area-enlarged ones
- Heat sink plate to the completed formumhüllten body with the additional advantages that the heat spreader is segmented and the small absolute size and the absolute expansion differences can be kept smaller. Greater differences in elongation mean smaller shear stresses and thus also longer service life compared to alternating temperature loads.
- FIG. 4 shows an external cohesive mounting of the surface-enlarged heat sink plate of a plurality of mold-enveloped bodies
- FIG. 5 a the heat sink plate of Figure 4 supplemented by surface-expanding structures such as fins or - shown - pins for air cooling, and
- the heat sink plate is now in another connection process, namely the silver sintered press technology, with dm completed formumhüllten body of the electronic assembly cohesively (and long-term stable) connected ( Figure 2a, 2b).
- the bonding layer of the sintered silver typically has a thermal conductivity of approx. 250 WVmK and is thus far superior to any thermal compound and to every adhesive and solder, both thermally and mechanically.
- the heat sink plate can be chosen in sufficient size, ie at least identical to the substrate size (primary function, high heat capacity) or identical to the molded body, or preferably also larger than the molded body (heat spreading and increasing the heat capacity).
- the pressure sintering technology combines temperature and pressure.
- the heat sink plate springs in the radius of the lower punch; connects via the bonding layer with the substrate and takes after cooling the final shape.
- the desired crowned shape can now be targeted influenced by the radius of the lower punch of the pressure sintering press.
- the arrangement can be optimized with the following improvement measures:
- the surface extending beyond the body may be provided with holes for mounting screws.
- the heat sink below a substrate plate may be segmented.
- a partial heat sink which in each case should be dimensioned at least identically large with the area requirement of the component, should be dimensioned.
- the individual partial heat sinks have smaller diagonals than the complete heat sink plate unsegmentiert.
- the smaller heat sink plate diagonal of the sub-plates have smaller shear stresses (due to low absolute thermal expansion di- tion) with respect to the substrate and this leads to a greater thermal shock resistance than can be achieved with a complete plate.
- the heat sink plate is a tube or a cooling-optimized hollow body, which can be flowed through by a cooling medium and in this way increases the cooling power.
- the cavity of the body may need to be prevented from deforming by a removable support body (e.g., square bar in square tubing) during the pressure sintering process.
- the heat sink body can be surrounded on several plan sides, preferably on the opposite surfaces with formumhumten assemblies according to the pressure sintering principle.
- a square tube on two opposite sides carry power modules.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008009510A DE102008009510B3 (de) | 2008-02-15 | 2008-02-15 | Verfahren zum Niedertemperatur-Drucksintern |
PCT/DE2009/000050 WO2009100698A2 (fr) | 2008-02-15 | 2009-01-16 | Procédé de frittage sous pression à basse température |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2243159A2 true EP2243159A2 (fr) | 2010-10-27 |
Family
ID=40651328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP09709504A Withdrawn EP2243159A2 (fr) | 2008-02-15 | 2009-01-16 | Procédé de frittage sous pression à basse température |
Country Status (5)
Country | Link |
---|---|
US (1) | US8118211B2 (fr) |
EP (1) | EP2243159A2 (fr) |
CN (1) | CN101952960B (fr) |
DE (1) | DE102008009510B3 (fr) |
WO (1) | WO2009100698A2 (fr) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5996435B2 (ja) * | 2010-11-22 | 2016-09-21 | 株式会社東芝 | 半導体モジュールおよび半導体モジュールの製造方法 |
DE102011076774A1 (de) * | 2011-05-31 | 2012-12-06 | Continental Automotive Gmbh | Baugruppe mit einem Träger und einem Kühlkörper |
DE102012208767A1 (de) * | 2011-06-17 | 2012-12-20 | Robert Bosch Gmbh | Elektronische Schaltungsanordnung mit Verlustwärme abgebenden Komponenten |
DE102011083911A1 (de) | 2011-09-30 | 2013-04-04 | Robert Bosch Gmbh | Elektronische Baugruppe mit hochtemperaturstabilem Substratgrundwerkstoff |
DE102012216401A1 (de) * | 2012-09-14 | 2014-04-10 | Powersem GmbH | Halbleiterbauelement |
US9295184B2 (en) * | 2012-12-14 | 2016-03-22 | GM Global Technology Operations LLC | Scalable and modular approach for power electronic building block design in automotive applications |
DE102013220591A1 (de) * | 2013-10-11 | 2015-04-16 | Robert Bosch Gmbh | Leistungsmodul mit Kühlkörper |
CN104867918A (zh) * | 2014-02-26 | 2015-08-26 | 西安永电电气有限责任公司 | 塑封式ipm模块及其dbc板的固定结构 |
DE102014114093B4 (de) | 2014-09-29 | 2017-03-23 | Danfoss Silicon Power Gmbh | Verfahren zum Niedertemperatur-Drucksintern |
DE102014114096A1 (de) | 2014-09-29 | 2016-03-31 | Danfoss Silicon Power Gmbh | Sinterwerkzeug für den Unterstempel einer Sintervorrichtung |
DE102014114097B4 (de) | 2014-09-29 | 2017-06-01 | Danfoss Silicon Power Gmbh | Sinterwerkzeug und Verfahren zum Sintern einer elektronischen Baugruppe |
DE102014114095B4 (de) | 2014-09-29 | 2017-03-23 | Danfoss Silicon Power Gmbh | Sintervorrichtung |
DE102016107287A1 (de) * | 2016-04-20 | 2017-11-09 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitereinrichtung und Verfahren zum Betrieb einer Leistungshalbleitereinrichtung |
DE102019204683A1 (de) * | 2019-04-02 | 2020-10-08 | Volkswagen Aktiengesellschaft | Verfahren und Vorrichtung zum stoffschlüssigen Verbinden mindestens eines Halbleitermoduls mit mindestens einem Gehäuseteil eines Kühlmoduls |
JP7486234B2 (ja) | 2020-05-15 | 2024-05-17 | ピンク ゲーエムベーハー テルモジステーメ | 電子アセンブリを接続するためのシステム |
CN114608311A (zh) * | 2022-01-24 | 2022-06-10 | 快克智能装备股份有限公司 | 烧结设备及其气氛可控的压力烧结机构 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3780795A (en) * | 1972-06-19 | 1973-12-25 | Rca Corp | Multilayer heat sink |
EP0275433B1 (fr) * | 1986-12-22 | 1992-04-01 | Siemens Aktiengesellschaft | Procédé pour fixer des composants électroniques sur un substrat, feuille pour réaliser le procédé et procédé pour la fabrication de la feuille |
EP0460286A3 (en) * | 1990-06-06 | 1992-02-26 | Siemens Aktiengesellschaft | Method and arrangement for bonding a semiconductor component to a substrate or for finishing a semiconductor/substrate connection by contactless pressing |
DE4233073A1 (de) * | 1992-10-01 | 1994-04-07 | Siemens Ag | Verfahren zum Herstellen eines Halbleiter-Modulaufbaus |
EP0693776B1 (fr) * | 1994-07-15 | 2000-05-31 | Mitsubishi Materials Corporation | Emballage céramique à haute radiation de chaleur |
US5786635A (en) * | 1996-12-16 | 1998-07-28 | International Business Machines Corporation | Electronic package with compressible heatsink structure |
US6324069B1 (en) * | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
US6784541B2 (en) * | 2000-01-27 | 2004-08-31 | Hitachi, Ltd. | Semiconductor module and mounting method for same |
JP3526788B2 (ja) * | 1999-07-01 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置の製造方法 |
JP3919398B2 (ja) * | 1999-10-27 | 2007-05-23 | 三菱電機株式会社 | 半導体モジュール |
DE10101086B4 (de) * | 2000-01-12 | 2007-11-08 | International Rectifier Corp., El Segundo | Leistungs-Moduleinheit |
DE20005746U1 (de) * | 2000-03-28 | 2000-08-03 | Danfoss Silicon Power Gmbh | Leistungshalbleitermodul |
DE10016129A1 (de) * | 2000-03-31 | 2001-10-18 | Siemens Ag | Verfahren zum Herstellen einer wärmeleitenden Verbindung zwischen zwei Werkstücken |
DE10062108B4 (de) | 2000-12-13 | 2010-04-15 | Infineon Technologies Ag | Leistungsmodul mit verbessertem transienten Wärmewiderstand |
DE10200372A1 (de) | 2002-01-08 | 2003-07-24 | Siemens Ag | Leistungshalbleitermodul |
JP2005109100A (ja) * | 2003-09-30 | 2005-04-21 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
DE102004019567B3 (de) * | 2004-04-22 | 2006-01-12 | Semikron Elektronik Gmbh & Co. Kg | Verfahren zur Befestigung von elektronischen Bauelementen auf einem Substrat |
US7205177B2 (en) * | 2004-07-01 | 2007-04-17 | Interuniversitair Microelektronica Centrum (Imec) | Methods of bonding two semiconductor devices |
EP1950767B1 (fr) * | 2005-09-21 | 2012-08-22 | Nihon Handa Co., Ltd. | Composition particulaire d'argent pateuse, processus de production d'argent massif, argent massif, procede d'assemblage, et processus de production d'une carte imprimee |
DE102005061772B4 (de) | 2005-12-23 | 2017-09-07 | Danfoss Silicon Power Gmbh | Leistungshalbleitermodul |
DE102005061773B3 (de) * | 2005-12-23 | 2007-05-16 | Danfoss Silicon Power Gmbh | Verfahren zum Herstellen eines Leistungshalbleitermoduls und Leistungshalbleitermodul |
DE102006009159A1 (de) | 2006-02-21 | 2007-08-23 | Curamik Electronics Gmbh | Verfahren zum Herstellen eines Verbundsubstrates sowie Verbundsubstrat |
US7821130B2 (en) * | 2008-03-31 | 2010-10-26 | Infineon Technologies Ag | Module including a rough solder joint |
-
2008
- 2008-02-15 DE DE102008009510A patent/DE102008009510B3/de active Active
-
2009
- 2009-01-16 US US12/866,121 patent/US8118211B2/en active Active
- 2009-01-16 CN CN2009801051597A patent/CN101952960B/zh active Active
- 2009-01-16 EP EP09709504A patent/EP2243159A2/fr not_active Withdrawn
- 2009-01-16 WO PCT/DE2009/000050 patent/WO2009100698A2/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CN101952960B (zh) | 2012-07-11 |
CN101952960A (zh) | 2011-01-19 |
WO2009100698A2 (fr) | 2009-08-20 |
US8118211B2 (en) | 2012-02-21 |
DE102008009510B3 (de) | 2009-07-16 |
US20110017808A1 (en) | 2011-01-27 |
WO2009100698A3 (fr) | 2009-12-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2243159A2 (fr) | Procédé de frittage sous pression à basse température | |
DE102009002191B4 (de) | Leistungshalbleitermodul, Leistungshalbleitermodulanordnung und Verfahren zur Herstellung einer Leistungshalbleitermodulanordnung | |
DE102007057533B4 (de) | Kühlkörper, Verfahren zur Herstellung eines Kühlkörpers und Leiterplatte mit Kühlkörper | |
DE102009055648B4 (de) | Leistungshalbleitermodul | |
DE10022726A1 (de) | Thermoelektrisches Modul mit verbessertem Wärmeübertragungsvermögen und Verfahren zum Herstellen desselben | |
DE102006008807B4 (de) | Anordnung mit einem Leistungshalbleitermodul und einem Kühlbauteil | |
EP2019429A1 (fr) | Module doté d'un composant électronique connecté électriquement entre deux substrats, en particulier des substrats de céramique DCB, et son procédé de fabrication | |
CN102984889B (zh) | 用于装配印刷电路板的方法、印刷电路板和散热片 | |
DE102015105575B4 (de) | Elektronisches Modul und Verfahren zum Herstellen desselben | |
DE112007001446T5 (de) | Chipmodul für vollständigen Leistungsstrang | |
DE102010003533B4 (de) | Substratanordnung, Verfahren zur Herstellung einer Substratanordnung, Verfahren zur Herstellung eines Leistungshalbleitermoduls und Verfahren zur Herstellung einer Leistungshalbleitermodulanordnung | |
DE102004018476A1 (de) | Leistungshalbleiteranordnung | |
DE10213648A1 (de) | Leistungshalbleitermodul | |
DE102012208146A1 (de) | Verbindungssystem zur herstellung elektrischer verbindungen eines leistungshalbleitermoduls und verfahren zur herstellung solcher verbindungen | |
DE102010016566A1 (de) | Halbleiterbaustein mit mehreren Chips und Substrat in einer Metallkappe | |
DE102014222993A1 (de) | Halbleitervorrichtung und Herstellungsverfahren dafür | |
CN101841975A (zh) | 热压法制作高导热性电路板的方法及高导热性电路板 | |
DE102017212233A1 (de) | Elektrische Baugruppe und Verfahren zur Herstellung einer elektrischen Baugruppe | |
DE102016206542A1 (de) | Verfahren zum Herstellen einer Halbleitervorrichtung | |
WO2005106954A2 (fr) | Circuit a semi-conducteur de puissance et procede pour produire un circuit a semi-conducteur de puissance | |
DE102015216779B4 (de) | Leistungshalbleitervorrichtung | |
DE102016115221A1 (de) | Verfahren zum Verbinden von mindestens zwei Substraten zur Bildung eines Moduls | |
EP1220314B1 (fr) | Module à semi-conducteurs à haut prestation | |
DE102015115132B4 (de) | Halbleitermodul mit integrierter Stift- oder Rippenkühlstruktur und Verfahren zu seiner Herstellung | |
KR20090120437A (ko) | 열전달부재를 구비한 열전모듈 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20100715 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA RS |
|
DAX | Request for extension of the european patent (deleted) | ||
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: DANFOSS SILICON POWER GMBH |
|
17Q | First examination report despatched |
Effective date: 20140331 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20140812 |