EP2235835A1 - Modulateur multibit à durée d'impulsion réglable numérique - Google Patents

Modulateur multibit à durée d'impulsion réglable numérique

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Publication number
EP2235835A1
EP2235835A1 EP09704656A EP09704656A EP2235835A1 EP 2235835 A1 EP2235835 A1 EP 2235835A1 EP 09704656 A EP09704656 A EP 09704656A EP 09704656 A EP09704656 A EP 09704656A EP 2235835 A1 EP2235835 A1 EP 2235835A1
Authority
EP
European Patent Office
Prior art keywords
signal
digital
input
pulse length
sigma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP09704656A
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German (de)
English (en)
Inventor
Hans Gustat
Johann Christoph Scheytt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IHP GmbH
Original Assignee
IHP GmbH
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Filing date
Publication date
Application filed by IHP GmbH filed Critical IHP GmbH
Publication of EP2235835A1 publication Critical patent/EP2235835A1/fr
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
    • H03M3/432—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one the quantiser being a pulse width modulation type analogue/digital converter, i.e. differential pulse width modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit

Definitions

  • Multibit modulator with digitally adjustable pulse duration
  • the invention relates to a multi-bit modulator with digitally adjustable pulse duration, in particular for use in a switched amplifier.
  • Switched power amplifiers driven by sigma-delta modulators are used as high-efficiency amplifiers, for example, in audio amplifiers or telecommunications transmitters or modulators of a broadcast stage.
  • the SDM (103-106) operates as a converter of an analog signal x (t) into a binary signal y1 (t), which serves to drive a switched amplifier (PA, 107) whose output signal y2 ( t) after filtering (108) as y (t) should form an amplified as linear as possible mapping of x (t). Since the PA as a switching amplifier normally has only one input with 1-bit data width, the digital signal of the A / D converter (105) of the modulator (103-106) will usually be a 1-bit signal from a comparator connected via a D / A converter (106) is converted into an analog value and fed as a correction value in the control loop.
  • This transmission errors in the forward path can be compensated, z. B. quantization error of the ADC, so that here also an ADC with low resolution can be used. Further Compensation is achieved by the feedback from the analog signal to the power amplifier or the subsequent reconstruction filter or from a replica of PA and filter. This can compensate for transmission errors in a larger part of the signal path. This feedback can lead to very high linearity of the entire system, since non-linearities in the forward branch can be compensated for until the feedback is taken up by the error correction in the feedback. For this, the bandwidth of the control loop must be large enough to readjust the errors of the signal.
  • the SDM must contain very high-frequency components, which makes its manufacture difficult and leads to high power consumption of the SDM itself, which reduces the efficiency of the system, especially when the transmission power of the PA is only in the range below 1 -10 watts, as in mobile Equipment usual.
  • the ADC (105) does not need to be very linear because the SDM can correct its errors
  • the DAC (106) must be higher linear than the desired linearity of the overall system. This requires a very fast and linear DAC, which is technologically demanding and requires a lot of power dissipation if the data width is to be more than 1 bit.
  • the object of the present invention is to provide an improved sigma-delta pulse length modulator and amplifier circuit with such a sigma-delta pulse length modulator.
  • the present invention overcomes the disadvantages described by employing an Mbit width multibit modulator in which the digital value range of a maximum of 2 M stages, rather than in amplitude stages, is converted into time stages that determine the duration of an output pulse. Since the behavior of the multibit modulator according to the invention has both properties of an SDM and of a pulse length modulator (PLM), the term sigma-delta-pulse length modulator (SDPLM) is used hereafter. Instead of the term pulse length modulator, the term pulse width modulator with identical meaning is used in this application. - A -
  • the sigma-delta pulse length modulator comprises a signal input with a differential stage whose first input is supplied with an analog input signal and which is designed to generate and output a differential signal corresponding to the difference of the signals present at its inputs
  • a forward loop filter for converting the difference signal into an analog filter output signal having a signal value
  • an analog-to-digital converter connected downstream of the forward loop filter configured to convert the analog filter output signal to a digital converter output signal containing two or more parallel bit component signals. which in their entirety represent a digital value corresponding to the signal value assumed by the analog filter output.
  • the sigma-delta pulse length modulator comprises a digital pulse length modulator to which the transducer output signal is supplied on the input side and which is designed to convert the applied transducer output signal into a digital modulator output signal, which consists of a single bit component signal and has a signal duration representing the digital value , which corresponds to the signal value assumed by the analog filter output signal, and a feedback loop which returns an analogue feedback signal dependent on the modulator output signal to a second input of the differential stage.
  • the feedback loop returns the modulator output signal to the second input of the differential stage via a digital-to-analog converter.
  • the analog-to-digital converter is designed to carry out the conversion of the filter output signal with a predeterminable by an applied first clock signal first clock frequency.
  • the sigma-delta pulse length modulator via a first clock input, a first clock signal at a first clock frequency and a second clock input, a second clock signal supplied to a second, compared to the first clock frequency increased clock frequency, wherein the pulse length modulator with the first and The pulse length modulator is configured to set at each clock event at the first clock input the count of the counter from a predetermined output value to the digital value corresponding to the signal value assumed by the analog filter output signal, the digital value for the digital one Value corresponding number of clock periods to keep the second clock frequency and then reset to an initial value.
  • sigma-delta pulse length modulator is configured to generate and output the modulator output signal with a signal duration that is in a non-linear relationship to the digital value of the filter output signal.
  • the analog-to-digital converter is followed by an encoder which is designed to convert the converter output signal into a coded converter output signal which can be written by a non-linear mapping rule.
  • the coder is an integral part of the sigma-delta pulse length modulator.
  • the sigma-delta pulse length modulator is preferably further configured to generate and output, based on the coded converter output signal, a modulator output signal having a respective signal duration that is in a nonlinear relationship to the digital value of the filter output signal and which is above a predetermined minimum amplifier duration dependent on the switched amplifier, and with a time signal interval between successive opposite signal edges of two temporally directly adjacent modulator output signals, which is above a predetermined, dependent on the switched amplifier temporal minimum signal spacing.
  • the coder of the sigma-delta pulse length modulator preferably includes a look-up table (LUT) which associates the possible values of the transducer output signal with each coded transducer output signal.
  • LUT look-up table
  • the bit width of the coded converter output signal comprises a larger bit width than the bit width of the converter output signal.
  • the encoder is further preferably designed to change the mapping rule for generating the coded transducer output signal during operation.
  • the sigma-delta pulse length modulator further preferably comprises a digitally adjustable delay element which generates a second signal with an adjustable delay with respect to the first signal from an applied first signal, and a digital circuit which links the first and the second signal to that their exit a third signal is applied whose pulse duration depends on the delay between the first and second signals.
  • the digital circuit includes an RS flip-flop, which is set by the first signal and reset by the second signal, and at the output of the third signal can be tapped.
  • the digitally adjustable delay element of the sigma-delta pulse length modulator comprises a number of parallel delay elements having different fixed delays to which the first signal is applied and a multiplexer connected downstream of the delay elements and formed at its output depending on the value of the coded converter output signal output one of the delayed first signals as the second signal.
  • the digitally adjustable delay element of the sigma-delta pulse length modulator preferably comprises a delay-locked loop (DLL) which is designed to impart the number of different fixed delays in parallel to the first signal supplied to it on the input side and the differently delayed first signals to a corresponding number provide parallel signal outputs, and a delay element downstream of the multiplexer, which is designed to output at its output depending on the value of the coded transducer output signal each one of the delayed first signals as the second signal.
  • DLL delay-locked loop
  • the encoder of the sigma-delta pulse length modulator is further preferably designed to change both the time of the rising edge and the falling edge of the modulator output signal in dependence on the input signal of the encoder.
  • the coder is preferably designed to change the pulse duration of the modulator output signal in dependence on the input signal of the coder and at the same time modulate the phase of the modulator output signal with respect to the clock effective for the feedback loop of the sigma-delta pulse length modulator, e.g. B. to the clock of the analog-to-digital converter, to keep constant to a remaining residual error of the phase.
  • the first input of the differential stage of the sigma-delta pulse length modulator is preceded by an input digital-to-analog converter which is designed to convert a digital input signal present at its input into the analog input signal.
  • the digital input signal vector determining the digital input signal is provided with a digital input amplitude signal and either a digital input signal vector Input phase signal or a digital input frequency signal, the digital input amplitude signal of the differential stage and the other of the two digital signals of the input signal vector supplied to a clock generator which is adapted to derive from this other of the two digital signals of the input signal vector, a clock signal which the sigma Delta pulse length modulator is supplied.
  • the digital input amplitude signal from the differential stage and the digital input frequency signal from a digital input signal vector determining the digital input signal having a digital input amplitude signal and a digital input frequency signal are applied to a clock generator which forms is to derive from the input frequency signal a clock signal which is supplied to the analog-to-digital converter and the sigma-delta pulse length modulator.
  • the frequency of the clock signal effective for the feedback loop of the sigma-delta pulse length modulator e.g. B. the clock of the analog-to-digital converter, according to the alternative embodiment of the invention is temporally variable and is from the instantaneous characteristics of the input signal of the sigma-delta pulse length modulator, z. B. from the time interval between two adjacent same-direction zero crossings, formed by a time-varying clock generator.
  • the frequency of the clock signal is preferably formed by a frequency multiplier.
  • the sigma-delta pulse length modulator comprises a signal input with a digital differential stage whose first input is supplied with a digital input signal and which is designed to generate a digital difference signal corresponding to the difference of the digital signals present at their inputs a forward feedforward digital filter for converting the input signal to a digital filter output signal containing two or more parallel bit component signals representing in their entirety a digital value corresponding to the signal value accepted by the digital filter output signal and a digital pulse length modulator input to the digital filter output signal and is configured to convert the applied filter output signal into a digital modulator output signal, which consists of a single bit component signal and the one Signal duration, which is dependent on the signal value of the digital filter output signal.
  • the sigma-delta pulse length modulator comprises a feedback loop which returns a digital feedback signal dependent on the digital filter output signal to a second input of the differential stage, comprising a digital input signal vector determining the digital input signal with a digital input amplitude signal and either a digital input signal.
  • Phase signal or a digital input frequency signal, the digital input amplitude signal of the differential stage and the other of the two digital signals of the input signal vector is supplied to a clock generator which is adapted to derive from this other of the two digital signals of the input signal vector, a clock signal, the pulse length modulator is supplied.
  • the digital forward loop filter of the sigma-delta pulse length modulator is a D flip-flop whose D input is supplied with the digital difference signal and whose enable input is supplied with the clock signal of the clock generator.
  • the sigma-delta pulse length modulator is preferably configured to generate and output the modulator output signal with a signal duration that is in a non-linear relationship to the digital value of the filter output signal.
  • the forward loop filter of the sigma-delta pulse length modulator is preferably followed by an encoder which is configured to convert the filter output signal into a converter output signal encoder output signal which can be written by a nonlinear mapping rule.
  • the encoder is an integral part of the sigma-delta pulse length modulator.
  • the encoder output signal is preferably fed back to the second input of the digital differential stage.
  • the encoder output signal is fed to the input of a digital simulation of a sigma-delta pulse length modulator downstream switching amplifier and / or reconstruction filter and fed back from the output of this digital simulation to the second input of the digital differential stage.
  • the amplifier circuit comprises a signal input, which is followed by a sigma-delta pulse length modulator as described above, a digitally switched amplifier, which is driven by the output signal of the sigma-delta pulse length modulator and which is designed, the output signal of the sigma-delta pulse length modulator and output as an amplifier output signal.
  • the amplifier circuit comprises a reconstruction filter to which the amplifier output signal is supplied and the is designed to filter the amplifier output signal such that at the output of the reconstruction filter an analog output signal is applied, which is amplified relative to the input signal applied to the signal input.
  • the feedback loop of the amplifier circuit preferably returns a feedback signal derived from the amplifier output signal via a digital-to-analog converter to the second input of the differential stage.
  • the feedback loop of the amplifier circuit directly feeds back a feedback signal derived from the analog output signal of the reconstruction filter to the second input of the difference stage.
  • the feedback signal is preferably derived by means of a capacitive or inductive coupling from a terminal in the digitally connected amplifier or reconstruction filter.
  • the switched amplifier and the reconstruction filter are not monolithically integrated with the sigma-delta pulse length modulator, but instead form separate circuit modules.
  • the feedback loop is monolithically integrated with the sigma-delta pulse length modulator and includes a first replica circuit of the switched amplifier configured to down-scale the behavior of the switched amplifier during operation of the amplifier circuit, and a second replica circuit formed in FIG Operation of the amplifier circuit to replicate the behavior of the reconstruction filter downscaled.
  • first and the second replica circuits can be combined in a common replica circuit.
  • the first and second replica circuits and the common replica circuit are preferably digital circuits.
  • the sigma-delta pulse length modulator is configured to generate the modulator output signal with a signal duration gradation between adjacent signal values, wherein a signal duration step is less than a minimum delay time of an active amplifier stage.
  • FIG. 1 block diagram of an amplifier circuit with a sigma-delta modulator
  • FIG. 2 a block diagram of an amplifier circuit having a first exemplary embodiment of a sigma-delta pulse length modulator according to the invention and an analog input interface
  • FIG. 2 b shows a block diagram of an amplifier circuit according to FIG. 2 a with a second embodiment variant of the inventive sigma-delta pulse length modulator with modified feedback, FIG.
  • FIG. 2c block diagram of a third embodiment of an amplifier circuit according to FIG. 2a with a third embodiment variant of the inventive sigma-delta pulse length modulator with modified feedback, FIG.
  • FIG. 2d shows a block diagram of a fourth embodiment of an amplifier circuit according to FIG. 2a with a fourth embodiment variant of the inventive sigma-delta pulse length modulator with modified feedback, FIG.
  • FIG. 3 shows a block diagram of an amplifier circuit according to FIG. 2a additionally with an encoder in the signal path of the sigma-delta pulse length modulator according to the invention
  • DPWM digitally controllable pulse width modulator
  • FIG. 4b shows a circuit example of a DPWM according to FIG. 4a, FIG.
  • FIG. 5b block diagram of a second variant of a DPWM according to FIG. 5a
  • FIG. 5c block diagram of a third variant of a DPWM according to FIG. 5a
  • FIG. 6a shows an example of a chain of non-linear amplifier stages of a conventional delay-locked loop (DLL)
  • FIG. 6b shows a chain of non-linear amplifier stages according to FIG. 6a, in which a plurality of series-connected passive delay elements are connected in parallel with each amplifier stage
  • FIG. 6a shows an example of a chain of non-linear amplifier stages of a conventional delay-locked loop (DLL)
  • FIG. 6b shows a chain of non-linear amplifier stages according to FIG. 6a, in which a plurality of series-connected passive delay elements are connected in parallel with each amplifier stage
  • FIG. DLL delay-locked loop
  • FIG. 6c shows a chain of non-linear amplifier stages according to FIG. 6b, in which the parallel circuit of the passive delay elements connected in series to each amplifier stage is separated, FIG.
  • FIG. 6d shows a chain of non-linear amplifier stages according to FIG. 6c, in which the chains of the passive delay elements are extended, FIG.
  • FIG. 7 shows a block diagram of an amplifier circuit according to FIG. 3, wherein the sigma-delta pulse length modulator according to the invention is additionally provided with a time-variable clock generator,
  • FIG. 9 shows a diagram of output signal curves of a DPWM according to FIG. 7
  • FIG. 10 shows a circuit with a multiplexer of a DPWM and an edge-triggered RS flip-flop
  • FIG. 11 shows a block diagram of an amplifier circuit according to FIG. 7, wherein the sigma-delta pulse length modulator according to the invention is additionally provided with a frequency divider,
  • FIG. 13 is a graph showing output waveforms of a DPWM shown in FIGS. 11 and 12 when using a DLL having 16 outputs.
  • FIG. 14 shows a block diagram of an amplifier circuit with a first alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface
  • 15 shows a circuit with a frequency synthesizer, a multiplexer of a DPWM and an edge-triggered flip-flop
  • 16 shows a block diagram of an amplifier circuit with a second alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface
  • FIG. 17 shows a block diagram of an amplifier circuit with a third alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface
  • FIG. 18 shows a block diagram of an amplifier circuit with a fourth alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface.
  • a first exemplary embodiment of an amplifier circuit with a sigma-delta pulse length modulator according to the invention is shown schematically in FIG. 2 a with reference to a block diagram.
  • the pulse interval (the duration of the pause between the pulses) changes in the opposite direction to the pulse duration: a shorter pulse duration leads to a greater pulse interval.
  • a counter which accepts the input value yd (t) for each clock CIk of the frequency f_clk and sets the output value to '1' for yd (t) clocks of the frequency Clk2, and then sets it to '0' until the next clock CIk.
  • Fig. 2a The operation of the system in Fig. 2a is similar to that of the system in Fig. 1 with a 1-bit ADC in Fig. 1, but results in higher linearity.
  • the ADC has M1> 1 bit width (eg 5 bits instead of 1 bit in Fig. 1)
  • y1 (t) is also a 1 bit wide signal
  • the DAC can be a 1-bit DAC and the PA a 1-bit PA, making it much easier to satisfy its linearity requirement than a multi-bit DAC or multi-bit PA.
  • the instantaneous pulse width y1 (t) is variable and is directly determined by the integer number with Z1 possible values formed by the M1 bits of the multi-bit signal yd (t) at the output of the ADC.
  • this is a linear representation of yd (t) by the pulse duration of y1 (t) and thus a better simulation of the signal than a 1-bit quantization, which corresponds to a low distortion.
  • the SDPLM in Fig. 2a is a multi-bit SDM in which the multi-bit value yd (t) is represented linearly by the pulse duration.
  • the multi-bit value yd (t) is represented linearly by the pulse duration.
  • PLM pulse length modulator
  • FIG. 2b A further advantageous variant of this is shown in FIG. 2b:
  • the error feedback and thus linearization concerns not only the ADC but also the PA by tapping the feedback to the PA, e.g. via a loose coupling (210), which draws very little power from the PA.
  • the DAC (106) can then be omitted.
  • the reconstruction filter (108) can be included in the error feedback and linearized, as indicated in Fig. 2c.
  • the variants in Figures 2c and 2d have a feedback loop that extends from loop filter (104), ADC (105) and DPWM (201) through PA (107) and reconstruction filters (108) back to summation point (103) and loop filter (104) , While summation point (103), loop filter (104), ADC (105), and DPWM (201) are all relatively easy to integrate, PA (107) is rarely (at low power) and reconstruction filter (108) after the current state of the art almost never.
  • the feedback loop in Figures 2c and 2d includes multiple components outside of an integrated one Circuit, which together with their connection technology have considerably larger dimensions than an integrated circuit with summation point (103), loop filter (104), ADC (105) and DPWM (201) and therefore require geometrically and electrically relatively long signal paths. This can lead to problems in the feedback loop, especially affecting its stability, especially when used for high signal frequencies, where signal propagation times can be very significant.
  • FIG. 2 d another variant according to the invention is proposed in FIG. 2 d, in which the entire feedback loop runs within a monolithically integrated circuit (220). Additional components are introduced for this purpose: A replica PA (207) simulates the PA (107) in its behavior as linearly scaling as possible, and a replica reconstruction filter (208) simulates the reconstruction filter (108) as linearly as possible in its behavior , If the PA (107) is, for example, a large switched MOS transistor with 40 V operating voltage as an external component with a wire-wound output transformer at the drain, then the replica PA (207) can be a much smaller switched MOS transistor with 2.5 V operating voltage be as a monolithic integrated device with a monolithically integrated output transformer at the drain.
  • the PA (107) is, for example, a large switched MOS transistor with 40 V operating voltage as an external component with a wire-wound output transformer at the drain
  • the replica PA (207) can be a much smaller switched MOS transistor with 2.5 V operating voltage be as a monolithic integrated device with a monolithically integrated output
  • the replica PA (207) can also have a completely different structure than the PA (107), which only when viewed from the outside (as a black box) behaves in a linear scaling approximately like the PA (107), but in scale reduction, so that a monolithic integration is possible, so z. B. with 10 mA drain current instead of 10 amps.
  • replica reconstruction filter (208) may have a very different structure than the reconstruction filter (108), which is only externally (in black box) approximated to the reconstruction filter (108) in linear scaling, but scaled down, such that a monolithic integration is possible. In this way delays are avoided by long signal paths in the entire feedback loop, and a higher stability of an SDPLM or a higher maximum signal frequency can be achieved.
  • This disadvantage overcomes a further improvement according to the invention in that the output signal of the ADC is used in a non-linear manner for controlling the pulse duration such that pulse durations of '0' or '1' do not occur below a minimum duration t_min_0 or t_min_1.
  • the ADC output values yd (t) are mapped to the input values of the DPWM ye (t) so that the DPWM receives no input values which would result in too short pulse durations or pulse pauses for the PA.
  • FIG. 3 represents an exemplary exemplary embodiment for this purpose, representative of numerous possible forms of implementation.
  • the return of the DPLM in front of the PA is assumed as in FIG. 2a.
  • the other return variants symbolically indicated in FIGS. 2b to 2d can also be used, but have not been shown here for the sake of simplicity.
  • an encoder (302) for example a look-up table (LUT) converts the M1 bit wide output of the A / D converter (ADC) into a now M2 bit wide input signal of the DPWM, the new bit width M2 may be equal to or different from M1.
  • ADC A / D converter
  • the integer value range of the output values ye (t) of the encoder (302) of Z2 possible values may be equal to or different from the integer value range of the input values yd (t) of the encoder (302) of Z1 possible values.
  • the advantage of this additional component is that now any mapping of the input values yd (t) of the encoder (302) into output values ye (t) of the encoder (302) allows.
  • this coder (302) can have the following function:
  • the DPWM contains a counter that resets to 0 after each new clock at CIk the count incremented to Clk2 with each clock and holds the output of the DPWM at '1' as long as the count is less than the input value of the DPWM, and ye_max is greater than the maximum count achievable in one clock period of CIk.
  • FIG. 4a An example of such a DPWM is shown in FIG. 4a: A Clk2 clocked down counter (401) is tested for output 0 with logic (402), and when 0 is reached, an edge triggered RS flip flop (403) is reset at the next clock at CIk receives a short set pulse, which also causes the counter (401) to reload the current value ye (t).
  • the clock frequency f_clk2 is chosen to be f_clk such that at the maximum value of ye (t) (a value of 15 for the 4-bit backward counter in FIG. 4) during a period 1 / f_clk, the count can not reach 0 (e.g.
  • the edge-triggered RS flip-flop (403) is set by a 0-1 edge at input S (i.e., the positive output Q_P is 1, the inverted output Q_N is 0) and is reset by a 0-1 edge at input R.
  • Fig. 4b shows a circuit example in this regard:
  • the set pulse stops its effect when it has passed through the chain of 3 inverters, so that from then on the circuit is free for a reset pulse, which also terminates its effect when the chain of 3 inverters until it becomes inactive again the set and reset signal.
  • the short pulse shortened set signal SetPulse is coupled out and is available for loading the backward counter (401).
  • Further circuit examples of such a pulse-controlled R-S flip-flop are known, for example with a clocked circuit instead of the inverter chain.
  • the SDPLM in Fig. 3 works like the SDM in Fig. 2a.
  • the function in (1) has two stages at both ends yd0 and yd1 of this range, which are formed by jumps of 0 and the maximum value, respectively.
  • the signal is greatly distorted at values yd (t) of the ADC outside the linear range. This distortion generates errors, but these are returned by the feedback of the SDPLM and result in a correction in the next following value yd (t).
  • the nonlinear distortion in (1) is still significantly more linear than a purely binary distinction of a conventional SDM that can only set whole pulses of durations 1 / f_clk at the output to '1' or '0'.
  • a conventional SDM can be seen as a special case of an extended SDPLM according to the invention according to FIG. 3 with a special variant of the function in (1), which results when yd ⁇ > yd1 is selected, and thus the middle range disappears, and thus only pulses the maximum duration 1 / f_clk or no pulses can be output by the DPWM.
  • the general function in (1) degenerates into a comparator function which generates a 1-bit value from the multi-bit value of the ADC to give an SDM behavior that is 1-bit -SDM corresponds.
  • the maximum number of possible pulse lengths Z2 at the input of the PA (107) in a multi-bit SDPLM according to the invention according to FIG. 3 when using (1) is slightly less than the maximum value of the number of stages Z1 in a multi-bit SDPLM according to the invention 2a, because the encoder (302) has excluded those of the Z1 step numbers which can not be transmitted "well enough” by the PA (107) (ie with insufficient efficiency or linearity) PA now only needs to transmit pulse lengths that are "good enough” for the PA.
  • the nonlinearity in (1) thus leads to Z2 ⁇ Z1 by choosing yd0> 0 and yd1 ⁇ ye_max.
  • a requirement for a sufficiently linear conversion of an input pulse length of the PA into an (ideally equally large) output pulse length of the PA can lead to a minimum pulse duration at the input must not fall below, as well little like a minimum duration of a pulse break.
  • the permissible values for this minimum pulse duration or pulse pause duration are thus determined by both PA criteria, efficiency (efficiency) and linearity on the basis of the switching characteristics of the PA, z. B. his slew rate, given.
  • the maximum clock period of a conventional SDM is severely limited by the PA.
  • a property of the PA is not used: Even a very small extension of the pulse duration at the input leads to a defined (almost linear) small extension of the pulse duration at the output, and that with a temporal step size, which is limited only by noise down and not by the bandwidth of the PA.
  • the total width of the pulse at the PA input must not be less than a relatively large minimum value (eg, 300 ps), this pulse duration may be varied in very fine steps whose step size may be much smaller than this minimum pulse duration.
  • a conventional PLM uses the variable-pulse-width property, but it has no feedback that could compensate for a nonlinear characteristic as defined in (1), and therefore requires a linear characteristic of the conversion. Amplitude in pulse duration without the possibility to exclude certain pulse durations, and as a result a PA with very high bandwidth to process even very short pulses.
  • the requirement for the bandwidth of the PA is relaxed compared to Fig.
  • the ADC can in another variant also be embodied as an ADC with a lower resolution M1 ⁇ M2, which does not even dissolve the edge regions suppressed by the encoder (302).
  • the value for M2 can be increased even with a constant resolution M1, if a counter with a resolution M2> M1 is easier to implement than an ADC with a higher resolution than M1, which is usually the case.
  • M2 is technically usually less limited than M1. Thus, the number of stages and thus the signal quality of the system can be further increased.
  • a more general formulation of the function of the encoder (302) in Fig. 3 according to the invention is that yd (t) is mapped to ye (t) with the encoder (302) such that pulse durations '0' and '1' below, respectively a minimum duration t_min_0 or t_min_1 not occur, where t_min_0 and t_min_1 are defined by the desired linearity of the system and efficiency of PA based on the PA speed.
  • a fixed image with a real look-up table is not absolutely necessary; a time-varying image in the encoder (302) is also possible, e.g. switching between several functions as a function of the input signal as long as pulse durations or pulse pauses below a minimum duration t_min_1 or t_min_0 do not occur.
  • This algorithm could, for. B. be designed so that the middle range in (1) is dynamically extended as long as the average efficiency (or the mean linearity or the error vector magnitude EVM) does not fall below a predetermined value. This gives the middle At times even more stages and even lower errors in the signal reconstruction, ie an even higher signal quality.
  • a simple embodiment of this more complex algorithm for the LUT component (302) could be e.g. For example, measure the instantaneous temperature of a power transistor of the PA (which can serve as a negative measure of PA efficiency) and, at higher temperature, decrease the midrange (ydO and yd1 approach each other) and increase that range at lower temperature (Remove ydO and yd1 from each other by decreasing ydO or increasing yd1). This optimizes the signal quality and ensures a desired average efficiency, a desired signal quality and safe operation of the PA.
  • 1 ps for a PA can be a realistic value in today's semiconductor technologies, because the time step can be reduced to the noise limit, below which no deterministic effect of a changed pulse duration is more detectable.
  • Such a clock frequency f_clk2 of e.g. 1 THz for the DPWM is hardly achievable in today's technologies, since the upper clock frequency by the minimum transit time of a signal by a logical unit (logic and memory, in the minimal case of a ring counter a single flip-flop) is determined, usually clear is greater than the time uncertainty due to noise.
  • An optimal utilization of the possible time resolution of the PA therefore requires a different DPWM than a DPWM based on clocking with f_clk2 as in FIG. 4.
  • Fig. 5a shows another embodiment of the DPWM.
  • the duration of the output pulse y1 (t) is not determined by a counter, but by a digitally adjustable delay (501), which resets an RS flip-flop (503) delayed here, after it has been derived by a clock derived from the clock CIk Pulse was set.
  • a digitally adjustable delay a number of implementations are known, for example as indicated in Fig. 5a by a DAC (501 b) followed by an analog adjustable delay (501a) are formed.
  • the input signal of the DAC (501b) is the input signal of the DPWM ye (t).
  • N 2 M of delay-connected delay units of different delay, of which exactly one is selected by a downstream multiplexer.
  • ye (t) is the input signal of the multiplexer that determines the selection of the delay unit.
  • DLL delay-locked loop
  • ye (t) is the input to the multiplexer, which determines the selection of the delay level.
  • the number of delay stages and thus the temporal resolution of a DLL which is usually based on chains of (often differential) non-linear amplifier stages, can be greatly increased.
  • a chain of such amplifier stages of a conventional DLL is shown by way of example. If the amplifier stages (602) consist of differential amplifiers, they have real differential inputs and outputs, of which only one is shown here.
  • the temporal resolution of the DLL is formed by the delay of the signal between two adjacent taps (603). The delay is dictated by the speed of the amplifier stages used.
  • Fig. 6a a chain of such amplifier stages of a conventional DLL is shown by way of example. If the amplifier stages (602) consist of differential amplifiers, they have real differential inputs and outputs, of which only one is shown here.
  • the temporal resolution of the DLL is formed by the delay of the signal between two adjacent taps (603). The delay is dictated by the speed of the amplifier stages used.
  • the temporal resolution is improved by a factor of 4 by connecting in parallel to each active amplifier stage (602) a number (here 4) of series-connected passive delay elements (604).
  • passive delay elements can have an almost arbitrarily small delay and thus allow an almost arbitrarily fine temporal resolution of the DLL.
  • the series-connected passive delay elements (604) both input and output side are connected in parallel to the associated active amplifier stage (602).
  • the delay from the input to the output of the active amplifier stage (602) is changed and determined in part by the passive elements. This can be an advantage if a high reproducibility and close tolerance of the delay are desired because the delay of passive elements can usually be made tighter tolerated than that of active elements.
  • the connection can be separated on the output side, as shown in Fig. 6c.
  • the delay from input to output of the active amplifier stage (602) is determined solely by the active amplifier stage (602). If a wide range of delay adjustment of active amplifier stage (602) is to be made greater than the delay of a single passive delay element (604), the chain of passive delay elements (604) may be extended as shown in Figure 6d to cover the entire range of necessary intermediate steps on delays.
  • the delay and thus the duration of the pulse can be changed in considerably finer time steps with a DPWM according to FIG. 5c, so that the possible time resolution of the PA for whose pulse duration at the input y1 (t) it can be used even finer, and the signal y2 (t) can represent the signal x (t) with even higher quality.
  • the operation of an SDM with time-variable frequency of the clock is not common practice.
  • the usual mathematical foundations of an SDM are based on the z-transformation, which requires a constant clock frequency. Nevertheless, they can be used approximately in this variant according to the invention, if the bandwidth of the signal x (t) is much smaller than its carrier or center frequency, which is usually the case in telecommunications.
  • the signal (702) for timing the ADC and the DPWM is generated by a time-varying clock generator (701) from the current frequency or current period of the input signal x (t), as shown in Fig. 7 symbolically.
  • the instantaneous period is a time-varying form of the constant period defined for purely periodic signals.
  • the time interval between two adjacent equidirectional zero crossings (eg both from x (t) ⁇ 0 to x (t)> 0) of the input signal x (t) can be regarded as the instantaneous period.
  • the clock generator (701) may include, for example, a clock multiplier with a downstream phase shifter.
  • the timing of sampling the input signal x (t) is phase locked to x (t) itself, and the phase shifter can adjust this phase difference deltaPhi.
  • This is especially useful for small values of oversampling factor OVR, that is, if only a few samples are executed per period of x (t). If the sampling times lie near the zero crossing of x (t), then the signal is reconstructed very poorly with a small OVR.
  • deltaPhi 90 °, x (t) becomes z. B.
  • the clock multiplier can be constructed, for example, from one or more clock doublers connected in series.
  • clock multipliers in particular clock doublers
  • a number of basic circuits also known as frequency multipliers or frequency doubling are known.
  • PLL phase-locked loop
  • the DLL is constructed so that its total delay in the center of the delay control without delay-locking is approximately K clock periods of the center frequency of x (t), where K is an integer by which the clock is to be multiplied. In the case of the DLL, this delay is exactly K clock periods of the center frequency of x (t).
  • This DLL is controlled with x (t) and is synchronized in the locked state phase locked with x (t).
  • FIG. 9 shows five examples of possible output signals:
  • ye (t) ye_max and thus y1 (t) should be constant at '1'.
  • ye (t) is in a definable intermediate range, for example between 5 and 11. Which limits are chosen for this range, According to the invention, as described above, depends on which minimum and maximum pulse duration are allowed for the given PA and its efficiency and linearity.
  • the pulse duration at y1 (t) thus varies from 5/16 (4th signal from below in FIG. 9) over 1/2 (3rd signal from below in FIG. 9) and 1 1/16 (2nd signal from below in Fig. 9) of the entire instantaneous clock period of CIk.
  • the pulse duration is thus varied depending on the amplitude of x (t), which is determined according to FIG. 7 phase-locked to x (t) in the permissible limits for the PA.
  • the nonlinearities at the end regions as well as the further errors resulting from quantization and other errors in the forward branch are fed back via the DAC (106) and compensated in the following periods.
  • the width M1 of yd (t) becomes larger, allowing a larger width M2 of ye (t).
  • the DPWM then receives constant values over several clock cycles of CIk at the input and generates - furthermore clocked with the undivided CIk - a duty cycle constant over K periods at y1 (t) for the PA. But with K> 1, the feedback loop slows down, so that the errors are no longer fed back to every clock on CIk, so that the ability of the SDPLM to linearize is partially lost.
  • K an optimal compromise for the particular implementation of the system, e.g. Between the increased accuracy by larger M1 and M2 and the reduced accuracy through less frequent feedback.
  • the pulse width modulation as shown, for example, in Fig. 9 still has a shortcoming, which comes into play especially at very low value for KOVR:
  • the beginning of the pulse of the signal y1 (t) is phase locked to x1, and thus necessarily varies the time center of the Pulse with the current amplitude. This gives y1 (t) an ampli- tudenplie phase modulation, which is the stronger, the smaller KOVR is, ie the fewer Clk cycles per period of x (t) are generated.
  • FIG. 12 An example of this is shown in FIG. 12 as a structure and in FIG. 13 in the signal profile.
  • the LUT (previously 302, now 1202) receives a modification: it has 2 outputs ye_start and ye_stop for the previous output ye.
  • the signals ye_start and ye_stop can be formed according to the following rule:
  • this output ye is not necessary at the LUT, since ye results from the control of the edge-controlled RS flip-flop (503) with the other signals.
  • the resulting signal curves are shown by way of example in FIG. 13.
  • yd (t) in the range from 5 to 11
  • y1 (t) a proportional pulse duration is generated at y1 (t), which, unlike FIG. 9, is now centered about the center of the pulse.
  • this centering is not exact, but can differ by a maximum of a half time unit, which results from the integer rounding in (2).
  • Such a system according to the invention can convert an analog high-frequency signal x (t) with a high-efficiency switched PA into an amplified analog output signal Generate y (t) with good linearity. It is well suited to replace existing analog PA with lower efficiency. Because of the inventive feature of setting limits for the minimum pulse duration and the minimum pulse pause, switched PA can be used up to much higher carrier frequencies than, for example, in a conventional PLM.
  • the solution described here has the main advantages that, firstly, the pulse duration is variable in virtually arbitrarily fine steps, the time unit can be far smaller than a clock period, and secondly, the pulse can be synchronized in phase with the input signal, with the described Centering the pulse center even when changing the pulse duration is almost no change in the phase.
  • xd (k) can be a summary (a vector) of several individual digital signals, for example comprising the digital signals of amplitude xda (k) and phase xdp (k), or comprising the digital signals of amplitude xda (k) and current frequency xdf (k).
  • x (t) which contains a signal in the range of the carrier frequency
  • the indication of amplitude and phase or amplitude and instantaneous frequency despite a relatively slow clock for k, namely based on the frequency range of the baseband, a any high-frequency signal x (t) in the frequency range of the carrier will be described.
  • Such a digital interface thus provides a very suitable description of x (t).
  • the system according to the invention can be advantageously adapted.
  • the clock is generated from the phase signal xdp (k) by a frequency synthesizer (1411) while the analog signal xa (t) for the SDPLM is generated by a D / A converter (1412) becomes.
  • a digital frequency signal xdf (k) can also be applied at the input of the frequency synthesizer (1411), which indicates the frequency currently to be synthesized (ie the integral of the phase). Whether phase or frequency is chosen depends on the definition of the digital interface, which in turn can be chosen so that the frequency synthesis requires a simple frequency synthesizer (1411).
  • the SDPLM loop should also be clocked in the order of magnitude of the carrier frequency for a digital interface operating in the time units of the baseband (or at least in fractions thereof, if the principle of FIG. 11 applies to the system in FIG. 14 is applied), so that the feedback of the nonlinearities takes place in small time periods and the errors are corrected promptly, so that on average a linear function results.
  • An advantageous solution for the required frequency synthesis is to tap off the taps of a constant clock (the carrier frequency) clocked DLL with a multiplexer so that each clock is incremented by a number of Z taps and thus delay units, such as the phase of the signal xs (t) to be synthesized has changed with respect to the signal xc (t) with the constant carrier frequency in this clock.
  • the carrier frequency is 1 GHz and the frequency to be synthesized is 1.01 GHz
  • the phase difference in each 1 GHz cycle is 1/100 period, ie 10 ps.
  • Such a frequency synthesis with DLL has the advantage that the same taps of the DLL can also be tapped to drive the inputs of the multiplexer or multiplexer, such as in Fig. 10 or 12. Since they are phase-locked to xc (t) and are thus no longer phase-locked to x (t), but in the frequency synthesizer (1411) incremented by Z (t) levels in each step must be added exactly that number to the value at the input of the multiplexer of the DPWM (501), as shown in Fig. 15 is outlined.
  • the structure in Fig. 14 includes a plurality of A / D and D / A conversions. These can be summarized very advantageously to a structure as shown in Fig. 16.
  • the feedback loop now only contains digital elements.
  • the summation function (1403) is now also executed digitally. Instead of the signal y1 (t) at the output of the DPWM, the signal ye (t) is now fed back, which is also a digital signal.
  • the essential nonlinearity of the system namely that of the encoder (302), is thus detected and corrected by the feedback.
  • the nonlinearities of the PA (107) and the reconstruction filter (108) are to be linearized in the feedback, they can advantageously be converted into a monolithic circuit (analogous to FIG. 2d) by a simulation of the PA (207) and the reconstruction filter (208). 1701) are integrated with the SDPLM and clock generation (1411) as shown in FIG. Again, a D / A converter (106) is required in the feedback loop since the replicas, as well as PA (107) and reconstruction filters (108), themselves produce analog signals.
  • this structure can advantageously be converted so that the SDPLM contains only digital elements and thus allows high accuracy and resolution at low cost and high clock rate.
  • FIG. 16 the integer signal ye (t) is used, and unlike in FIG. 17, the replicas of the PA (1707) and the reconstruction filter (1708) are digital elements.
  • the replicas of the PA (1707) and the reconstruction filter (1708) can also be combined into a single digital element that generates a sequence of digital output values yd * (t) for a sequence of input values ye (t) that reflect the real behavior of the PA (107) and the reconstruction filter (108) with sufficient accuracy and scaled for the SDPLM.
  • one already suffices here simple LUT which indicates the integral of the value resulting at yd over a clock period in suitably scaled form as output value yd * for each possible value ye and thus pulse duration value y1 which is present at the input of the PA.
  • the individual clock periods are relatively independent of each other, so that even such a LUT as a common replica of the PA (107) and the reconstruction filter (108) can provide very good results.
  • Further effects of the temporal dependence of yd (t) on previous history in previous clock periods resulting, for example, from the heating of the PA can also be digitally modeled, eg by means of FIR filters, and thus included together with LUT in the common replica.
  • a structure according to the invention offers a monolithic circuit (1701) which is improved but still cost-effective to implement, with a digital interface at the input providing a high-quality largely error-free analog signal yd (t) at the output of the system.

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Abstract

Modulateur de longueur d'impulsion sigma-delta, comprenant une entrée de signal à étage différentiel dont la première entrée reçoit un signal d'entrée analogique, ledit étage étant configuré pour produire et émettre en sortie un signal différentiel correspondant à la différence des signaux appliqués à leurs entrées, un filtre à boucle d'anticipation pour la conversion du signal différentiel en signal de sortie de filtre analogique ayant une valeur de signal, un convertisseur analogique-numérique en aval du filtre à boucle d'anticipation, ledit convertisseur étant configuré pour la conversion du signal de sortie de filtre analogique en signal de sortie de convertisseur numérique contenant deux ou plusieurs signaux composants de bits parallèles représentant une valeur numérique globale correspondant à la valeur de signal prise par le signal de sortie de filtre analogique, un modulateur de longueur d'impulsion numérique auquel le signal de sortie de convertisseur est envoyé, à son côté entrée, ledit modulateur étant configuré pour convertir le signal de sortie du convertisseur entrant, en un signal de sortie de modulateur numérique qui comprend un signal composant de bit individuel et ayant une durée de signal qui représente la valeur numérique correspondant à la valeur de signal prise par le signal de sortie de filtre analogique, et une boucle de rétroaction qui renvoie un signal de rétroaction analogique qui dépend du signal de sortie de modulateur, à une seconde entrée de l'étage différentiel.
EP09704656A 2008-01-21 2009-01-21 Modulateur multibit à durée d'impulsion réglable numérique Ceased EP2235835A1 (fr)

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DE102008041142A DE102008041142A1 (de) 2008-01-21 2008-08-11 Multibit-Modulator mit digital stellbarer Pulsdauer
PCT/EP2009/050639 WO2009092722A1 (fr) 2008-01-21 2009-01-21 Modulateur multibit à durée d'impulsion réglable numérique

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US6414614B1 (en) 1999-02-23 2002-07-02 Cirrus Logic, Inc. Power output stage compensation for digital output amplifiers
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US6965339B2 (en) 2004-04-07 2005-11-15 Motorola, Inc. Method and system for analog to digital conversion using digital pulse width modulation (PWM)

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