EP2235835A1

EP2235835A1 - Multibit modulator with digital adjustable pulse duration

Info

Publication number: EP2235835A1
Application number: EP09704656A
Authority: EP
Inventors: Hans Gustat; Johann Christoph Scheytt
Original assignee: IHP GmbH
Current assignee: IHP GmbH
Priority date: 2008-01-21
Filing date: 2009-01-21
Publication date: 2010-10-06
Also published as: DE102008041142A1; WO2009092722A1

Abstract

Sigma delta pulse length modulator, comprising a signal input with a difference stage, the first input of which receives an analog input signal, said stage being configured to produce and output a difference signal corresponding to the difference of the signals at the inputs thereof, a forward loop filter for converting the difference signal to an analog filter output signal having a signal value, an analog-digital converter downstream of the forward loop filter, said converter being configured for the conversion of the analog filter output signal to a digital converter output signal containing two or more parallel bit component signals representing an overall digital value corresponding to the signal value assumed by the filter output signal, a digital pulse length modulator to which the converter output signal is sent at the input side thereof, the modulator being designed for converting the incoming converter output signal to a digital modulator output signal comprising an individual bit component signal and having a signal duration that represents the digital value corresponding to the signal value assumed by the analog filter output signal, and a reverse coupling loop that feeds an analog reverse coupling signal, which depends on the modulator output signal, to a second input of the difference stage.

Description

Multibit modulator with digitally adjustable pulse duration

The invention relates to a multi-bit modulator with digitally adjustable pulse duration, in particular for use in a switched amplifier.

Switched power amplifiers driven by sigma-delta modulators (SDMs) are used as high-efficiency amplifiers, for example, in audio amplifiers or telecommunications transmitters or modulators of a broadcast stage.

Here, as shown in Fig. 1, the SDM (103-106) operates as a converter of an analog signal x (t) into a binary signal y1 (t), which serves to drive a switched amplifier (PA, 107) whose output signal y2 ( t) after filtering (108) as y (t) should form an amplified as linear as possible mapping of x (t). Since the PA as a switching amplifier normally has only one input with 1-bit data width, the digital signal of the A / D converter (105) of the modulator (103-106) will usually be a 1-bit signal from a comparator connected via a D / A converter (106) is converted into an analog value and fed as a correction value in the control loop. This transmission errors in the forward path (104, 105) can be compensated, z. B. quantization error of the ADC, so that here also an ADC with low resolution can be used. further Compensation is achieved by the feedback from the analog signal to the power amplifier or the subsequent reconstruction filter or from a replica of PA and filter. This can compensate for transmission errors in a larger part of the signal path. This feedback can lead to very high linearity of the entire system, since non-linearities in the forward branch can be compensated for until the feedback is taken up by the error correction in the feedback. For this, the bandwidth of the control loop must be large enough to readjust the errors of the signal. If such a system is used for a high-frequency signal x (t), then the clock frequency of the system, the sampling rate of the ADC and the time base for the here (as usual in Z-transform) SDM filter H (z) (104 ), be much higher than the highest signal frequency f_x_max occurring in x (t). So that f_x_max is contained in y1 (t) at all, the clock rate f_clk of the clock signal CIk must be at least 2 * f_x_max (Nyquist criterion). However, a much higher sampling rate is desired, so that x (t) is resolved better in time and the error in y1 (t) and thus in y (t) is lower. However, a very high clock frequency f_clk has several problems:

The SDM must contain very high-frequency components, which makes its manufacture difficult and leads to high power consumption of the SDM itself, which reduces the efficiency of the system, especially when the transmission power of the PA is only in the range below 1 -10 watts, as in mobile Equipment usual.

The PA has to process pulses of width 1 / f_clk at y1 (t) to an approximately rectangular output signal, ie its bandwidth should be much higher than f_clk (desirable for good rectangular shape and thus good efficiency would be at least the 7th harmonic of the Fundamental wave f_clk still to be amplified, ie> = 7 * f_clk as band width). This is a requirement that often goes beyond the possibilities of semiconductor technology, for example, for f_x_max = 2GHz a value of f_clk = 16 * f_x_max would be technologically feasible, but already a bandwidth of 1 * f_clk = 32GHz would be very difficult for a PA realize, let alone a bandwidth of 7 * f_clk for a good efficiency.

Therefore, it appears problematic in the prior art to use an SDM for high signal frequencies, despite its attractive characteristics such as very high linearity and an efficiency of theoretically up to 100%. A remedy would be the use of a multi-bit SDM, in which the signal y1 (t) more than just 1 bit wide. Here, the error can be quantized and corrected more accurately than with 1-bit resolution in one cycle, so that less oversampling is necessary. But that is also problematic:

Although the ADC (105) does not need to be very linear because the SDM can correct its errors, the DAC (106) must be higher linear than the desired linearity of the overall system. This requires a very fast and linear DAC, which is technologically demanding and requires a lot of power dissipation if the data width is to be more than 1 bit.

The most serious problem with this approach is that it requires a switched PA with an input of more than 1 bit wide. Although one could build such a PA, it is itself a fast DAC, but a high output DAC, and thus much more difficult to achieve with sufficient linearity than the DAC (106) in the SDM because it is designed to switch high power with high efficiency while the DAC (106) in the SDM, the efficiency is less important. This would also require several power transistors as switches and a power combiner in the PA, which increase the cost of the PA and reduce its efficiency.

The object of the present invention is to provide an improved sigma-delta pulse length modulator and amplifier circuit with such a sigma-delta pulse length modulator.

The present invention overcomes the disadvantages described by employing an Mbit width multibit modulator in which the digital value range of a maximum of 2 ^M stages, rather than in amplitude stages, is converted into time stages that determine the duration of an output pulse. Since the behavior of the multibit modulator according to the invention has both properties of an SDM and of a pulse length modulator (PLM), the term sigma-delta-pulse length modulator (SDPLM) is used hereafter. Instead of the term pulse length modulator, the term pulse width modulator with identical meaning is used in this application. - A -

The object is thus achieved by a sigma-delta pulse length modulator according to claim 1 or according to claim 40 and an amplifier circuit according to claim 47. The remaining claims contain further embodiments of the invention.

According to a first aspect of the invention, the sigma-delta pulse length modulator according to the invention comprises a signal input with a differential stage whose first input is supplied with an analog input signal and which is designed to generate and output a differential signal corresponding to the difference of the signals present at its inputs A forward loop filter for converting the difference signal into an analog filter output signal having a signal value, an analog-to-digital converter connected downstream of the forward loop filter configured to convert the analog filter output signal to a digital converter output signal containing two or more parallel bit component signals. which in their entirety represent a digital value corresponding to the signal value assumed by the analog filter output.

Furthermore, the sigma-delta pulse length modulator according to the invention comprises a digital pulse length modulator to which the transducer output signal is supplied on the input side and which is designed to convert the applied transducer output signal into a digital modulator output signal, which consists of a single bit component signal and has a signal duration representing the digital value , which corresponds to the signal value assumed by the analog filter output signal, and a feedback loop which returns an analogue feedback signal dependent on the modulator output signal to a second input of the differential stage.

The implementation in time stages is carried out in preferred embodiments nonlinear to better meet the properties of PA.

Preferably, in the sigma-delta pulse length modulator, the feedback loop returns the modulator output signal to the second input of the differential stage via a digital-to-analog converter. In this case, the analog-to-digital converter is designed to carry out the conversion of the filter output signal with a predeterminable by an applied first clock signal first clock frequency.

More preferably, the sigma-delta pulse length modulator via a first clock input, a first clock signal at a first clock frequency and a second clock input, a second clock signal supplied to a second, compared to the first clock frequency increased clock frequency, wherein the pulse length modulator with the first and The pulse length modulator is configured to set at each clock event at the first clock input the count of the counter from a predetermined output value to the digital value corresponding to the signal value assumed by the analog filter output signal, the digital value for the digital one Value corresponding number of clock periods to keep the second clock frequency and then reset to an initial value.

In another embodiment, sigma-delta pulse length modulator is configured to generate and output the modulator output signal with a signal duration that is in a non-linear relationship to the digital value of the filter output signal.

Furthermore, in the sigma-delta pulse length modulator, the analog-to-digital converter is followed by an encoder which is designed to convert the converter output signal into a coded converter output signal which can be written by a non-linear mapping rule. The coder is an integral part of the sigma-delta pulse length modulator.

The sigma-delta pulse length modulator is preferably further configured to generate and output, based on the coded converter output signal, a modulator output signal having a respective signal duration that is in a nonlinear relationship to the digital value of the filter output signal and which is above a predetermined minimum amplifier duration dependent on the switched amplifier, and with a time signal interval between successive opposite signal edges of two temporally directly adjacent modulator output signals, which is above a predetermined, dependent on the switched amplifier temporal minimum signal spacing.

The coder of the sigma-delta pulse length modulator preferably includes a look-up table (LUT) which associates the possible values of the transducer output signal with each coded transducer output signal. In this case, the bit width of the coded converter output signal comprises a larger bit width than the bit width of the converter output signal. The encoder is further preferably designed to change the mapping rule for generating the coded transducer output signal during operation.

The sigma-delta pulse length modulator further preferably comprises a digitally adjustable delay element which generates a second signal with an adjustable delay with respect to the first signal from an applied first signal, and a digital circuit which links the first and the second signal to that their exit a third signal is applied whose pulse duration depends on the delay between the first and second signals. In this case, the digital circuit includes an RS flip-flop, which is set by the first signal and reset by the second signal, and at the output of the third signal can be tapped.

The digitally adjustable delay element of the sigma-delta pulse length modulator comprises a number of parallel delay elements having different fixed delays to which the first signal is applied and a multiplexer connected downstream of the delay elements and formed at its output depending on the value of the coded converter output signal output one of the delayed first signals as the second signal.

Furthermore, the digitally adjustable delay element of the sigma-delta pulse length modulator preferably comprises a delay-locked loop (DLL) which is designed to impart the number of different fixed delays in parallel to the first signal supplied to it on the input side and the differently delayed first signals to a corresponding number provide parallel signal outputs, and a delay element downstream of the multiplexer, which is designed to output at its output depending on the value of the coded transducer output signal each one of the delayed first signals as the second signal.

The encoder of the sigma-delta pulse length modulator is further preferably designed to change both the time of the rising edge and the falling edge of the modulator output signal in dependence on the input signal of the encoder. In this case, the coder is preferably designed to change the pulse duration of the modulator output signal in dependence on the input signal of the coder and at the same time modulate the phase of the modulator output signal with respect to the clock effective for the feedback loop of the sigma-delta pulse length modulator, e.g. B. to the clock of the analog-to-digital converter, to keep constant to a remaining residual error of the phase.

In an alternative embodiment of the invention, the first input of the differential stage of the sigma-delta pulse length modulator is preceded by an input digital-to-analog converter which is designed to convert a digital input signal present at its input into the analog input signal.

In this case, the digital input signal vector determining the digital input signal is provided with a digital input amplitude signal and either a digital input signal vector Input phase signal or a digital input frequency signal, the digital input amplitude signal of the differential stage and the other of the two digital signals of the input signal vector supplied to a clock generator which is adapted to derive from this other of the two digital signals of the input signal vector, a clock signal which the sigma Delta pulse length modulator is supplied.

In another embodiment of the alternative embodiment of the invention, the digital input amplitude signal from the differential stage and the digital input frequency signal from a digital input signal vector determining the digital input signal having a digital input amplitude signal and a digital input frequency signal are applied to a clock generator which forms is to derive from the input frequency signal a clock signal which is supplied to the analog-to-digital converter and the sigma-delta pulse length modulator.

The frequency of the clock signal effective for the feedback loop of the sigma-delta pulse length modulator, e.g. B. the clock of the analog-to-digital converter, according to the alternative embodiment of the invention is temporally variable and is from the instantaneous characteristics of the input signal of the sigma-delta pulse length modulator, z. B. from the time interval between two adjacent same-direction zero crossings, formed by a time-varying clock generator. In this case, the frequency of the clock signal is preferably formed by a frequency multiplier.

According to a further alternative embodiment of the invention, the sigma-delta pulse length modulator comprises a signal input with a digital differential stage whose first input is supplied with a digital input signal and which is designed to generate a digital difference signal corresponding to the difference of the digital signals present at their inputs a forward feedforward digital filter for converting the input signal to a digital filter output signal containing two or more parallel bit component signals representing in their entirety a digital value corresponding to the signal value accepted by the digital filter output signal and a digital pulse length modulator input to the digital filter output signal and is configured to convert the applied filter output signal into a digital modulator output signal, which consists of a single bit component signal and the one Signal duration, which is dependent on the signal value of the digital filter output signal. Furthermore, the sigma-delta pulse length modulator comprises a feedback loop which returns a digital feedback signal dependent on the digital filter output signal to a second input of the differential stage, comprising a digital input signal vector determining the digital input signal with a digital input amplitude signal and either a digital input signal. Phase signal or a digital input frequency signal, the digital input amplitude signal of the differential stage and the other of the two digital signals of the input signal vector is supplied to a clock generator which is adapted to derive from this other of the two digital signals of the input signal vector, a clock signal, the pulse length modulator is supplied.

In this case, the digital forward loop filter of the sigma-delta pulse length modulator is a D flip-flop whose D input is supplied with the digital difference signal and whose enable input is supplied with the clock signal of the clock generator.

The sigma-delta pulse length modulator is preferably configured to generate and output the modulator output signal with a signal duration that is in a non-linear relationship to the digital value of the filter output signal.

The forward loop filter of the sigma-delta pulse length modulator is preferably followed by an encoder which is configured to convert the filter output signal into a converter output signal encoder output signal which can be written by a nonlinear mapping rule. The encoder is an integral part of the sigma-delta pulse length modulator. The encoder output signal is preferably fed back to the second input of the digital differential stage.

In a further embodiment, the encoder output signal is fed to the input of a digital simulation of a sigma-delta pulse length modulator downstream switching amplifier and / or reconstruction filter and fed back from the output of this digital simulation to the second input of the digital differential stage.

According to a further aspect of the invention, the amplifier circuit comprises a signal input, which is followed by a sigma-delta pulse length modulator as described above, a digitally switched amplifier, which is driven by the output signal of the sigma-delta pulse length modulator and which is designed, the output signal of the sigma-delta pulse length modulator and output as an amplifier output signal. Furthermore, the amplifier circuit comprises a reconstruction filter to which the amplifier output signal is supplied and the is designed to filter the amplifier output signal such that at the output of the reconstruction filter an analog output signal is applied, which is amplified relative to the input signal applied to the signal input.

In this case, the feedback loop of the amplifier circuit preferably returns a feedback signal derived from the amplifier output signal via a digital-to-analog converter to the second input of the differential stage.

In one embodiment of the invention, the feedback loop of the amplifier circuit directly feeds back a feedback signal derived from the analog output signal of the reconstruction filter to the second input of the difference stage.

The feedback signal is preferably derived by means of a capacitive or inductive coupling from a terminal in the digitally connected amplifier or reconstruction filter.

In a further embodiment of the invention, in the amplifier circuit the switched amplifier and the reconstruction filter are not monolithically integrated with the sigma-delta pulse length modulator, but instead form separate circuit modules. Furthermore, the feedback loop is monolithically integrated with the sigma-delta pulse length modulator and includes a first replica circuit of the switched amplifier configured to down-scale the behavior of the switched amplifier during operation of the amplifier circuit, and a second replica circuit formed in FIG Operation of the amplifier circuit to replicate the behavior of the reconstruction filter downscaled.

In this case, the first and the second replica circuits can be combined in a common replica circuit. The first and second replica circuits and the common replica circuit are preferably digital circuits.

More preferably, in the amplifier circuit, the sigma-delta pulse length modulator is configured to generate the modulator output signal with a signal duration gradation between adjacent signal values, wherein a signal duration step is less than a minimum delay time of an active amplifier stage.

Hereinafter, further embodiments will be explained with reference to the figures. As far as the figures show amplifier circuits with a sigma-delta pulse length modulator, it is understood that the particular embodiment of the sigma-delta pulse length modulator can also be combined in conjunction with other circuit components to implement a function other than that of an amplifier.

Show it:

Fig. 1 block diagram of an amplifier circuit with a sigma-delta modulator

(SDM) and an analog input interface (prior art),

2 a block diagram of an amplifier circuit having a first exemplary embodiment of a sigma-delta pulse length modulator according to the invention and an analog input interface,

2 b shows a block diagram of an amplifier circuit according to FIG. 2 a with a second embodiment variant of the inventive sigma-delta pulse length modulator with modified feedback, FIG.

2c block diagram of a third embodiment of an amplifier circuit according to FIG. 2a with a third embodiment variant of the inventive sigma-delta pulse length modulator with modified feedback, FIG.

2d shows a block diagram of a fourth embodiment of an amplifier circuit according to FIG. 2a with a fourth embodiment variant of the inventive sigma-delta pulse length modulator with modified feedback, FIG.

FIG. 3 shows a block diagram of an amplifier circuit according to FIG. 2a additionally with an encoder in the signal path of the sigma-delta pulse length modulator according to the invention, FIG.

4 a block diagram of a digitally controllable pulse width modulator (DPWM),

4b shows a circuit example of a DPWM according to FIG. 4a, FIG.

5 a block diagram of a further embodiment of a DPWM,

5b block diagram of a second variant of a DPWM according to FIG. 5a,

5c block diagram of a third variant of a DPWM according to FIG. 5a,

6a shows an example of a chain of non-linear amplifier stages of a conventional delay-locked loop (DLL), FIG. 6b shows a chain of non-linear amplifier stages according to FIG. 6a, in which a plurality of series-connected passive delay elements are connected in parallel with each amplifier stage, FIG.

6c shows a chain of non-linear amplifier stages according to FIG. 6b, in which the parallel circuit of the passive delay elements connected in series to each amplifier stage is separated, FIG.

FIG. 6d shows a chain of non-linear amplifier stages according to FIG. 6c, in which the chains of the passive delay elements are extended, FIG.

7 shows a block diagram of an amplifier circuit according to FIG. 3, wherein the sigma-delta pulse length modulator according to the invention is additionally provided with a time-variable clock generator,

8 is a diagram of output waveforms of a 16-output DLL;

9 shows a diagram of output signal curves of a DPWM according to FIG. 7

Using a DLL with 16 outputs,

10 shows a circuit with a multiplexer of a DPWM and an edge-triggered RS flip-flop,

11 shows a block diagram of an amplifier circuit according to FIG. 7, wherein the sigma-delta pulse length modulator according to the invention is additionally provided with a frequency divider,

12 shows a circuit with a multiplexer of a DPWM, an edge-controlled RS flip-flop and a modified look-up table (LUT),

FIG. 13 is a graph showing output waveforms of a DPWM shown in FIGS. 11 and 12 when using a DLL having 16 outputs. FIG.

14 shows a block diagram of an amplifier circuit with a first alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface,

15 shows a circuit with a frequency synthesizer, a multiplexer of a DPWM and an edge-triggered flip-flop, 16 shows a block diagram of an amplifier circuit with a second alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface,

17 shows a block diagram of an amplifier circuit with a third alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface,

18 shows a block diagram of an amplifier circuit with a fourth alternative embodiment of a sigma-delta pulse length modulator according to the invention and a digital input interface.

A first exemplary embodiment of an amplifier circuit with a sigma-delta pulse length modulator according to the invention is shown schematically in FIG. 2 a with reference to a block diagram. Compared with FIG. 1, a component has been added here: A digitally controllable pulse width modulator (DPWM, 201) generates from a binary signal yd (t) with M1 bit width, ie with M1 parallel bit component signals, an integer with a value range of Z1 values represent with Z1 <2 ^M1 , an output signal y1 (t) with 1-bit width, where the pulse width (the duration of the active phase of the signal, so the period of a clock period in which contiguous y1 (t) = '1', also pulse duration, signal duration) of y1 (t) is not constant, unlike in FIG. 1, but is determined to be variable in time by the numerical value of yd (t). If the beginning of the pulse duration is defined by a clock, the pulse interval (the duration of the pause between the pulses) changes in the opposite direction to the pulse duration: a shorter pulse duration leads to a greater pulse interval.

This can be done, for example, with the aid of a counter which accepts the input value yd (t) for each clock CIk of the frequency f_clk and sets the output value to '1' for yd (t) clocks of the frequency Clk2, and then sets it to '0' until the next clock CIk. This interprets the binary vector at yd (t) as a positive integer with Z1 possible values, which specifies the pulse duration. If all 2 ^M1 maximum possible binary values of yd (t) are to correspond exactly to one pulse duration (one-to-one mapping), then the frequency f_clk2 must be at least a factor 2 ^M1 higher than f_clk in the case of realization by a counter.

The operation of the system in Fig. 2a is similar to that of the system in Fig. 1 with a 1-bit ADC in Fig. 1, but results in higher linearity. Although in Fig. 2 the ADC has M1> 1 bit width (eg 5 bits instead of 1 bit in Fig. 1), y1 (t) is also a 1 bit wide signal, and the DAC can be a 1-bit DAC and the PA a 1-bit PA, making it much easier to satisfy its linearity requirement than a multi-bit DAC or multi-bit PA.

In contrast to FIG. 1, the instantaneous pulse width y1 (t) is variable and is directly determined by the integer number with Z1 possible values formed by the M1 bits of the multi-bit signal yd (t) at the output of the ADC. In the case of a linear counter in the DPWM, this is a linear representation of yd (t) by the pulse duration of y1 (t) and thus a better simulation of the signal than a 1-bit quantization, which corresponds to a low distortion.

Thus, the SDPLM in Fig. 2a is a multi-bit SDM in which the multi-bit value yd (t) is represented linearly by the pulse duration. Already that is an extension of an SDM according to the invention. It allows a higher resolution in the SDM loop without the need for a higher clock for the ADC. It also allows the use of a 1-bit DAC, which can be very linear. It also allows in an amplifier circuit the use of a conventional PA with 1 bit input width and relatively low switching frequency f_clk_f_clk2. In effect, this system is an SDM with additional features of a known pulse length modulator (PLM), ie a hybrid system with features of SDM and PLM. It combines the advantages of an SDM (error feedback and thus linearization of the components in the forward branch) with those of a PLM (finer time quantization than 1 / f_clk, lower power loss than an SDM operated with f_clk2).

A further advantageous variant of this is shown in FIG. 2b: Here, the error feedback and thus linearization concerns not only the ADC but also the PA by tapping the feedback to the PA, e.g. via a loose coupling (210), which draws very little power from the PA. The DAC (106) can then be omitted.

Also, the reconstruction filter (108) can be included in the error feedback and linearized, as indicated in Fig. 2c.

The variants in Figures 2c and 2d have a feedback loop that extends from loop filter (104), ADC (105) and DPWM (201) through PA (107) and reconstruction filters (108) back to summation point (103) and loop filter (104) , While summation point (103), loop filter (104), ADC (105), and DPWM (201) are all relatively easy to integrate, PA (107) is rarely (at low power) and reconstruction filter (108) after the current state of the art almost never. Thus, the feedback loop in Figures 2c and 2d includes multiple components outside of an integrated one Circuit, which together with their connection technology have considerably larger dimensions than an integrated circuit with summation point (103), loop filter (104), ADC (105) and DPWM (201) and therefore require geometrically and electrically relatively long signal paths. This can lead to problems in the feedback loop, especially affecting its stability, especially when used for high signal frequencies, where signal propagation times can be very significant.

Therefore, another variant according to the invention is proposed in FIG. 2 d, in which the entire feedback loop runs within a monolithically integrated circuit (220). Additional components are introduced for this purpose: A replica PA (207) simulates the PA (107) in its behavior as linearly scaling as possible, and a replica reconstruction filter (208) simulates the reconstruction filter (108) as linearly as possible in its behavior , If the PA (107) is, for example, a large switched MOS transistor with 40 V operating voltage as an external component with a wire-wound output transformer at the drain, then the replica PA (207) can be a much smaller switched MOS transistor with 2.5 V operating voltage be as a monolithic integrated device with a monolithically integrated output transformer at the drain.

However, the replica PA (207) can also have a completely different structure than the PA (107), which only when viewed from the outside (as a black box) behaves in a linear scaling approximately like the PA (107), but in scale reduction, so that a monolithic integration is possible, so z. B. with 10 mA drain current instead of 10 amps.

Similarly, the replica reconstruction filter (208) may have a very different structure than the reconstruction filter (108), which is only externally (in black box) approximated to the reconstruction filter (108) in linear scaling, but scaled down, such that a monolithic integration is possible. In this way delays are avoided by long signal paths in the entire feedback loop, and a higher stability of an SDPLM or a higher maximum signal frequency can be achieved.

These solutions according to the invention with the common approach of a multi-bit realization of an SDPLM by pulse length modulation already represent an improvement over a pulse length modulator (PLM) and also an SDM. However, they still have a common disadvantage typical of PLM: very small values yd (t) not equal to 0, but close to 0, produce pulses of very short duration (very short term) Values of '1' at the input of the PA, minimum duration 1 / f_clk2). As described above, these are a difficult problem for the efficiency and bandwidth of the PA since a real PA can only produce pulses of finite duration. Analogously, very large values yd (t) close to 2 ^M1 can lead to pulse pauses of a very short duration, ie the same problem in the inverted direction (very short-term values of '0' at the input of the PA).

This disadvantage overcomes a further improvement according to the invention in that the output signal of the ADC is used in a non-linear manner for controlling the pulse duration such that pulse durations of '0' or '1' do not occur below a minimum duration t_min_0 or t_min_1. In the simplest case, those ADC output values yd (t) which result in too short pulse durations (t (y1 (t) = T) <t_min_1) are simply set to 0 and thus the short pulse is suppressed; Analogously too short pulse pauses are likewise suppressed by setting the input of the DPWM to the maximum value and thus outputting a permanent '1' at the output of the DPWM. In the general case, the ADC output values yd (t) are mapped to the input values of the DPWM ye (t) so that the DPWM receives no input values which would result in too short pulse durations or pulse pauses for the PA.

FIG. 3 represents an exemplary exemplary embodiment for this purpose, representative of numerous possible forms of implementation. Here again, the return of the DPLM in front of the PA is assumed as in FIG. 2a. The other return variants symbolically indicated in FIGS. 2b to 2d can also be used, but have not been shown here for the sake of simplicity. Another additional component, an encoder (302), for example a look-up table (LUT), converts the M1 bit wide output of the A / D converter (ADC) into a now M2 bit wide input signal of the DPWM, the new bit width M2 may be equal to or different from M1. Even with the same bit width M2 = M1, the integer value range of the output values ye (t) of the encoder (302) of Z2 possible values may be equal to or different from the integer value range of the input values yd (t) of the encoder (302) of Z1 possible values. The advantage of this additional component is that now any mapping of the input values yd (t) of the encoder (302) into output values ye (t) of the encoder (302) allows. In the simplest case, this coder (302) can have the following function:

I 0 for yd (t) <ydO ye (t) = I yd (t) for ydO <= yd (t) <= yd1 (1)

I yejnax for yd (t)> yd1 In this case, it is assumed that the DPWM is designed so that it outputs a pulse duration of 0 for an input value ye (t) = 0, thus suppressing this pulse, and outputs a pulse duration of 1 / f_clk for an input value ye (t) = ye_max , ie sets this pulse to '1' for the entire cycle duration from 1 / f_clk, ie suppresses the pulse pause. This can be z. For example, if the DPWM contains a counter that resets to 0 after each new clock at CIk the count incremented to Clk2 with each clock and holds the output of the DPWM at '1' as long as the count is less than the input value of the DPWM, and ye_max is greater than the maximum count achievable in one clock period of CIk.

An example of such a DPWM is shown in FIG. 4a: A Clk2 clocked down counter (401) is tested for output 0 with logic (402), and when 0 is reached, an edge triggered RS flip flop (403) is reset at the next clock at CIk receives a short set pulse, which also causes the counter (401) to reload the current value ye (t). The clock frequency f_clk2 is chosen to be f_clk such that at the maximum value of ye (t) (a value of 15 for the 4-bit backward counter in FIG. 4) during a period 1 / f_clk, the count can not reach 0 (e.g. Eg f_clk2 <15-f_clk). The edge-triggered RS flip-flop (403) is set by a 0-1 edge at input S (i.e., the positive output Q_P is 1, the inverted output Q_N is 0) and is reset by a 0-1 edge at input R.

Fig. 4b shows a circuit example in this regard: The set pulse stops its effect when it has passed through the chain of 3 inverters, so that from then on the circuit is free for a reset pulse, which also terminates its effect when the chain of 3 inverters until it becomes inactive again the set and reset signal. The duration of the phase Q_P = 1 is thus determined by the time interval between the 0-1 edge at the input S and the 0-1 edge at the input R. In addition, the short pulse shortened set signal SetPulse is coupled out and is available for loading the backward counter (401). Further circuit examples of such a pulse-controlled R-S flip-flop are known, for example with a clocked circuit instead of the inverter chain.

Now, for the inventive use of the encoder (302), ydO and yd1 must also be chosen according to the properties of the PA such that t_min_1 = ydθ / f_clk2 forms the smallest pulse duration which the PA can still transmit with sufficient efficiency, and analogously t_min_0 = (ye_max -yd1) / f_clk2 satisfies the smallest satisfactory from the PA portable pulse pause duration. Both can also be identical, depending on the execution of the PA: t_min_0 = t_nnin_1.

The function in (1) thus has a linear range ye (t) = yd (t) for mean values of yd (t). In this area, the SDPLM in Fig. 3 works like the SDM in Fig. 2a. In addition, the function in (1) has two stages at both ends yd0 and yd1 of this range, which are formed by jumps of 0 and the maximum value, respectively. With this strong nonlinearity, the signal is greatly distorted at values yd (t) of the ADC outside the linear range. This distortion generates errors, but these are returned by the feedback of the SDPLM and result in a correction in the next following value yd (t). Also, the nonlinear distortion in (1) is still significantly more linear than a purely binary distinction of a conventional SDM that can only set whole pulses of durations 1 / f_clk at the output to '1' or '0'.

A conventional SDM can be seen as a special case of an extended SDPLM according to the invention according to FIG. 3 with a special variant of the function in (1), which results when ydθ> yd1 is selected, and thus the middle range disappears, and thus only pulses the maximum duration 1 / f_clk or no pulses can be output by the DPWM. With such a choice ydθ> yd1, the general function in (1) degenerates into a comparator function which generates a 1-bit value from the multi-bit value of the ADC to give an SDM behavior that is 1-bit -SDM corresponds. The more the values ydO and yd1 are apart (with ydθ <yd1), the more value steps for controlling the pulse length are possible, and the more a multi-bit SDPLM according to the invention according to FIG. 3 gains in resolution over a conventional 1-bit SDPLM. SDM according to FIG. 1.

The maximum number of possible pulse lengths Z2 at the input of the PA (107) in a multi-bit SDPLM according to the invention according to FIG. 3 when using (1) is slightly less than the maximum value of the number of stages Z1 in a multi-bit SDPLM according to the invention 2a, because the encoder (302) has excluded those of the Z1 step numbers which can not be transmitted "well enough" by the PA (107) (ie with insufficient efficiency or linearity) PA now only needs to transmit pulse lengths that are "good enough" for the PA. The nonlinearity in (1) thus leads to Z2 <Z1 by choosing yd0> 0 and yd1 <ye_max. However, (1) is only one of the possible variants of the non-linear mapping of yd (t) according to the invention onto ye (t). Clearly, the effect of the SDPLM according to the invention from the point of view of the PA can be explained as follows: A switched PA has a technologically limited maximum slew rate of the output signal. In order to produce an output signal which is still sufficiently similar to a rectangle (and thus still sufficiently close to the ideal efficiency of 100%), a minimum pulse duration at the input must not be undercut, just as a minimum duration of a pulse -Break. As well as the requirement for sufficiently high efficiency, a requirement for a sufficiently linear conversion of an input pulse length of the PA into an (ideally equally large) output pulse length of the PA can lead to a minimum pulse duration at the input must not fall below, as well little like a minimum duration of a pulse break. The permissible values for this minimum pulse duration or pulse pause duration are thus determined by both PA criteria, efficiency (efficiency) and linearity on the basis of the switching characteristics of the PA, z. B. his slew rate, given. With a conventional SDM according to FIG. 1, a PA is thus driven with pulses of this minimum duration if it is to operate at the upper limit of the temporal resolution. The maximum clock period of a conventional SDM then corresponds to the reciprocal of this minimum pulse width. Thus, the maximum clock period of a conventional SDM is severely limited by the PA. But a property of the PA is not used: Even a very small extension of the pulse duration at the input leads to a defined (almost linear) small extension of the pulse duration at the output, and that with a temporal step size, which is limited only by noise down and not by the bandwidth of the PA. Although the total width of the pulse at the PA input must not be less than a relatively large minimum value (eg, 300 ps), this pulse duration may be varied in very fine steps whose step size may be much smaller than this minimum pulse duration.

So you can control the PA with different long pulses of very fine time increment (eg 5 ps), provided that the pulse duration and the pause duration remain within the permissible range. This fine step size in the linear range (from yd0 to yd1) results in multi-bit resolution quantized SDPLM behavior, which is equivalent to a 1-bit SDM with a much higher clock rate (eg, 1 / ( 5ps) = 200GHz). Such a comparable much faster conventional SDM according to FIG. 1 would be technologically difficult to implement and would in particular far exceed the PA in terms of the bandwidth of the PA. On the other hand, a conventional PLM uses the variable-pulse-width property, but it has no feedback that could compensate for a nonlinear characteristic as defined in (1), and therefore requires a linear characteristic of the conversion. Amplitude in pulse duration without the possibility to exclude certain pulse durations, and as a result a PA with very high bandwidth to process even very short pulses.

In a numerical example of an embodiment of the simple case described by the function in (1), M1 = M2 = 4, f_x_max = 1GHz, f_clk = 4GHz, f_clk2 = 64GHz, ydθ = 5, yd1 = 10. The ADC then operates at 4 gigasamples / second (4 GS / s) and produces 4-bit values (from 0 to 15, Z1 = 16) that are linearly converted into identical values ye = yd in the range of 5 to 10, the one variable pulse width from 5/15 to 10/15 of the cycle duration 1 / f_clk. At ADC values yd (t) <5 no pulses are generated (y1 (t) remains '0' over the cycle duration), at values> 10 a continuous pulse is generated (y1 (t) remains '1' above the cycle time). The DPWM then generates pulses of duration (0, 5..10, 15) / 15 - 1 / f_clk, ie in total Z2 = 8 values. This is six times more than a conventional binary SDM with binary PA, and despite the finer grading, a binary PA can still be used in the inventive solution. The minimum pulse width which the PA has to process here is 5 / (15-f_clk) = 1 / (3-f_clk) compared to 1 / f_clk for the conventional binary SDM and 1 / (8-f_clk) for a linear multibit SDPLM of Fig. 2 with 8 stages. Thus, for equal efficiency, the bandwidth of the PA must be three times higher (= (3-f_clk) / f_clk) than with a conventional binary SDM, but the grading of the output value is seven times higher (seven steps of the pulse duration - except 0). instead of a step). The requirement for the bandwidth of the PA is relaxed compared to Fig. 2a by a factor of 3/8 (= (3-f_clk) / (8-f_clk)), so the PA can get along with 37.5% of the previous bandwidth, or at the same Bandwidth of the PA, the clock rate f_clk can be 8/3 higher than in FIG. 2a. This would correspond to a 8/3 faster PA with unchanged structure in Fig. 2a, so an increase in PA bandwidth to 267%. An encoder (302) is certainly a much less expensive component than a 267% accelerated PA and also monolithically integrated.

Since the ADC values are in any case only used in a subarea, the ADC can in another variant also be embodied as an ADC with a lower resolution M1 <M2, which does not even dissolve the edge regions suppressed by the encoder (302). In the previous numerical example, seven stages were linearly coded, requiring only a 3-bit ADC. Then M1 = 3 (Z1 <8) and M2 = 4 (Z2 <16). If the maximum range of ADC values is used with Z1 = 8, the following nonlinear mapping results, for example: The ADC values yd (t) = 1 to 6 correspond to ye (t) = 5 to 10; yd (t) = O gives ye (t) = 0 and yd (t) = 7 gives ye (t) = 15. ye (t) thus also includes 8 values used from the range 0 to 15, ie Z2 =. 8 In this case, the non-linearity of the encoder is defined differently than in the example of (1), but there is still a linear range for middle values.

Instead of a reduction of the ADC resolution M1, the value for M2 can be increased even with a constant resolution M1, if a counter with a resolution M2> M1 is easier to implement than an ADC with a higher resolution than M1, which is usually the case. M2 is technically usually less limited than M1. Thus, the number of stages and thus the signal quality of the system can be further increased.

A linear mapping such as ye (t) = yd (t) in the middle region of (1) is not absolutely necessary for an embodiment according to the invention, an approximately linear mapping is sufficient since the linear feedback of the SDPLM can correct the nonlinear errors. A more general formulation of the function of the encoder (302) in Fig. 3 according to the invention is that yd (t) is mapped to ye (t) with the encoder (302) such that pulse durations '0' and '1' below, respectively a minimum duration t_min_0 or t_min_1 not occur, where t_min_0 and t_min_1 are defined by the desired linearity of the system and efficiency of PA based on the PA speed. In this case, a fixed image with a real look-up table is not absolutely necessary; a time-varying image in the encoder (302) is also possible, e.g. switching between several functions as a function of the input signal as long as pulse durations or pulse pauses below a minimum duration t_min_1 or t_min_0 do not occur.

Even this condition can be further generalized in a statistical form according to the invention to the effect that such pulse durations or pulse pauses below a minimum duration t_min_1 or t_min_0 do not occur only in the vast majority of the pulses. Indeed, it is possible to admit some relatively few such pulses, which then cause the PA to currently operate at a lower than the required efficiency, but since the efficiency is a medium size, the efficiency averaged over many pulses can still be sufficiently high if such very short pulse durations or pulse pauses occur only rarely enough. The same applies to the nonlinearity, whose share of the average total power of the signal must then be sufficiently low. This allows for a time varying algorithm for the encoder (302) that is much more complex than a lookup table. This algorithm could, for. B. be designed so that the middle range in (1) is dynamically extended as long as the average efficiency (or the mean linearity or the error vector magnitude EVM) does not fall below a predetermined value. This gives the middle At times even more stages and even lower errors in the signal reconstruction, ie an even higher signal quality.

A simple embodiment of this more complex algorithm for the LUT component (302) could be e.g. For example, measure the instantaneous temperature of a power transistor of the PA (which can serve as a negative measure of PA efficiency) and, at higher temperature, decrease the midrange (ydO and yd1 approach each other) and increase that range at lower temperature (Remove ydO and yd1 from each other by decreasing ydO or increasing yd1). This optimizes the signal quality and ensures a desired average efficiency, a desired signal quality and safe operation of the PA.

With an execution of the DPWM based on a CLk2 clocked counter as in FIG. 4, the maximum number of stages of the DPWM is limited by the maximum count frequency of the counter. This forms a limit to the time quantization of the pulse width at the input of the PA. Is z. If, for example, the PA is still able to produce a defined change in the energy of the approximately rectangular pulse at the output y2 (t) when the pulse duration at its input y1 (t) is changed by 1 ps, a maximum counting frequency of 1 / (1 ps) = 1000 GHz for a DPWM according to FIG. 4, in order to sufficiently finely quantize the pulse duration. Such a time resolution of z. B. 1 ps for a PA can be a realistic value in today's semiconductor technologies, because the time step can be reduced to the noise limit, below which no deterministic effect of a changed pulse duration is more detectable. Such a clock frequency f_clk2 of e.g. 1 THz for the DPWM, however, is hardly achievable in today's technologies, since the upper clock frequency by the minimum transit time of a signal by a logical unit (logic and memory, in the minimal case of a ring counter a single flip-flop) is determined, usually clear is greater than the time uncertainty due to noise.

An optimal utilization of the possible time resolution of the PA therefore requires a different DPWM than a DPWM based on clocking with f_clk2 as in FIG. 4.

Fig. 5a shows another embodiment of the DPWM. Here, the duration of the output pulse y1 (t) is not determined by a counter, but by a digitally adjustable delay (501), which resets an RS flip-flop (503) delayed here, after it has been derived by a clock derived from the clock CIk Pulse was set. For a digitally adjustable delay, a number of implementations are known, for example as indicated in Fig. 5a by a DAC (501 b) followed by an analog adjustable delay (501a) are formed. Here, the input signal of the DAC (501b) is the input signal of the DPWM ye (t).

Another variant, shown in Figure 5b, uses a number N = 2 ^M of delay-connected delay units of different delay, of which exactly one is selected by a downstream multiplexer. Here, ye (t) is the input signal of the multiplexer that determines the selection of the delay unit.

Another variant, shown in Fig. 5c, uses a delay-locked loop (DLL) to generate N = 2 ^M different delay stages of the clock signal, of which exactly one is again selected by a downstream multiplexer. Again, ye (t) is the input to the multiplexer, which determines the selection of the delay level.

Further variants for a digitally adjustable delay are known as the prior art.

The advantage of such an embodiment of the DPWM, as illustrated by way of example in FIGS. 5a to 5c, is that the delay and thus the pulse duration can be changed in considerably finer time steps than in the case of clocking. As a result, the fine possible time resolution of the PA for its pulse duration at its input y1 (t) can be exhausted, and the signal y2 (t) can represent the signal x (t) with higher quality.

In a further improved variant according to the invention, the number of delay stages and thus the temporal resolution of a DLL, which is usually based on chains of (often differential) non-linear amplifier stages, can be greatly increased. In Fig. 6a, a chain of such amplifier stages of a conventional DLL is shown by way of example. If the amplifier stages (602) consist of differential amplifiers, they have real differential inputs and outputs, of which only one is shown here. The temporal resolution of the DLL is formed by the delay of the signal between two adjacent taps (603). The delay is dictated by the speed of the amplifier stages used. In Fig. 6b, the temporal resolution is improved by a factor of 4 by connecting in parallel to each active amplifier stage (602) a number (here 4) of series-connected passive delay elements (604). Such passive delay elements can have an almost arbitrarily small delay and thus allow an almost arbitrarily fine temporal resolution of the DLL. In Fig. 6b, the series-connected passive delay elements (604) both input and output side are connected in parallel to the associated active amplifier stage (602). Thus, the delay from the input to the output of the active amplifier stage (602) is changed and determined in part by the passive elements. This can be an advantage if a high reproducibility and close tolerance of the delay are desired because the delay of passive elements can usually be made tighter tolerated than that of active elements. If, on the other hand, the focus is on a wide tuning range of the DLL, then the connection can be separated on the output side, as shown in Fig. 6c. Here, the delay from input to output of the active amplifier stage (602) is determined solely by the active amplifier stage (602). If a wide range of delay adjustment of active amplifier stage (602) is to be made greater than the delay of a single passive delay element (604), the chain of passive delay elements (604) may be extended as shown in Figure 6d to cover the entire range of necessary intermediate steps on delays.

If such a design of a DLL is used symbolically as shown in FIGS. 6b to 6d, then the delay and thus the duration of the pulse can be changed in considerably finer time steps with a DPWM according to FIG. 5c, so that the possible time resolution of the PA for whose pulse duration at the input y1 (t) it can be used even finer, and the signal y2 (t) can represent the signal x (t) with even higher quality.

A further improvement is possible by the SDPLM not with a fixed clock frequency f_clk = const. is operated, but the current frequency f_clk is selected as a multiple of the input frequency. The operation of an SDM with time-variable frequency of the clock is not common practice. The usual mathematical foundations of an SDM are based on the z-transformation, which requires a constant clock frequency. Nevertheless, they can be used approximately in this variant according to the invention, if the bandwidth of the signal x (t) is much smaller than its carrier or center frequency, which is usually the case in telecommunications.

Here, the signal (702) for timing the ADC and the DPWM is generated by a time-varying clock generator (701) from the current frequency or current period of the input signal x (t), as shown in Fig. 7 symbolically. The instantaneous period is a time-varying form of the constant period defined for purely periodic signals. The time interval between two adjacent equidirectional zero crossings (eg both from x (t) <0 to x (t)> 0) of the input signal x (t) can be regarded as the instantaneous period. The clock generator (701) may include, for example, a clock multiplier with a downstream phase shifter. Thereby For example, the timing of sampling the input signal x (t) is phase locked to x (t) itself, and the phase shifter can adjust this phase difference deltaPhi. This is especially useful for small values of oversampling factor OVR, that is, if only a few samples are executed per period of x (t). If the sampling times lie near the zero crossing of x (t), then the signal is reconstructed very poorly with a small OVR. In the worst case with deltaPhi = 0, for example, x (t) is sampled to phase 0 and to the phase 180 °, and yd (t) = 0 is obtained. By setting deltaPhi = 90 °, x (t) becomes z. B. sampled to the phase 90 ° and to the phase 270 °, and one obtains at yd (t) the maximum information, namely the amplitude of the peak value of x (t). Such a clocking of the system with a clock derived from x (t) is also useful for larger OVR, because it allows you to set the sampling times so that they represent the signal x (t) as well as possible and the informationless zero crossings are rarely or not scanned , In a conventional clock unconsolidated to x (t) CIk, the instantaneous information content of yd (t) would be indeterminate and statistically justifiable, so that a high OVR is needed to replicate the signal with sufficient accuracy. This improvement according to FIG. 7 therefore permits a lower OVR and thus a higher maximum frequency of the input signal given technologically given maximum sampling clock f_clk_max. This can be a significant improvement because, for example, with a reduction in the required OVR from 4 to 1, the fourfold carrier frequency at x (t) can now be processed and other fields of application for a PA with SDM or SDPLM are possible, Especially in the areas above 1 GHz, which are particularly interesting for telecommunications, but for switched PA because of the high required OVR hardly came into question.

The clock multiplier can be constructed, for example, from one or more clock doublers connected in series. For clock multipliers, in particular clock doublers, a number of basic circuits, also known as frequency multipliers or frequency doubling are known. An example of clock multiplication by a factor T is to separate the instantaneous phase information of x (t) (containing the frequency information) from the amplitude information by connecting a comparator or limiter amplifier downstream of x (t) and this signal xs (t), which may ideally be formed by the sign function sgn () with xs (t) = sgn (x (t)), then to control a phase-locked loop (PLL) with integer divisor (integer N-PLL) with the fixed divider factor T. use, where the bandwidth of the PLL must be large enough for the bandwidth of x (t). Another known possibility is to use a DLL for clock multiplication. First, the DLL is constructed so that its total delay in the center of the delay control without delay-locking is approximately K clock periods of the center frequency of x (t), where K is an integer by which the clock is to be multiplied. In the case of the DLL, this delay is exactly K clock periods of the center frequency of x (t). This DLL is controlled with x (t) and is synchronized in the locked state phase locked with x (t). Fig. 8 shows an example of the output signals of a DLL with N = 16 outputs. The output Q16 is held in phase lock by the control loop to the input D (= xs (t)). Now this DLL is followed by a logic block linking taps of the DLL to produce a clock signal at the desired multiple clock frequency by generating a total of K output clock pulses at each period of the input clock on signal D in FIG , In Fig. 8 K = 2 is selected.

If a DLL is also used for the DPWM in FIG. 7, signals are produced at the output y1 (t) of the DPWM as shown in the example in FIG. For the sake of simplicity, a DLL with N = 16 outputs is also shown here. Real, however, the number of taps can be much larger, in order to achieve a finer time resolution. A DLL with a very large N can be constructed according to FIGS. 6b to 6d. FIG. 9 shows five examples of possible output signals:

For yd (t) <ydθ, ye (t) = 0 and thus also y1 (t) is constant at '0'. This can be achieved in a structure according to Fig. 7 and a circuit similar to Fig. 5c by the set signal S of the edge-triggered RS flip-flop (403 or 503) is kept constant at '0'. In this case, the structure of the DPWM of Fig. 5c is somewhat widened, as shown in Fig. 10. A logical block detects the two cases ye = 0 and ye = ye_max and generates the corresponding signals ye_is_0 at ye = 0 and ye_is_max at ye = ye_max. This leaves the RS flip-flop reset at ye = 0 and y1 (t) constant at '0' (5th signal from the bottom in FIG. 9).

For yd (t)> yd1, ye (t) = ye_max and thus y1 (t) should be constant at '1'. This can be achieved in a structure according to FIG. 7 and a circuit similar to FIG. 5 c by keeping the reset signal R of the edge-triggered RS flip-flop (403 or 503) constant at '0' as shown in FIG. 10 is shown. This leaves the RS flip-flop set and y1 (t) constant at '1' (1st signal from the bottom in FIG. 9).

For the other values of yd (t), ye (t) is in a definable intermediate range, for example between 5 and 11. Which limits are chosen for this range, According to the invention, as described above, depends on which minimum and maximum pulse duration are allowed for the given PA and its efficiency and linearity. The pulse duration at y1 (t) thus varies from 5/16 (4th signal from below in FIG. 9) over 1/2 (3rd signal from below in FIG. 9) and 1 1/16 (2nd signal from below in Fig. 9) of the entire instantaneous clock period of CIk. In these cases, the set signal S is formed by CIk (= D in Fig. 9), while the reset signal R is selected by ye (t) from the multiplexer of the taps of the DLL.

The pulse duration is thus varied depending on the amplitude of x (t), which is determined according to FIG. 7 phase-locked to x (t) in the permissible limits for the PA. The nonlinearities at the end regions as well as the further errors resulting from quantization and other errors in the forward branch are fed back via the DAC (106) and compensated in the following periods.

Since the sampling now takes place in phase with x (t) and the amplitude of x (t) normally only with the bandwidth of x (t), i. With the modulation bandwidth, not with the much higher center frequency or carrier frequency of x (t) changes, this phase-locked sampling at the ADC can also be done less frequently. This possibility is shown by way of example in FIG. 11: An additional frequency divider divK (1101) with the fixed divider ratio K reduces the sampling rate of the ADC. If the DAC is clocked, its clock frequency can also be reduced, as shown in FIG. 11. This relaxes the requirements for ADC and DAC, which is e.g. a slower and thus higher resolution ADC allowed. Thus, the width M1 of yd (t) becomes larger, allowing a larger width M2 of ye (t). The DPWM then receives constant values over several clock cycles of CIk at the input and generates - furthermore clocked with the undivided CIk - a duty cycle constant over K periods at y1 (t) for the PA. But with K> 1, the feedback loop slows down, so that the errors are no longer fed back to every clock on CIk, so that the ability of the SDPLM to linearize is partially lost. Thus, for K, an optimal compromise for the particular implementation of the system, e.g. Between the increased accuracy by larger M1 and M2 and the reduced accuracy through less frequent feedback.

The pulse width modulation as shown, for example, in Fig. 9 still has a shortcoming, which comes into play especially at very low value for KOVR: The beginning of the pulse of the signal y1 (t) is phase locked to x1, and thus necessarily varies the time center of the Pulse with the current amplitude. This gives y1 (t) an ampli- tudenabhängige phase modulation, which is the stronger, the smaller KOVR is, ie the fewer Clk cycles per period of x (t) are generated.

This deficiency can be remedied by a further variant according to the invention in which the pulse width control is equally divided between the beginning and the end of the pulse, i. with increasing ye (t) the phase for the beginning of the pulse becomes always earlier and the phase for its end (as before) ever later, but both oppositely directed temporal shifts occur only with half the phase difference as before, so that Overall, the full phase difference and pulse duration again.

An example of this is shown in FIG. 12 as a structure and in FIG. 13 in the signal profile. In FIG. 12, the LUT (previously 302, now 1202) receives a modification: it has 2 outputs ye_start and ye_stop for the previous output ye. In addition, in this example, the LUT can take over the generation of the signals ye_is_0 (, 1 'at yd (t) <ydO) and ye_is_max (, 1' at ye = yd (t)> yd1), so that the additional Logical block is saved. The signals ye_start and ye_stop can be formed according to the following rule:

I 0 for yd (t) <ydO ye_start (t) = | ye_max / 2-integer (yd (t) / 2) for ydO <= yd (t) <= yd1 (2) I yejnax for yd (t)> yd1

I 0 for yd (t) <ydO ye_stop (t) = | ye_start (t) + yd (t) for ydθ <= yd (t) <= yd1 (3)

I yejnax for yd (t)> yd1

The division by 2 in (2) will produce a rounding error on odd values of yd (t) by the integer function. Therefore, in (3), this integer value ye_start (t) is used so that the difference ye_stop (t) -ye_start (t) in the linear region (ie at ydO <= yd (t) <= yd1) is exactly equal to yd (t ) and does not contain a rounding error, so that the pulse duration is mapped linearly without rounding error. Table 1 shows an example of such a LUT. Table 1

In this case, the column ye gives the effective value of the pulse duration for a choice of ydθ = 5, yd 1 = 11. In FIG. 12, this output ye is not necessary at the LUT, since ye results from the control of the edge-controlled RS flip-flop (503) with the other signals. The resulting signal curves are shown by way of example in FIG. 13. For yd (t) in the range from 5 to 11, a proportional pulse duration is generated at y1 (t), which, unlike FIG. 9, is now centered about the center of the pulse. However, it can be seen that this centering is not exact, but can differ by a maximum of a half time unit, which results from the integer rounding in (2). Thus, a residual error in the generated phase of the pulse of at most half a time unit of the delay remains between two adjacent taps of the DLL. This maximum residual error can, however, by a DLL with very large N, z. B. be kept very small according to FIG. 6b to 6d.

Such a system according to the invention can convert an analog high-frequency signal x (t) with a high-efficiency switched PA into an amplified analog output signal Generate y (t) with good linearity. It is well suited to replace existing analog PA with lower efficiency. Because of the inventive feature of setting limits for the minimum pulse duration and the minimum pulse pause, switched PA can be used up to much higher carrier frequencies than, for example, in a conventional PLM. Compared to a conventional SDM, the solution described here has the main advantages that, firstly, the pulse duration is variable in virtually arbitrarily fine steps, the time unit can be far smaller than a clock period, and secondly, the pulse can be synchronized in phase with the input signal, with the described Centering the pulse center even when changing the pulse duration is almost no change in the phase.

For future further applications, it may also be desirable to provide a digital interface xd (k) instead of the analog input interface x (t). Here k is an integer variable for the constant clock with which the digital signal xd (k) is present. xd (k) can be a summary (a vector) of several individual digital signals, for example comprising the digital signals of amplitude xda (k) and phase xdp (k), or comprising the digital signals of amplitude xda (k) and current frequency xdf (k). In contrast to using x (t), which contains a signal in the range of the carrier frequency, the indication of amplitude and phase or amplitude and instantaneous frequency, despite a relatively slow clock for k, namely based on the frequency range of the baseband, a any high-frequency signal x (t) in the frequency range of the carrier will be described. Such a digital interface thus provides a very suitable description of x (t).

Also for this purpose, the system according to the invention can be advantageously adapted. In a first simple example in Fig. 14, the clock is generated from the phase signal xdp (k) by a frequency synthesizer (1411) while the analog signal xa (t) for the SDPLM is generated by a D / A converter (1412) becomes. Instead of the phase signal xdp (k), a digital frequency signal xdf (k) can also be applied at the input of the frequency synthesizer (1411), which indicates the frequency currently to be synthesized (ie the integral of the phase). Whether phase or frequency is chosen depends on the definition of the digital interface, which in turn can be chosen so that the frequency synthesis requires a simple frequency synthesizer (1411). For this purpose, solutions are known, for example based on another SDM. The fixed time units of the variable k of the values of the digital interface are selectable within wide limits, they must be small enough to describe the (analog here imaginary) ideal analog signal x (t) exactly enough. However, since the digital description no longer contains times in the time domain but can be in the frequency domain, the digital interface can also be set in the time units of the baseband. Thus, the data rate at xd (k) drops significantly compared to the frequency at x (t), since the bandwidth is usually much smaller than the carrier frequency of a signal. Nevertheless, the SDPLM loop should also be clocked in the order of magnitude of the carrier frequency for a digital interface operating in the time units of the baseband (or at least in fractions thereof, if the principle of FIG. 11 applies to the system in FIG. 14 is applied), so that the feedback of the nonlinearities takes place in small time periods and the errors are corrected promptly, so that on average a linear function results.

An advantageous solution for the required frequency synthesis is to tap off the taps of a constant clock (the carrier frequency) clocked DLL with a multiplexer so that each clock is incremented by a number of Z taps and thus delay units, such as the phase of the signal xs (t) to be synthesized has changed with respect to the signal xc (t) with the constant carrier frequency in this clock. If, for example, the carrier frequency is 1 GHz and the frequency to be synthesized is 1.01 GHz, the phase difference in each 1 GHz cycle is 1/100 period, ie 10 ps. If the taps of the DLL are in the raster of 5 ps, then for a frequency of 1.01 GHz to be synthesized, Z = 2 taps must be incremented for each clock. Since the signal at the end of the DLL chain coincides in phase with that at the beginning of the last taps can be moved back to the first taps, so the phase after the addition of the phase step by a modulo-N operation on the N taps of DLL can be mapped. If the frequency to be synthesized requires phase steps which do not form integer multiples of the DLL taps, then this rational number can be achieved by another SDM by time-averaging the available phase steps, where the input signal of this further SDM is either the phase or the frequency of the be synthesizing signal. Such a frequency synthesis with DLL has the advantage that the same taps of the DLL can also be tapped to drive the inputs of the multiplexer or multiplexer, such as in Fig. 10 or 12. Since they are phase-locked to xc (t) and are thus no longer phase-locked to x (t), but in the frequency synthesizer (1411) incremented by Z (t) levels in each step must be added exactly that number to the value at the input of the multiplexer of the DPWM (501), as shown in Fig. 15 is outlined.

The structure in Fig. 14 includes a plurality of A / D and D / A conversions. These can be summarized very advantageously to a structure as shown in Fig. 16. The feedback loop now only contains digital elements. The summation function (1403) is now also executed digitally. Instead of the signal y1 (t) at the output of the DPWM, the signal ye (t) is now fed back, which is also a digital signal. The essential nonlinearity of the system, namely that of the encoder (302), is thus detected and corrected by the feedback. An embodiment of the DPWM according to FIG. 12, where the coder (1202) no longer forms an explicit signal ye (t), can nevertheless also be used here by simply expanding the coder (302) or the LUT (1202) and is provided with an additional output signal ye (t) which outputs the effective values for ye (t), as already exemplified in the last column in Table 1. This system in Fig. 16 is a very cost-effective yet high-quality implementation of the concern of the invention in the form of an SDPLM which combines the advantages of SDM and PLM in a largely digitally implemented system and overcomes their respective disadvantages.

If, in addition, the nonlinearities of the PA (107) and the reconstruction filter (108) are to be linearized in the feedback, they can advantageously be converted into a monolithic circuit (analogous to FIG. 2d) by a simulation of the PA (207) and the reconstruction filter (208). 1701) are integrated with the SDPLM and clock generation (1411) as shown in FIG. Again, a D / A converter (106) is required in the feedback loop since the replicas, as well as PA (107) and reconstruction filters (108), themselves produce analog signals.

Again, this structure can advantageously be converted so that the SDPLM contains only digital elements and thus allows high accuracy and resolution at low cost and high clock rate. An example of this is shown in FIG. As in FIG. 16, the integer signal ye (t) is used, and unlike in FIG. 17, the replicas of the PA (1707) and the reconstruction filter (1708) are digital elements. The replicas of the PA (1707) and the reconstruction filter (1708) can also be combined into a single digital element that generates a sequence of digital output values yd * (t) for a sequence of input values ye (t) that reflect the real behavior of the PA (107) and the reconstruction filter (108) with sufficient accuracy and scaled for the SDPLM. In one simple case, one already suffices here simple LUT, which indicates the integral of the value resulting at yd over a clock period in suitably scaled form as output value yd * for each possible value ye and thus pulse duration value y1 which is present at the input of the PA. Since the PA is switched, the individual clock periods are relatively independent of each other, so that even such a LUT as a common replica of the PA (107) and the reconstruction filter (108) can provide very good results. Further effects of the temporal dependence of yd (t) on previous history in previous clock periods resulting, for example, from the heating of the PA can also be digitally modeled, eg by means of FIR filters, and thus included together with LUT in the common replica.

Thus, a structure according to the invention, as illustrated by way of example in FIG. 18, offers a monolithic circuit (1701) which is improved but still cost-effective to implement, with a digital interface at the input providing a high-quality largely error-free analog signal yd (t) at the output of the system.

Claims

claims

A sigma-delta pulse length modulator comprising

a signal input having a differential stage whose first input is supplied with an analog input signal and which is designed to generate and output a difference signal corresponding to the difference of the signals present at its inputs,

a forward loop filter for converting the difference signal into an analog filter output signal having a signal value,

an analog-to-digital converter connected downstream of the forward loop filter and configured to convert the analog filter output signal to a digital converter output signal containing two or more parallel bit component signals that together represent a digital value corresponding to the signal value assumed by the analog filter output signal .

a digital pulse length modulator to which the Wandlerausgang- ssignal is supplied on the input side and which is adapted to convert the applied transducer output signal into a digital modulator output signal, which consists of a single bit component signal and having a signal duration representing the digital value, which is the one assumed by the analog filter output signal Signal value corresponds, and

a feedback loop which returns an analogue feedback signal dependent on the modulator output signal to a second input of the differential stage.

The sigma-delta pulse length modulator of claim 1, wherein the feedback loop recirculates the modulator output via a digital-to-analog converter to the second input of the differential stage.

3. sigma-delta pulse length modulator according to one of the preceding claims, wherein the analog-to-digital converter is adapted to perform the implementation of the filter output signal with a predeterminable by an applied first clock signal first clock frequency.

4. sigma-delta pulse length modulator according to any one of the preceding claims, in which

the pulse length modulator is supplied with a first clock signal having a first clock frequency via a first clock input, and a second clock signal having a second clock signal, which is higher than the first clock frequency, via a second clock input;

the pulse length modulator includes a counter connected to the first and second clock inputs and configured to set the counter reading of the counter from a predetermined output value to the digital value corresponding to the signal value assumed by the analog filter output signal at each clock event at the first clock input, the digital value to hold for a digital value corresponding number of clock periods of the second clock frequency and then reset to an initial value.

The sigma-delta pulse length modulator of claim 1 or 2, wherein the pulse length modulator is configured to generate and output the modulator output signal with a signal duration that is in a non-linear relationship to the digital value of the filter output signal.

6. sigma-delta pulse length modulator according to any one of the preceding claims, with an analog-to-digital converter downstream encoder, which is designed to convert the converter output signal into a coded by a non-linear mapping rule coded transducer output signal.

The sigma-delta pulse length modulator of claim 6, wherein the encoder is an integral part of the pulse length modulator.

8. A sigma-delta pulse length modulator according to claim 6 or 7, wherein the pulse length modulator is configured to generate and output a modulator output signal from the coded converter output signal having a respective signal duration that is in a non-linear relationship to the digital value of the filter output signal and is above a predetermined, dependent on the switched amplifier minimum signal duration, and with a temporal signal spacing between successive opposite signal edges of two temporally directly adjacent modulator output signals, which is above a predetermined, dependent on the switched amplifier temporal minimum signal spacing.

A sigma-delta pulse length modulator as claimed in any one of claims 6 to 8, wherein the encoder includes a look-up table which assigns a coded transducer output signal to the possible values of the transducer output signal.

A sigma-delta pulse length modulator according to any one of claims 6 to 9, wherein the bit width of the coded transducer output signal comprises a larger bit width (M2) than the bit width (M 1) of the transducer output signal.

The sigma-delta pulse length modulator of any one of claims 6 to 10, wherein the encoder is configured to change the mapping rule to produce the coded transducer output signal during operation.

12. sigma-delta pulse length modulator according to claim 1, wherein the pulse width modulator comprises a digitally adjustable delay element (501), which generates from an applied first signal, a second signal with an adjustable delay relative to the first signal, and a digital circuit comprising the first and the second signal linked so that at its output a third signal is applied, the pulse duration of which depends on the delay between the first and second signal.

13. sigma-delta pulse length modulator according to claim 12, wherein the digital circuit includes an RS flip-flop, which is set by the first signal and reset by the second signal, and at whose output the third signal can be tapped.

The sigma-delta pulse length modulator of claim 12, wherein the digitally-adjustable delay element includes a number of parallel delay elements having different fixed delays to which the first signal is applied and a multiplexer connected downstream of the delay elements and formed at its output in response output each of the delayed first signals as the second signal from the value of the coded converter output signal.

15. The sigma-delta pulse length modulator of claim 12, wherein the digitally adjustable delay element comprises:

a delay-locked loop, which is designed to impose in parallel the number of different fixed delays on the input side of the first signal and to provide the differently delayed first signals at a corresponding number of parallel signal outputs, and a delay element connected downstream of the multiplexer, which is designed to output at its output depending on the value of the coded converter output signal in each case one of the delayed first signals as the second signal.

The sigma-delta pulse length modulator of any one of claims 6 to 10, wherein the encoder is configured to vary both the timing of the rising edge and the falling edge of the modulator output signal in response to the input signal of the encoder.

17. The sigma-delta pulse length modulator of claim 16, wherein the encoder is configured to vary the pulse duration of the modulator output signal in response to the input signal of the encoder and at the same time modulate the phase of the modulator output signal relative to that for the feedback loop of the sigma delta signal. Pulse length modulator effective clock, eg to the clock of the analog-to-digital converter, to keep constant on a remaining residual error of the phase.

18. sigma-delta pulse length modulator according to claim 1, wherein the first input of the differential stage, an input digital-to-analog converter is connected upstream, which is designed to convert a voltage applied to its input digital input signal into the analog input signal.

The sigma-delta pulse length modulator of claim 18, wherein the digital input amplitude signal of the differential stage and the other of a digital input signal vector determining the digital input signal having a digital input amplitude signal and either a digital input phase signal or a digital input frequency signal the two digital signals of the input signal vector is supplied to a clock generator, which is designed to derive from this other of the two digital signals of the input signal vector a clock signal which is supplied to the pulse length modulator.

The sigma-delta pulse length modulator of claim 18, wherein the digital input amplitude signal of the differential stage and the digital input frequency signal are applied to a clock generator from a digital input signal vector determining the digital input signal having a digital input amplitude signal and a digital input frequency signal which is adapted to derive from the input frequency signal a clock signal which is supplied to the analog-to-digital converter and the pulse length modulator.

21 sigma-delta pulse length modulator according to any one of the preceding claims, wherein the frequency of the effective for the feedback loop of the sigma-delta pulse length modulator clock signal, z. B. the clock of the analog-to-digital converter, is time-varying and from the instantaneous characteristics of the input signal of the sigma-delta pulse length modulator, z. B. from the time interval between two adjacent same-direction zero crossings, is formed by a time-varying clock generator.

The sigma-delta pulse length modulator of claim 21, wherein the frequency of the clock signal is formed by a frequency multiplier.

23. sigma-delta pulse length modulator comprising

a signal input having a digital differential stage, the first input of which is supplied with a digital input signal and which is designed to generate and output a digital difference signal corresponding to the difference of the digital signals present at its inputs,

a forward feedforward digital filter for converting the input signal into a digital filter output signal containing two or more parallel bit component signals which in their entirety represent a digital value corresponding to the signal value assumed by the digital filter output signal,

a digital pulse length modulator, to which the digital filter output signal is fed on the input side and which is designed to convert the applied filter output signal into a digital modulator output signal, which consists of a single bit component signal and has a signal duration that depends on the signal value of the digital filter output signal, and

a feedback loop which returns a digital feedback signal dependent on the digital filter output signal to a second input of the differential stage;

in which the digital input amplitude signal of the differential stage and the other of the two digital signals of the input signal vector are fed to a clock generator from a digital input signal vector determining the digital input signal having a digital input amplitude signal and either a digital input phase signal or a digital input frequency signal is who is trained out deriving from this other one of the two digital signals of the input signal vector a clock signal which is fed to the pulse length modulator.

24 sigma-delta pulse length modulator according to claim 23, wherein the digital forward loop filter is a D-type flip-flop, whose D input, the digital difference signal is supplied, and the enable input, the clock signal of the clock generator is supplied.

The sigma-delta pulse length modulator of claim 23 or 24, wherein the pulse length modulator is configured to generate and output the modulator output signal with a signal duration that is in a non-linear relationship to the digital value of the filter output signal.

The sigma-delta pulse length modulator of any one of claims 23 to 25, further comprising an encoder coupled downstream of the forward loop filter and configured to convert the filter output signal to a transducer output signal encoder output signal writable by a non-linear mapping law.

The sigma-delta pulse length modulator of claim 26, wherein the encoder is an integral part of the pulse length modulator.

28 sigma-delta pulse length modulator according to claim 26 or 27, wherein the Kodier rerausgangssignal is fed back to the second input of the digital differential stage.

29. A sigma-delta pulse length modulator according to claim 26 or 27, wherein the encoder output signal is responsive to the input of a digital replica of a sigma delta signal.

Pulse length modulator downstream switching amplifier and / or reconstruction filter is guided and is fed back from the output of this digital replica to the second input of the digital differential stage.

30. amplifier circuit comprising

a signal input, which is followed by a sigma-delta pulse length modulator according to one of the preceding claims,

a digitally switched amplifier, which is driven by the output signal of the sigma-delta pulse length modulator and which is designed to amplify the output signal of the sigma-delta pulse length modulator and output as an amplifier output signal, and a reconstruction filter, to which the amplifier output signal is supplied and which is designed to filter the amplifier output signal in such a way that, at the output of the reconstruction filter, an analogue output signal is present which is amplified in relation to the input signal present at the signal input.

31. The amplifier circuit of claim 30, wherein the feedback loop recirculates a feedback signal derived from the amplifier output via a digital-to-analog converter to the second input of the differential stage.

The amplifier circuit of claim 30, wherein the feedback loop directly feeds back a feedback signal derived from the analog output signal of the reconstruction filter to the second input of the difference stage.

33. Amplifier circuit according to claim 31 or 32, wherein the feedback signal is derived by means of a capacitive or inductive coupling of a terminal in the digitally switched amplifier or reconstruction filter.

34. An amplifier circuit according to claim 30, 31 or 32, wherein

the switched amplifier and the reconstruction filter are not monolithically integrated with the sigma-delta pulse length modulator, but instead form separate circuit components, and in which

the feedback loop is monolithically integrated with the sigma-delta pulse length modulator and includes a first replica circuit of the switched amplifier configured to down-scale the behavior of the switched amplifier during operation of the amplifier circuit and a second replica circuit configured to operate during operation of the switched amplifier Amplifier circuit to reproduce the behavior of the reconstruction filter downscaled.

35. The amplifier circuit of claim 34, wherein the first and second replica circuits are combined in a common replica circuit.

36. An amplifier circuit according to claim 34 or 35, wherein the first and second replica circuits and the common replica circuit are digital circuits.

37. The amplifier circuit of claim 30, wherein the sigma-delta pulse length modulator is configured to provide the modulator output signal with a signal duration offset. staging between adjacent signal values, wherein one stage of the signal duration graduation is less than a minimum delay time of an active amplifier stage.