DE102004006995B4 - Digital phase-locked loop for sub-μ technologies - Google Patents

Abstract

Digital phase-locked loop, with
A digitally controlled oscillator (4) for generating an output frequency,
- a phase detector means (11, 12, 13) for detecting the phase difference between a reference frequency and one of the output frequency of the oscillator (4) dependent frequency, and for converting the phase difference into a digital control signal, wherein the phase detector means (11, 12, 13) comprises a delta-sigma frequency decider (11),
- A digital loop filter (14), via which the digital control signal or a digital signal derived from the digital control signal is supplied to the digitally controlled oscillator (4) for adjusting the output frequency, and
- One of the delta-sigma frequency decision (11) downstream digital frequency control device (12) for generating a frequency value-containing digital signal for driving the loop filter (14).

Description

The The invention relates to a digital phase-locked loop for generating an output frequency using a digitally controlled oscillator.

digital Phase locked loops, so-called PLL (Phase-Locked Loop) come used in a variety of integrated circuits. PLL serve as clock and frequency synthesizers, generators and multipliers, they come in time, data and Clock recovery circuits are used and are also in receiving and transmitting circuits used by phase or frequency modulated systems.

Previous Applications mostly use analog PLL, which is a phase / frequency detector (PFD: Phase / Frequency Detector) include the output frequency of a Voltage Controlled Oscillator (VCO: Voltage Controlled Oscillator) with a reference frequency and as an output signal generates a voltage representing the information of the phase and frequency difference between the output frequency of the voltage controlled oscillator and the reference frequency. The voltage signal is fed to a charge pump (CP: Charge Pump), which converts the voltage signal into a corresponding current signal. This Current signal is fed to a loop filter (LF: Loop Filter) whose Output signal drives the voltage controlled oscillator. in the Feedback path between the voltage-controlled oscillator and the phase / frequency detector can a frequency divider may be arranged with a divider factor N. in the Regulated state of the PLL corresponds to the output frequency of the PLL Voltage controlled oscillator of N times the reference frequency.

In recently, Time will be the design and implementation of fully integrated PLL aspired. Here are the use of modern CMOS technologies Conditions (for example, reduced voltage and power supply, gate leakage, reduced gm * r Product (reinforcement)) before that for analog circuits are less favorable than for digital circuits. Future CMOS Technologies will provide faster nMOS and pMOS transistors, the for digital circuits are excellently suited. Furthermore More than eight metal layers will be feasible, the spiral inductor structures enable, and there is a possibility To realize MOS varactor fields. This will be the realization from digitally controlled VCO, so-called DCO (Digital Controlled Oscillator) compared to analog oscillators favored.

From the nearest prior art illustrative patent DE 100 22 486 C1 a digital phase-locked loop is known which can be realized in integrated form. The phase detector device of this circuit comprises a substantially analog phase / frequency detector.

In Scripture US 6,580,376 B2 a phase-locked loop is described in which a digital phase error signal is integrated by a digital integration block and then converted into an analog signal. The integrated analog signal is fed to a voltage controlled oscillator as a control signal. The integration length of the integration block can be varied by increasing or decreasing the bit resolution of circuits within the integration block.

The font US 6,429,693 B1 discloses another digital PLL that is compatible with modern sub-μ CMOS technologies. The digital phase / frequency detector comprises a time-to-digital converter whose resolution is given by the switching delay of an inverter realized in the CMOS process.

at such digital phase / frequency detectors becomes a digital word, that represents the reference frequency, from a digital word representing the (possibly divided) output frequency of the digitally controlled oscillator, subtracted to the Phase / frequency error value which is the output signal an analog phase / frequency detector equivalent. The main one Disadvantage of this procedure is the appearance of not controllable interference frequencies (spurious frequencies), which due to the finite word length of arise from each other to subtracting digital words.

In the publication "Delta Sigma Modulation in Fractional-N Frequency Synthesis ", T.A. Riley, M.A. Copeland and T.A. Kwasniewski, Journal of Solid State Circuits (JSSC), Vol. 28, No. 5, pages 553 to 559, May 1993, is the use of a delta sigma Modulators for the signal driving a frequency divider described. The frequency divider is implemented as a two-modulus divider. By the delta-sigma modulation becomes the influence of interfering frequencies in comparison to known fractional-N dividers in phase-locked loops reduced.

In the publication "An Oversampling Delta-Sigma Frequency Discriminator", RD Beards, MA Copeland, IEEE Transactions on Circuits and Systems-II .: Analog and Digital Signal Processing, Vol. 41, No. 1, pp. 26 to 32, January 1994, a Frequenzentscheider circuit is given, which consists of a two-modulus frequency divider and a frequency comparator downstream of the phase comparator consists. The implementation advantage of this circuit is that two-modulus frequency dividers are relatively simple digital circuits that can operate at high frequency (several gigahertz) at low power consumption. The Frequenzentscheider is used in the front end of an intermediate frequency heterodyne receiver.

US 5,266,907 discloses a phase locked loop in which a delta-sigma frequency detector is provided.

US 5,781,044 discloses a delta-sigma frequency synthesizer in which a delta-sigma frequency discriminator and a loop filter are provided.

Of the Invention is based on the object, a digital phase locked loop which has a high degree of digitization and (nevertheless) excellent PLL properties under different conditions (manufacturing and / or operating conditions). In particular, should as possible no interference frequencies occur and PLL characteristics such as jitter (phase noise), Jitter tolerance, steady state bandwidth, frequency resolution, phase / frequency modulation etc. over suitable design parameters simple and the respective field of application can be controlled or adjusted accordingly.

The The invention is based task by the Characteristics of claim 1 solved. Advantageous embodiments and further developments of the invention are specified in the dependent claims.

According to claim 1 shows the inventive digital Control circuit a digitally controlled oscillator for generating a Output frequency on. Furthermore, the digital control circuit comprises a Phase detector means for detecting the phase difference between a reference frequency and one of the output frequency of the oscillator dependent Frequency, and for converting the phase difference into a digital one Control signal. By means of a digital loop filter is the digital control signal or digital derived from the digital control signal Signal the digitally controlled oscillator to adjust the output frequency fed. According to the invention the digital phase locked loop characterized in that the phase detector means comprises a delta-sigma frequency decider.

By the use of a delta-sigma frequency discriminator in the phase detector device this one has a simple and for integration into sub-μ CMOS processes suitable structure. Another significant advantage exists in that the noise generated by the frequency quantization in higher Frequency range - above the transmission bandwidth limit the settled PLL - shifted becomes. This will be the suppression of interfering frequencies decisively improved. Another advantage of the PLL according to the invention is that due to the delta-sigma frequency decision to a charge pump circuit in the signal path behind the Frequenzentscheider can be waived. As a result, it can be achieved that the entire digital phase locked loop has no integrated or discrete capacitors to summarizes. In addition, the inventive digital Phase locked loop excellent properties in terms of jitter and transient behavior.

According to one advantageous embodiment is the delta-sigma frequency decision a digital frequency control device for generating a frequency values containing digital signal for driving the loop filter downstream. This frequency control device can by a be implemented simple two-way multiplexer.

To a particularly preferred embodiment of the invention is digital loop filters of third or higher order. Through a loop filter third order is a damping of -60 dB / decade achieved, whereby the frequency quantization noise sufficient is filtered away.

The Digital loop filters are preferably from the Butterworth, Bessel, Chebyshev or Cauer type, with the latter two filter types particularly preferred due to its steep cutoff characteristic are.

A further advantageous embodiment of the invention is characterized thereby, a wave digital filter as a digital loop filter too choose. Wave digital filters come with a shorter word length Filter coefficients and the internal state variables. Further need Wave digital filter lower power consumption than conventional digital filters. One further advantage in the use of wave digital filters in that after an overflow, as caused for example by a noise pulse can show an excellent recovery behavior. by virtue of the inherent passivity of a wave digital filter, the filter response to an input noise pulse should completely disappear. Wave digital filters are the publication "Explicit Formulas for Lattice Wave Digital Filters ", Gazasi, IEEE Transactions on Circuits and Systems, Volume 32, No. 1, pages 68 to 88, January 1985, refer to.

A further advantageous embodiment of The invention is characterized in that an integrator is arranged between the digital frequency control device and the loop filter. The task of the digital integrator is to convert frequency information into phase information. Although the digital integrator may be provided at a different position in the signal path, eg behind the loop filter or between a sampling rate conversion circuit and a noise shaper, its optimal position lies between the digital frequency control device and the Loop filter, as in this position an optimal dynamic modulation range and low power consumption are given.

A further advantageous embodiment of the invention is characterized in that in the signal path behind the loop filter is a quantizer which is a re-quantization of input values to output values with reduced word width performs. By the quantizer on the one hand, the one usually larger word width in the digital loop filter to the smaller word width of the input be adapted to the digitally controlled oscillator. On the other hand can - according to one Particularly preferred embodiment of the quantizer - by an increase the sampling rate in the quantizer by the quantization error caused phase noise (jitter) shifted to higher frequencies become. This is particularly advantageous when the quantizer additionally includes a noise shaper, as this while the phase noise at low frequencies, but amplified at high frequencies.

The Invention will be described below with reference to an embodiment and variants the same explained with reference to the drawings; in these shows:

1 the architecture of a digital PLL according to the invention using a digitally controlled oscillator;

2 the structure of in 1 shown digital processor;

3 a schematic diagram of the in 2 illustrated oversampling delta-sigma frequency discriminator;

4 a schematic diagram of in 2 shown frequency control unit;

5 a schematic diagram of in 2 the quantization and rate conversion unit shown;

6 a first variant of in 2 the quantization and rate conversion unit shown;

7 a second variant of in 2 the quantization and rate conversion unit shown;

8th two graphs in which the phase noise or the accumulated phase noise (absolute jitter) over the frequency are shown;

9 a graph in which a simulated output signal of the digitally controlled oscillator over time is shown; and

10 a diagram in which the 9 corresponding digital input signal of the digitally controlled oscillator is shown over time.

1 shows the general structure of a digital PLL according to the invention. The digital PLL includes a digital processor 1 , which has a digital control bus 2 with the entrance 3 a digitally controlled oscillator (DCO) 4 communicates. At the exit 5 of the digitally controlled oscillator, an analog frequency signal is output. This is via an electrical connection 6 a first entrance 7 of the digital processor 1 fed. At a second entrance 8th of the digital processor 1 is a reference frequency or a reference clock Fref on.

In the 1 The circuit shown can be implemented in a single integrated circuit in a fully integrated form.

2 shows a block diagram of the digital processor 1 , This includes a delta-sigma frequency decider 11 , a digital frequency control unit 12 , a digital integrator 13 , a digital loop filter 14 and a digital quantization and rate conversion unit 15 ,

The reference frequency Fref and the output signal of the digitally controlled oscillator 4 become the delta-sigma frequency decider 11 fed. The digital frequency control unit 12 receives via an entrance 16 Frequency synthesis parameters. Filter parameters and possibly also state values can be used by the digital loop filter 14 over an entrance 17 be forwarded. The structure of the individual blocks as well as the functioning of in 2 The circuit shown below are based on the 3 to 7 explained in more detail.

3 shows the circuit structure of the delta-sigma frequency discriminator 11 , The analog output signal of the digitally controlled oscillator 4 becomes the input of a two-modulus divider circuit 20 with suitably chosen divisor factors N and N - L forwarded. The frequency-divided output signal Fdif of the two-modulus frequency divider circuit 20 is on the one hand with the clock input of a phase comparator 21 on the other hand gives the clock of a delay element 22 via which an output signal F_digital of the phase comparator 21 to the entrance 23 the two-modulus divider circuit 20 is created to select the divisor factor. The frequency comparator 21 is for example designed as a simple D flip-flop, wherein the reference frequency Fref the D input 8th of the flip-flop 21 is forwarded.

The delta-sigma frequency decider 11 (first order) serves the frequency / phase information of the digitally controlled oscillator 4 into the digital domain. In the delta-sigma frequency decider 11 becomes a coarse quantization of the frequency deviation between the reference frequency Fref and the output frequency of the digitally controlled oscillator 4 realized with a 1-bit accuracy. In addition, the (binary) output bit stream F_digital noise is converted, ie the noise caused by the frequency quantization is shifted to a higher frequency range.

The functioning of the in 3 illustrated delta-sigma frequency decision 11 is known in the art and described in detail, for example, in the aforementioned article "An Oversampling Delta-Sigma Frequency Discriminator" by RD Beards and A. Copeland. This article shows that the in 3 illustrated circuit has the same properties as a classical first-order delta-sigma modulator, that is suppressed the quantization noise in the output by means of high-pass filtering. The output signal (bit stream) F_digital of the flip-flop 21 can be considered as the sign of the phase difference between the reference frequency Fref and the output frequency signal of the digitally controlled oscillator 4 be considered, ie the flip-flop 21 acts as a phase quantizer (phase decision) which produces a 1-bit approximation of this phase difference. It is further noted that the clock frequency Fdiv, with which the flip-flop 21 and the delay element 22 and which is the sampling rate of the digital (binary) output bitstream F_digital of the flip-flop 21 represents, in the steady state, the PLL approximately corresponds to the reference frequency Fref. It should also be noted that the phase comparator 21 may be more complex in reality and in addition to the D flip-flop has a phase / frequency detector to convert the control loop in the transient state in the transient response.

The bitstream F_digital becomes the frequency control unit 12 fed. This is in 4 shown in more detail. Their job is to set the output frequency of the digitally controlled oscillator 4 set. The frequency control unit 12 consists essentially of a two-way multiplexer MUX 30 to which two different frequency control parameters vx and vy are supplied at its multiplexer inputs. The multiplexer input 0 (ie the frequency control parameter vy) is selected when the control signal F_digital has the logic state 0. Otherwise, that is, when the logic state of the control signal F_digital is 1, the multiplexer input 1 (ie, the frequency control parameter vx) is selected. The respectively selected frequency control parameter vx or vy is a digital word (with, for example, a word length 20 ) and forms the output signal F_synt of the frequency control unit 12 ,

A synopsis of 3 and 4 indicates that the output bit stream F_digital of the delta-sigma frequency discriminator 11 both the two-modulus frequency divider circuit 20 as well as the multiplexer 30 controls: If F_digital is 0, the divider factor is the two-modulus divider circuit 20 at the next sampling time, the value N and the output value of the multiplexer 30 is the constant value vy. If F_digital has the value 1, the two-modulus divider circuit is used 20 in the following sampling time use the divider value NL and the value of F_synt is vx.

The Values of vy and vx are constant. They can be precalculated and in be stored in a ROM, RAM or a flash memory device.

The usable frequency range of the digitally controllable oscillator 4 depends on the maximum and minimum values allowed via the digital control bus 2 from the processor 1 to the oscillator 4 can be transmitted. It is well known that by averaging in the time domain, the frequency resolution of the output signal of the digitally controllable oscillator 4 can be set very finely and practically alone by the bit accuracy of the digital processor 1 is dependent. If the PLL is operated as a frequency synthesizer, the synthesized output frequency of the oscillator results 4 to Fgoal = n · Fref, (1) where n is an arbitrary real number and Fgoal the desired output frequency of the oscillator 4 is.

On this way a continuous frequency tuning is possible. For this values of n so chosen be that Fgoal the allowed tuning range of the frequency synthesizer.

For known values of Fgoal and Fref, the frequency control parameters vx and vy may be the frequency control circuit 12 calculated as follows:
The integer divisor factor N results from the equation N = [Fgoal / Fref], (2) where [·] denotes the integer part of the parenthesis expression + 1. L denotes an integer design parameter which is chosen to select a suitable value for a divisor factor Nfrac. Nfrac follows according to Nfrac = (N - Fgoal / Fref) / L. (3)

According to the relationship following from the equations (1) to (3) n = N - Nfrac × L (4) Nfrac is the fractional divider factor scaled by L.

The frequency control parameters vy and vx are now defined according to the following equations vy = Nfrac and vx = Nfrac - 1 (5)

Out The equations (1) to (5) show that for a given ratio of Fgoal / Fref (i.e. a given divisor factor n) when using different ones Values L are different scaled fractional divisor factors Nfrac and thus also different frequency control parameters vx and vy be obtained.

The frequency control unit 12 In addition, it can be used to impose frequency modulation on the output of the digitally controlled oscillator 4 be used. To illustrate this possibility, the scaled fractional divider factor Nfrac is written in the following form: Nfrac = Nfrac0 + mod_Nfrac, (6) where Nfrac0 is the (scaled) fractional divider value without modulation and mod_Nfrac is the (scaled) digital input value for frequency modulation. Assuming that the modulated output frequency of the digitally controlled oscillator 4 through the expression Fgoal = Fgoal0 + mod_freq (7) where Fgoal0 is the output frequency of the oscillator 4 without modulation and mod_freq the modulation component of the output frequency of the oscillator 4 , equation (4) yields the following relationship: mod_freq = -mod_Nfrac · L · Fref. (8th)

Since L and Fref are constant during the modulation, digital modulation of the output frequency of the digitally controlled oscillator can be achieved by suitable digital signal processing for the now variable frequency control parameters vx and vy 4 be achieved.

According to 2 becomes the digital output signal F_synt of the frequency control unit 12 the digital integrator 13 fed. This converts the digital frequency information by integration in a phase information. The at the output of the integrator 13 The provided phase information represents a phase error signal with a linear behavior with respect to the tracking characteristic of the PLL. The digital integrator 13 can also be found elsewhere in the signal path, eg behind the loop filter 14 or between the rate conversion unit to be explained later and the noise shaper (noise shaping stage).

Due to the linearity of the phase error signal at the output of the integrator 13 can the digital loop filter 14 be realized in a conventional manner. The use of a digital loop filter 14 allows completely new possibilities compared to analog filter arrangements: First, the digital PLL does not require a charge pump and therefore no (integrated or discrete) capacitors. Second, a closed loop transfer function can be realized with higher (third or fourth) order without the use of inductors or active loop filter topologies. Third, the shape of the closed loop transfer function can be determined according to the Butterworth, Bessel, Chebyshev, and Cauer filter specifications. Consequently, with digital filters, highly selective truncation characteristics of the transfer function can be achieved, which are not achievable with an analog PLL using a charge pump. This is due to the presence of parasitic poles and zeroes in an analog PLL that exert second-order effects on the closed PLL transfer function and thereby unacceptably affect the stability of an analog PLL.

For the present invention, the use of a higher order (3rd or 4th order) sharp cut-off frequency function of the closed-loop (digital) PLL is very advantageous because, as already mentioned, the main drawback of digital processors is the prevalence is that of interference frequencies due to the finite word width. It is important to be able to control these disturbing frequencies or disturbing sounds for all process and temperature variations which occur during the production or operation of the PLL. Distortion tones destroy the spectrum of the output frequency of the PLL and increase the noise level of the PLL. In other words, distortion sounds reduce the phase noise quality (jitter quality) of the PLL.

As already explained, there is a significant advantage of the delta-sigma frequency discriminator 11 This is to shift disturbing sounds into the stop band of the digital PLL's transfer function, thereby providing the ability to effectively attenuate them using the loop filter. However, the noise shaping function of the delta-sigma frequency discriminator has 11 has a noise enhancement of +20 dB / decade, so that a common second-order loop filter attenuates the interference tones caused by the frequency quantization only at -20 dB / decade instead of its actual attenuation at -40 dB / decade in the stopband. In order to achieve an attenuation of -40 dB / decade in the stopband, therefore, at least one loop filter with an attenuation of -60 dB / decade (ie at least one filter 3rd order) is required, with a particularly sharp cutting performance by Chebyshev and Cauer filters of said filter order is achieved.

It is known that noise analysis is of central importance for analogue PLLs. Nothing else applies to a PLL based on digital signal processing. However, there are differences between the digital and analog approaches: When using a digital loop filter, a so-called "bit-true" analysis must be performed on two aspects, namely truncation (truncation) of bits on the least significant bit (LSB) side ) and the correction of an overflow at the most significant bit (MSB: Most Significant Bit) position. In addition, by scaling the internal digital signals within the loop, the dynamic range of each digital circuit element must be optimally utilized and matched. These mechanisms require a relatively high level of expertise in the field of digital technology. To reduce the word width requirements of the filter coefficients and the internal state variables, it is therefore advantageous to use as a loop filter 14 to use a wave digital filter. As a result, both the power consumption of the filter and its recovery properties in a sudden overflow in the input signal is favorably influenced.

5 shows a first variant 15.1 the in 2 represented quantization and rate conversion unit 15 , The quantization and rate conversion unit 15.1 includes a quantizer 40 which is a rate conversion stage 41 fed. The output of the rate conversion stage 41 is with the digital control bus 2 connected.

The digital filter is clocked at the frequency Fdiv, which is generally different from the frequency Fgoal of the output signal of the digitally controlled oscillator 4 is. As a result, there is between the output of the digital loop filter 14 and the entrance 3 of the digitally controlled oscillator 4 a sample rate conversion required. In addition, the word width of the in the digital loop filter 14 processed digital signal is typically larger (20 bits or more) than the allowable input word width of the digitally controlled oscillator 4 which is usually less than 14 bits. As a result, the frequency / phase information (depending on whether, the integrator 13 at the in 2 or within the quantization and phase conversion unit 15 is intended to be quanitized again (the first quantization to individual bits has already been performed in the delta-sigma frequency discriminator 11 performed). The quantizer 40 is referred to below as the DCO quantizer.

Provided that by the DCO quantizer 40 caused quantization error is negligible (this applies, for example, for n ≈ 1), the output frequency signal of the digital loop filter 14 be quantized directly (the sampling rate is the frequency Fdiv and corresponds in the steady state approximately the reference frequency Fref). The rate conversion can be done by a simple repeater (repeater) 41 be performed.

In 6 is a variant 15.2 the quantization and rate conversion unit 15 for the case n >> 1 shown. In this case, Fgoal is considerably larger than Fref, which is the norm in transmit / receive circuits of phase or frequency modulated systems. Unless the influence of the DCO quantizer 40 can not be neglected, he can through the in 6 shown arrangement significantly reduced or avoided. Because the quantization error and its spectral power density are inversely proportional to the clock frequency of the DCO quantizer 40 may be the quantization error of the DCO quantizer 40 by a shift of the clock frequency of the DCO-Qantisierers 40 reduced to higher frequencies. For this purpose, the in 6 illustrated quantization and rate conversion unit 15.2 a divider circuit 42 , by means of which a suitable clock for the DCO quantizer 40 is produced. The divider circuit 42 performs a division of the input side of the digitally controlled oscillator 4 obtained output signal by the intezahli divider factor M through, and carries the frequency-divided signal to the clock input of the DCO-Qantisierers 40 to. The value M is to be chosen so that a sufficient reduction of the quantization error is obtained. In this case, there are two sample rate conversion stages 43 . 44 with different conversion factors A and B needed. The sample rate conversion stage 43 with the conversion factor A is the DCO quantizer 40 preceded while the sample rate conversion stage 44 with the conversion factor B the DCO quantizer 40 is downstream. The sample rate conversion stage 43 interpolates the sampling rate at the output of the loop filter Fdiv into a sampling rate equal to the output frequency of the digitally controlled oscillator 4 divided by M equals. The second sample rate conversion stage 44 performs an interpolation of the sampling rate by the factor M. Both sample rate conversions can be realized using a simple repeater.

By choosing a suitable divisor factor M, a trade off between power consumption and elimination of the quantization error of the DCO quantizer can be achieved 40 be made. The higher the clock frequency of the DCO quantizer, the higher the power consumption and the lower the quantization error of the 6 illustrated circuit.

7 shows a third variant 15.3 the quantization and rate conversion unit 15 , which differ from the second variant 15.2 merely differentiates that the DCO quantizer 45 additionally contains a noise-shaper. This solution is advantageous if, despite the (compared to Fdiv) increased clock rate of the DCO quantizer 40 there still remains too much quantization error (ie a small value for M is chosen) or if the small value M causes implementation problems. The DCO quantizer with noise shaper 45 has two functions. First, he performs the required quantization. On the other hand, it reduces the influence of the quantization error by shifting the phase noise (jitter) towards higher frequencies. The noise shaper therefore reduces the influence of the quantization error (phase noise) at low frequencies, but at the same time amplifies the phase noise at higher frequencies. In the case of a first order noise shaper, the gain is +20 dB / decade at higher frequencies. This makes it possible to select the divisor factor M and the order of the noise shaper and to match them so that the quantization error (taking into account the amplification by the respective noise shaper) is shifted to an optimum frequency range.

The above explanations show that a variety of design parameters (L, type and order of the digital loop filter 14 , Position of the integrator 13 , M, Noise Shaper order in the DCO quantizer 45 , Defining the word width of the individual digital circuit elements, etc.) are available in order to design the PLL for the particular application, which shows an optimal behavior with regard to manufacturing or operating process or temperature variations, the requirements of future CMOS technologies can be maintained or exploited far below μ-structure widths.

The following is a specific, non-limiting example of the present invention:
The basic parameters of the digital processor are, for example:
Fref = 300 MHz; Fgoal = 4.8648 GHz;

A choice of L = 2 results
n = 4864.8 / 300 = 16,216, hence, N = 17, N - L = 15.

It follows Nfrac = (N - n) / L = (17-16,216) / 2 = 0.392.

These values result in the following values for the frequency control parameters vy and vx vy = Nfrac = 0.392 vx = Nfrac - 1 = -0.608.

When using an internal word width of 20 bits for the frequency control unit 12 the frequency control parameters vx, vy are represented by the following values vy_int = round (vy · 524288) = 205521 vx_int = round (vx · 524288) = -318767, wherein vy_int and vx_int represent the frequency control parameters vy and vy expressed in the least significant bits using the rounding operation 524288 = 2 ¹⁹ (corresponding to the 20-bit representation).

With
KT = 1/400 MHz and F0 = 4.913448 GHz
become the parameters of the digitally controlled oscillator 4 designated. KT denotes the amplification factor and F0 denotes the freewheeling frequency of the oscillator.

To complete the PLL still the design parameters for the digital filter 14 and the DCO quantizer 40 (please refer 5 ) needed. The quantizer 40 should have a word width of 14 bits point. It is assumed that the transfer function of the closed PLL is a third-order Butterworth form (-60 dB / decade damping) with a cut-off frequency of
fco = 800 kHz
shows.

In the 8th to 10 Simulation results of such a PLL are displayed. This resulted in a hysteresis of 2 ps in the delta-sigma frequency discriminator 11 based on.

In the upper part of the 8th is the total phase noise of the PLL in the steady state at the frequency output of the digitally controlled oscillator 4 shown above the frequency in Hz. In the lower part of the 8th the integrated average (RMS) jitter versus frequency is plotted in Hz. In both representations, the x-axis represents the frequency offset from the carrier frequency Fgoal. The illustrations show the excellent jitter behavior without annoying frequency tones.

9 shows a representation in which the output frequency of the PLL over time (in s) is plotted. The curve was determined by a simulation calculation using the parameters given above. Shown is the transient response of the PLL and the response of the PLL to a sudden change in parameters in the digitally controlled oscillator 4 ,

The digitally controlled oscillator 4 starts at t = 0 with a freewheeling frequency of 4.913448 GHz. In 9 it can be seen that after 2 μs the target frequency Fgoal of 4.8648 GHz is reached. The frequency change during the transient process is 48,648 MHz.

Parameter changes in the digital PLL can occur either during the manufacturing process or during operation (eg as a temperature drift). Essentially, significant changes can only occur with two parameters: the KT value and the freewheeling frequency. Both parameters relate to the digitally controlled oscillator 4 , The digital processor 1 is insensitive to temperature drifts and other changes.

At time t = 1.68 μs, a sudden, step change in KT gain occurs in the digitally controlled oscillator 4 simulated by 10%. 9 shows that the digitally controlled oscillator 4 After a short transitional period, Fgoal has returned to the target frequency.

In 10 is the corresponding change to the input of the digitally controlled oscillator 4 (ie at the output of the quantization and rate conversion unit 15 ). It becomes clear that the change occurring at 1.68 μs persists. The reason for this is that the simulated change in KT gain in the closed loop must be compensated. A similar result will be with a change in the freewheeling frequency of the digitally controlled oscillator 4 receive.

In summary It should be noted that the present invention is the design of a central circuit part of transmitters and receivers in one technology allows which also for future CMOS Technologies with feature sizes well below the μ-range in particular the use of integrated or discrete capacities can be avoided.

Claims (10)

Digital phase locked loop, with - a digitally controlled oscillator ( 4 ) for generating an output frequency, - a phase detector device ( 11 . 12 . 13 ) for detecting the phase difference between a reference frequency and one of the output frequency of the oscillator ( 4 ) dependent frequency, and for converting the phase difference into a digital control signal, wherein the phase detector means ( 11 . 12 . 13 ) a delta-sigma frequency decider ( 11 ), - a digital loop filter ( 14 ), via which the digital control signal or a digital signal derived from the digital control signal is transmitted to the digitally controlled oscillator ( 4 ) is supplied to adjust the output frequency, and - a delta-sigma frequency decision ( 11 ) downstream digital frequency control device ( 12 ) for generating a frequency signal containing digital signal for driving the loop filter ( 14 ). Digital phase-locked loop according to claim 1, characterized in that the delta-sigma frequency decider ( 11 ) a multi-modulus frequency divider ( 20 ) and a multi-modulus frequency divider downstream phase comparator ( 21 ), wherein the output signal of the phase comparator ( 21 ) a control input ( 23 ) of the multi-modulus frequency divider ( 20 ) for selecting the divider factor of the multi-modulus frequency divider ( 20 ) is fed back. Digital phase locked loop according to one of the preceding claims, characterized in that the digital loop filter ( 14 ) of third or higher order. Digital phase-locked loop according to one of the preceding claims, characterized gekennzeich net that the digital loop filter ( 14 ) of the Butterworth, Bessel, Chebyshev or Cauer type. Digital phase locked loop according to one of the preceding claims, characterized in that the digital loop filter ( 14 ) is a wave digital filter. Digital phase locked loop according to claim 1, characterized by a digital frequency control device ( 12 ) and the digital loop filter ( 14 ) arranged digital integrator ( 13 ). Digital phase locked loop according to one of the preceding claims, characterized by a digital loop filter ( 14 ) downstream quantizer ( 40 . 45 ) which re-quantizes input values to reduced word width output values. Digital phase locked loop according to claim 7, characterized in that the sampling rate of the output values of the quantizer ( 40 . 45 ) compared to the sampling rate of the input values of the quantizer ( 40 . 45 ) is increased. Digital phase locked loop according to claim 8, characterized in that the clock for the quantizer ( 40 . 45 ) by means of a frequency divider ( 42 ) from the output frequency of the digitally controlled oscillator ( 4 ) is derived. Digital phase locked loop according to one of Claims 7 to 9, characterized in that the quantizer ( 45 ) includes a noise shaper for shifting the phase noise to higher frequencies.