EP1998368B8 - Method for manufacturing soi wafer - Google Patents
Method for manufacturing soi wafer Download PDFInfo
- Publication number
- EP1998368B8 EP1998368B8 EP08009380.0A EP08009380A EP1998368B8 EP 1998368 B8 EP1998368 B8 EP 1998368B8 EP 08009380 A EP08009380 A EP 08009380A EP 1998368 B8 EP1998368 B8 EP 1998368B8
- Authority
- EP
- European Patent Office
- Prior art keywords
- soi wafer
- manufacturing soi
- manufacturing
- wafer
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007145624A JP5143477B2 (ja) | 2007-05-31 | 2007-05-31 | Soiウエーハの製造方法 |
Publications (4)
Publication Number | Publication Date |
---|---|
EP1998368A2 EP1998368A2 (en) | 2008-12-03 |
EP1998368A3 EP1998368A3 (en) | 2012-05-23 |
EP1998368B1 EP1998368B1 (en) | 2014-06-04 |
EP1998368B8 true EP1998368B8 (en) | 2014-07-30 |
Family
ID=39789380
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP08009380.0A Active EP1998368B8 (en) | 2007-05-31 | 2008-05-21 | Method for manufacturing soi wafer |
Country Status (5)
Country | Link |
---|---|
US (1) | US8268700B2 (ko) |
EP (1) | EP1998368B8 (ko) |
JP (1) | JP5143477B2 (ko) |
KR (1) | KR101482792B1 (ko) |
TW (1) | TWI456689B (ko) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2935536B1 (fr) | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | Procede de detourage progressif |
EP2200077B1 (en) * | 2008-12-22 | 2012-12-05 | Soitec | Method for bonding two substrates |
JP2011061060A (ja) * | 2009-09-11 | 2011-03-24 | Sumco Corp | 貼り合わせ基板の製造方法 |
FR2961630B1 (fr) | 2010-06-22 | 2013-03-29 | Soitec Silicon On Insulator Technologies | Appareil de fabrication de dispositifs semi-conducteurs |
US8141429B2 (en) * | 2010-07-30 | 2012-03-27 | Rosemount Aerospace Inc. | High temperature capacitive static/dynamic pressure sensors and methods of making the same |
US8338266B2 (en) | 2010-08-11 | 2012-12-25 | Soitec | Method for molecular adhesion bonding at low pressure |
FR2964193A1 (fr) | 2010-08-24 | 2012-03-02 | Soitec Silicon On Insulator | Procede de mesure d'une energie d'adhesion, et substrats associes |
JP5629594B2 (ja) * | 2011-02-09 | 2014-11-19 | 信越化学工業株式会社 | シリコン薄膜転写ウェーハの製造方法および研磨装置 |
CN102431961A (zh) * | 2011-12-07 | 2012-05-02 | 华中科技大学 | 一种低温等离子体活化直接键合的三维硅模具制备方法 |
CN103776660B (zh) | 2012-10-24 | 2016-03-09 | 艾博生物医药(杭州)有限公司 | 一种装置 |
US9202711B2 (en) * | 2013-03-14 | 2015-12-01 | Sunedison Semiconductor Limited (Uen201334164H) | Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness |
US9240357B2 (en) | 2013-04-25 | 2016-01-19 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having preliminary stacked structure with offset oxide etched using gas cluster ion |
DE102014223603B4 (de) | 2014-11-19 | 2018-05-30 | Siltronic Ag | Halbleiterscheibe und Verfahren zu deren Herstellung |
JP6545053B2 (ja) * | 2015-03-30 | 2019-07-17 | 東京エレクトロン株式会社 | 処理装置および処理方法、ならびにガスクラスター発生装置および発生方法 |
CN108695147A (zh) * | 2017-04-08 | 2018-10-23 | 沈阳硅基科技有限公司 | Soi键合硅片的制备方法 |
WO2019236320A1 (en) * | 2018-06-08 | 2019-12-12 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57149301A (en) | 1981-03-11 | 1982-09-14 | Daiichi Togyo Kk | Novel polysaccharide having coagulating property |
EP0387753A1 (de) | 1989-03-17 | 1990-09-19 | Schott Glaswerke | Verfahren und Vorrichtung zum Schutz der proximalen Einkoppelseiten von Laserkathetern |
JP3324469B2 (ja) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JPH11145438A (ja) | 1997-11-13 | 1999-05-28 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP3911901B2 (ja) * | 1999-04-09 | 2007-05-09 | 信越半導体株式会社 | Soiウエーハおよびsoiウエーハの製造方法 |
US6287941B1 (en) | 1999-04-21 | 2001-09-11 | Silicon Genesis Corporation | Surface finishing of SOI substrates using an EPI process |
WO2002005315A2 (en) * | 2000-07-10 | 2002-01-17 | Epion Corporation | System and method for improving thin films by gas cluster ion be am processing |
FR2827078B1 (fr) | 2001-07-04 | 2005-02-04 | Soitec Silicon On Insulator | Procede de diminution de rugosite de surface |
JP2004063730A (ja) * | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
US6774040B2 (en) * | 2002-09-12 | 2004-08-10 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
FR2846788B1 (fr) | 2002-10-30 | 2005-06-17 | Procede de fabrication de substrats demontables | |
JP4509488B2 (ja) | 2003-04-02 | 2010-07-21 | 株式会社Sumco | 貼り合わせ基板の製造方法 |
US7026249B2 (en) * | 2003-05-30 | 2006-04-11 | International Business Machines Corporation | SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
EP1962340A3 (en) * | 2004-11-09 | 2009-12-23 | S.O.I. TEC Silicon | Method for manufacturing compound material wafers |
DE102004054564B4 (de) * | 2004-11-11 | 2008-11-27 | Siltronic Ag | Halbleitersubstrat und Verfahren zu dessen Herstellung |
JP2006210899A (ja) * | 2004-12-28 | 2006-08-10 | Shin Etsu Chem Co Ltd | Soiウエーハの製造方法及びsoiウェーハ |
US7405152B2 (en) * | 2005-01-31 | 2008-07-29 | International Business Machines Corporation | Reducing wire erosion during damascene processing |
JP4934966B2 (ja) * | 2005-02-04 | 2012-05-23 | 株式会社Sumco | Soi基板の製造方法 |
JP5249511B2 (ja) | 2006-11-22 | 2013-07-31 | 信越化学工業株式会社 | Soq基板およびsoq基板の製造方法 |
-
2007
- 2007-05-31 JP JP2007145624A patent/JP5143477B2/ja active Active
-
2008
- 2008-05-14 US US12/153,160 patent/US8268700B2/en active Active
- 2008-05-15 TW TW097117856A patent/TWI456689B/zh not_active IP Right Cessation
- 2008-05-21 EP EP08009380.0A patent/EP1998368B8/en active Active
- 2008-05-30 KR KR20080050893A patent/KR101482792B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
TW200913128A (en) | 2009-03-16 |
US20090023270A1 (en) | 2009-01-22 |
JP2008300660A (ja) | 2008-12-11 |
KR101482792B1 (ko) | 2015-01-14 |
JP5143477B2 (ja) | 2013-02-13 |
EP1998368B1 (en) | 2014-06-04 |
TWI456689B (zh) | 2014-10-11 |
EP1998368A3 (en) | 2012-05-23 |
US8268700B2 (en) | 2012-09-18 |
EP1998368A2 (en) | 2008-12-03 |
KR20080106094A (ko) | 2008-12-04 |
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