EP1987532A1 - Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits - Google Patents

Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits

Info

Publication number
EP1987532A1
EP1987532A1 EP06849411A EP06849411A EP1987532A1 EP 1987532 A1 EP1987532 A1 EP 1987532A1 EP 06849411 A EP06849411 A EP 06849411A EP 06849411 A EP06849411 A EP 06849411A EP 1987532 A1 EP1987532 A1 EP 1987532A1
Authority
EP
European Patent Office
Prior art keywords
film
openings
substrate
contact
laser cutting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06849411A
Other languages
German (de)
English (en)
Inventor
Ladislaus Bittmann
Jörg NAUNDORF
Karl Weidner
Hans Wulkesch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1987532A1 publication Critical patent/EP1987532A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
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    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1062—Prior to assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a method for contacting at least one electrical contact surface on a surface of a substrate and / or a surface of a semiconductor chip arranged on the substrate, with the
  • the invention likewise relates in this way to dielectrically planar contacted substrates and / or semiconductor chips.
  • WO 2003/030247 A2 a method for surface contact of electrical contact surfaces of a substrate and a device made of a substrate with electrical contact surfaces is described.
  • a polyimide or epoxy-based film is vacuum-laminated to the surface such that the film covers and adheres the surface to the contact surfaces, adhering to each contact surface to be contacted
  • the surface is exposed by opening respective windows in the foil and each exposed contact surface is contacted flat with a layer of metal.
  • Herge ⁇ presented devices are particularly power semiconductor chips which require a high current density and have large area contacts.
  • This method is used to produce planar, that is flat, electrical contacts of three-dimensional assemblies.
  • large contact windows must be used in compari- se thick insulating materials are opened.
  • the thicknesses of the insulating materials are conventionally in the range of 200 ⁇ m.
  • the openings in the insulating layers are used in particular for the through-connection of substrate and chip contact surfaces.
  • contact windows are opened by blanket structuring over the entire surface. Conventionally, a range of one cm ⁇ is opened in about 100 seconds. This leads to undesirably long processing times and is therefore disadvantageous in terms of a planned manufacturing process from an economic point of view.
  • the object is achieved by a method according to the main claim and a device according to the independent claim.
  • a time-consuming laser ablation method for producing openings in a foil of electrically insulating plastic material for exposing electrical contact surfaces of a substrate and / or a semiconductor chip is to be improved.
  • Laser cutting means severing, for example a film, along a line by means of a laser whose spatial energy distribution is generated, for example, with a Gaussian profile.
  • a time-consuming ⁇ surface removal as is done for example in a so-called laser ablation avoided. Due to the linear laser cutting devisöff ⁇ can voltages in the film of electrically insulating plastic material be relatively quickly generated. That's it Method and the corresponding manufactured devices inexpensive to provide.
  • a cost-effective structuring method for producing contact openings in the film of electrically insulating plastic material with short processing times is provided. According to the present invention, no surface material removal takes place. It can be a significant reduction in processing times and also a reduction or elimination of Ablationsresten be effected on the contact surfaces. The laser processing times are a major cost factor and thus also decide on the economic viability of electrical planar contactations.
  • a polyimide or epoxy based film is vacuum laminated to the surface so that the film closely overlies the surface with the contact surfaces and adheres to that surface.
  • the film openings are generated according to the individual position of the contact surfaces or according to the individual position of the semiconductor chips, by means of an automatic optical inspection method (AOI) determined data.
  • the film openings are cut according to the individual position of the components according to the determined AOI data.
  • the actual positions of the components for example semiconductor chips, in the x- and y- direction and with respect to a rotation of the components are determined by means of a high-resolution camera. By means of a check window an actual setpoint comparison of the positions is made. The actual positions of contacts or contact surfaces of the components are determined exactly.
  • the laser cutting takes place at a cutting speed in the area around 4 cm per second. In this way, a particularly favorable ratio of cutting time to cut quality is given.
  • the openings in the insulating Bezie ⁇ hung, in the film with respect to the contact surfaces very accurately locate.
  • Such a precise positioning can be particularly advantageous after opening the film, that is to say after the respective openings have been produced, and before the film is laminated onto the substrate or onto the substrate
  • Semiconductor chip to be executed.
  • An adjustment and fixing of the film for the precise positioning of the openings relative to the contact surfaces on the surface is performed by means of geometric shapes.
  • the openings having structured films are in particular by means of geometric
  • At a further advantageous refinement least one opening formed in the film with a geometric rule ⁇ mold is centered on a formed on the substrate structure with a corresponding geometric shape Any artwork.
  • the centering can be done optoelectronically via suitable alignment structures. It is advantageous to create the geometric shape of the opening created equal to the geometric shape of the structure produced.
  • the openings produced in the film and the substrate structures may be referred to as marks.
  • the geometric shapes are crosses, squares or circles.
  • the axis centers of film and structure can be superimposed congruent.
  • the border lines can be matched.
  • Particularly advantageous are point or axisymmetric geometric shapes.
  • the geometric shapes in the film by means of laser, in particular laser cutting can be generated.
  • the geometric structures on the substrate can be produced particularly advantageously by means of etching.
  • the geometric shapes can also be generated by means of plasma etching or mechanical processing methods, in particular punching.
  • Figure 1 shows an embodiment of a device according to the invention
  • Figure 2 shows an embodiment of cut contact openings
  • FIG. 3 shows an exemplary embodiment of adjustment structures.
  • Figure 1 shows an embodiment of a device according to the present invention.
  • semiconductor chips 2 are arranged on a substrate 1 .
  • the reference numeral 4 denotes a Fo ⁇ lie.
  • 1 shows laser cutting contact ⁇ prepared openings in a film, for example with the bottlesbe ⁇ drawing TSA 15 designated films microns with a thickness of 200th Due to positional inaccuracies of the chips, the positions for the contact openings are determined by means of automatic optical inspection (AOI) prior to lamination. In an alternative punching process, the individual position of the chips can not be taken into account.
  • Figure 2 shows an embodiment of laser ⁇ cut cut contact openings 3.
  • the contact openings 3 are showing the openings 3 in the film 4 for a free access to contact pads 6 of the substrate 1 and / or of the semiconductor chip 2.
  • Reference numeral 3 the Kunststofföff ⁇ calculations 3
  • Reference numeral 4 the insulating film 4.
  • the Kunststofföff ⁇ openings 3 are cut analogously to the determined AOI chip positions before lamination.
  • FIG. 3 shows an exemplary embodiment of adjustment structures or geometric shapes 5.
  • the film 4 is adjusted and fixed for precise positioning of the openings 3 relative to the contact surfaces 6 5.
  • on the surfaces of the substrate 1 and the semiconductor chip 2 by means of geometric shapes is at least one centered opening created in the film 4 with a ge ⁇ ometrischen form 5 to a formed on the substrate 1 structure with a corresponding geometric shape.
  • the geometric shape 5 is a cross.
  • the cross on the sub ⁇ can strat 1 are produced by etching.
  • the geometric shape 5 as an opening in the film 4 is here also a cross. This can also be generated by means of laser cutting.
  • FIG. 3 shows alignment structures or geometric shapes 5 in the film 4 and in the underlying substrate 1.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Laser Beam Processing (AREA)
  • Wire Bonding (AREA)

Abstract

La présente invention concerne un procédé conçu pour mettre en contact au moins une surface de contact électrique (6) sur une surface d'un substrat (1) et/ou sur une surface d'une puce à semi-conducteur (2) placée sur le substrat (1). Un film (4) en matière plastique électro-isolante est ensuite appliqué sur lesdites surfaces, puis les surfaces de contact (6) librement accessibles par des ouvertures (3) dans le film sont mises en contact plan avec une couche de matière électroconductrice. Dans le cas d'un procédé de mise en contact électrique plan, des ouvertures (3) doivent être ménagées dans une isolation avec un temps d'usinage court. Les ouvertures (3) doivent notamment être positionnées de façon précise par rapport aux surfaces de contact (6). A cette fin, avant l'étape d'application, chaque ouverture (3) dans le film en matière plastique électro-isolante est ménagée par découpe au laser dans la zone de la surface de contact (6) à mettre en contact. Ce procédé est particulièrement adapté à toutes les opérations de mise en contact électrique plan. Cette invention permet de produire des substrats ou des puces à semi-conducteur (2) ainsi mis en contact. Les puces à semi-conducteur (2) utilisées peuvent notamment être des puces à semi-conducteur de puissance (2).
EP06849411A 2006-02-20 2006-12-20 Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits Withdrawn EP1987532A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102006007795 2006-02-20
DE102006010523A DE102006010523B3 (de) 2006-02-20 2006-03-07 Verfahren zur Herstellung von planaren Isolierschichten mit positionsgerechten Durchbrüchen mittels Laserschneiden und entsprechend hergestellte Vorrichtungen
PCT/EP2006/070021 WO2007096017A1 (fr) 2006-02-20 2006-12-20 Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits

Publications (1)

Publication Number Publication Date
EP1987532A1 true EP1987532A1 (fr) 2008-11-05

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EP06849411A Withdrawn EP1987532A1 (fr) 2006-02-20 2006-12-20 Procédé pour produire des couches isolantes planes présentant des ouvertures conformes à la position au moyen d'une découpe au laser et dispositifs ainsi produits

Country Status (4)

Country Link
US (1) US8191243B2 (fr)
EP (1) EP1987532A1 (fr)
DE (1) DE102006010523B3 (fr)
WO (1) WO2007096017A1 (fr)

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JP5075944B2 (ja) * 2010-06-10 2012-11-21 株式会社東芝 電子機器
CN112224509B (zh) * 2020-09-30 2022-07-08 上海艾为电子技术股份有限公司 一种用于基板贴膜的固定治具及装置

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WO2007096017A1 (fr) 2007-08-30
DE102006010523B3 (de) 2007-08-02
US20090021923A1 (en) 2009-01-22
US8191243B2 (en) 2012-06-05

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