EP1987532A1 - Method for producing planar insulating layers with breakthroughs at the correct position by means of laser cutting and devices produced accordingly - Google Patents

Method for producing planar insulating layers with breakthroughs at the correct position by means of laser cutting and devices produced accordingly

Info

Publication number
EP1987532A1
EP1987532A1 EP06849411A EP06849411A EP1987532A1 EP 1987532 A1 EP1987532 A1 EP 1987532A1 EP 06849411 A EP06849411 A EP 06849411A EP 06849411 A EP06849411 A EP 06849411A EP 1987532 A1 EP1987532 A1 EP 1987532A1
Authority
EP
European Patent Office
Prior art keywords
film
openings
substrate
contact
laser cutting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06849411A
Other languages
German (de)
French (fr)
Inventor
Ladislaus Bittmann
Jörg NAUNDORF
Karl Weidner
Hans Wulkesch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1987532A1 publication Critical patent/EP1987532A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
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    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/2402—Laminated, e.g. MCM-L type
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
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    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
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    • H01L2924/0102—Calcium [Ca]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1062—Prior to assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a method for contacting at least one electrical contact surface on a surface of a substrate and / or a surface of a semiconductor chip arranged on the substrate, with the
  • the invention likewise relates in this way to dielectrically planar contacted substrates and / or semiconductor chips.
  • WO 2003/030247 A2 a method for surface contact of electrical contact surfaces of a substrate and a device made of a substrate with electrical contact surfaces is described.
  • a polyimide or epoxy-based film is vacuum-laminated to the surface such that the film covers and adheres the surface to the contact surfaces, adhering to each contact surface to be contacted
  • the surface is exposed by opening respective windows in the foil and each exposed contact surface is contacted flat with a layer of metal.
  • Herge ⁇ presented devices are particularly power semiconductor chips which require a high current density and have large area contacts.
  • This method is used to produce planar, that is flat, electrical contacts of three-dimensional assemblies.
  • large contact windows must be used in compari- se thick insulating materials are opened.
  • the thicknesses of the insulating materials are conventionally in the range of 200 ⁇ m.
  • the openings in the insulating layers are used in particular for the through-connection of substrate and chip contact surfaces.
  • contact windows are opened by blanket structuring over the entire surface. Conventionally, a range of one cm ⁇ is opened in about 100 seconds. This leads to undesirably long processing times and is therefore disadvantageous in terms of a planned manufacturing process from an economic point of view.
  • the object is achieved by a method according to the main claim and a device according to the independent claim.
  • a time-consuming laser ablation method for producing openings in a foil of electrically insulating plastic material for exposing electrical contact surfaces of a substrate and / or a semiconductor chip is to be improved.
  • Laser cutting means severing, for example a film, along a line by means of a laser whose spatial energy distribution is generated, for example, with a Gaussian profile.
  • a time-consuming ⁇ surface removal as is done for example in a so-called laser ablation avoided. Due to the linear laser cutting devisöff ⁇ can voltages in the film of electrically insulating plastic material be relatively quickly generated. That's it Method and the corresponding manufactured devices inexpensive to provide.
  • a cost-effective structuring method for producing contact openings in the film of electrically insulating plastic material with short processing times is provided. According to the present invention, no surface material removal takes place. It can be a significant reduction in processing times and also a reduction or elimination of Ablationsresten be effected on the contact surfaces. The laser processing times are a major cost factor and thus also decide on the economic viability of electrical planar contactations.
  • a polyimide or epoxy based film is vacuum laminated to the surface so that the film closely overlies the surface with the contact surfaces and adheres to that surface.
  • the film openings are generated according to the individual position of the contact surfaces or according to the individual position of the semiconductor chips, by means of an automatic optical inspection method (AOI) determined data.
  • the film openings are cut according to the individual position of the components according to the determined AOI data.
  • the actual positions of the components for example semiconductor chips, in the x- and y- direction and with respect to a rotation of the components are determined by means of a high-resolution camera. By means of a check window an actual setpoint comparison of the positions is made. The actual positions of contacts or contact surfaces of the components are determined exactly.
  • the laser cutting takes place at a cutting speed in the area around 4 cm per second. In this way, a particularly favorable ratio of cutting time to cut quality is given.
  • the openings in the insulating Bezie ⁇ hung, in the film with respect to the contact surfaces very accurately locate.
  • Such a precise positioning can be particularly advantageous after opening the film, that is to say after the respective openings have been produced, and before the film is laminated onto the substrate or onto the substrate
  • Semiconductor chip to be executed.
  • An adjustment and fixing of the film for the precise positioning of the openings relative to the contact surfaces on the surface is performed by means of geometric shapes.
  • the openings having structured films are in particular by means of geometric
  • At a further advantageous refinement least one opening formed in the film with a geometric rule ⁇ mold is centered on a formed on the substrate structure with a corresponding geometric shape Any artwork.
  • the centering can be done optoelectronically via suitable alignment structures. It is advantageous to create the geometric shape of the opening created equal to the geometric shape of the structure produced.
  • the openings produced in the film and the substrate structures may be referred to as marks.
  • the geometric shapes are crosses, squares or circles.
  • the axis centers of film and structure can be superimposed congruent.
  • the border lines can be matched.
  • Particularly advantageous are point or axisymmetric geometric shapes.
  • the geometric shapes in the film by means of laser, in particular laser cutting can be generated.
  • the geometric structures on the substrate can be produced particularly advantageously by means of etching.
  • the geometric shapes can also be generated by means of plasma etching or mechanical processing methods, in particular punching.
  • Figure 1 shows an embodiment of a device according to the invention
  • Figure 2 shows an embodiment of cut contact openings
  • FIG. 3 shows an exemplary embodiment of adjustment structures.
  • Figure 1 shows an embodiment of a device according to the present invention.
  • semiconductor chips 2 are arranged on a substrate 1 .
  • the reference numeral 4 denotes a Fo ⁇ lie.
  • 1 shows laser cutting contact ⁇ prepared openings in a film, for example with the bottlesbe ⁇ drawing TSA 15 designated films microns with a thickness of 200th Due to positional inaccuracies of the chips, the positions for the contact openings are determined by means of automatic optical inspection (AOI) prior to lamination. In an alternative punching process, the individual position of the chips can not be taken into account.
  • Figure 2 shows an embodiment of laser ⁇ cut cut contact openings 3.
  • the contact openings 3 are showing the openings 3 in the film 4 for a free access to contact pads 6 of the substrate 1 and / or of the semiconductor chip 2.
  • Reference numeral 3 the Kunststofföff ⁇ calculations 3
  • Reference numeral 4 the insulating film 4.
  • the Kunststofföff ⁇ openings 3 are cut analogously to the determined AOI chip positions before lamination.
  • FIG. 3 shows an exemplary embodiment of adjustment structures or geometric shapes 5.
  • the film 4 is adjusted and fixed for precise positioning of the openings 3 relative to the contact surfaces 6 5.
  • on the surfaces of the substrate 1 and the semiconductor chip 2 by means of geometric shapes is at least one centered opening created in the film 4 with a ge ⁇ ometrischen form 5 to a formed on the substrate 1 structure with a corresponding geometric shape.
  • the geometric shape 5 is a cross.
  • the cross on the sub ⁇ can strat 1 are produced by etching.
  • the geometric shape 5 as an opening in the film 4 is here also a cross. This can also be generated by means of laser cutting.
  • FIG. 3 shows alignment structures or geometric shapes 5 in the film 4 and in the underlying substrate 1.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Laser Beam Processing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a method for contacting at least one electric contact surface (6) on a surface of a substrate (1) and/or a surface of a semiconductor chip (2) arranged on a substrate (1). According to the invention, a film (4) of electrically insulating plastic material is laminated onto the surfaces. A large-area contacting of the contact surfaces (6), which are freely accessible via the openings (3) in the film, with a layer of electrically conductive material is then carried out. It is the aim of a planar electric contacting method to produce openings (3) in an insulation during a short period of processing time. In particular, openings (3) are to be positioned at a precise position to the contact surfaces (6). To achieve this, openings (3) are produced in the film of electrically insulating plastic material in the region of the contact surface (6) to be contacted by means of laser cutting and prior to laminating. This method is suitable for all planar contacting processes. Substrates (1) or semiconductor chips (2) which are contacted accordingly may be produced. The semiconductor chips (2) used can be, in particular, power semiconductor chips.

Description

Beschreibungdescription
Verfahren zur Herstellung von planaren Isolierschichten mit positionsgerechten Durchbrüchen mittels Laserschneiden und entsprechend hergestellte VorrichtungenProcess for the production of planar insulating layers with positionally correct openings by means of laser cutting and correspondingly produced devices
Die vorliegende Erfindung betrifft ein Verfahren zum Kontaktieren mindestens einer elektrischen Kontaktfläche auf einer Oberfläche eines Substrats und/oder einer Oberfläche eines auf dem Substrat angeordneten Halbleiterchips, mit denThe present invention relates to a method for contacting at least one electrical contact surface on a surface of a substrate and / or a surface of a semiconductor chip arranged on the substrate, with the
Schritten Auflaminieren einer Folie aus elektrisch isolierendem Kunststoffmaterial auf die Oberfläche und flächiges Kon¬ taktieren der mittels Öffnungen in der Folie frei zugänglichen Kontaktfläche mit einer Schicht aus elektrisch leitendem Material. Die Erfindung betrifft ebenso auf diese Weise e- lektrisch planar kontaktierte Substrate und/oder Halbleiterchips .Steps laminating a film of electrically insulating plastic material on the surface and surface Kon ¬ taktieren the freely accessible by means of openings in the film contact surface with a layer of electrically conductive material. The invention likewise relates in this way to dielectrically planar contacted substrates and / or semiconductor chips.
Gemäß der WO 2003/030247 A2 wird ein Verfahren zum flächigen Kontaktieren elektrischer Kontaktflächen eines Substrats und eine Vorrichtung aus einem Substrat mit elektrischen Kontaktflächen beschrieben. Bei dem Kontaktieren elektrischer Kontaktflächen auf einer Oberfläche eines Substrats wird eine Folie auf Polyimid- oder Epoxidbasis unter Vakuum auf die O- berfläche auflaminiert, so dass die Folie die Oberfläche mit den Kontaktflächen eng anliegend bedeckt und auf dieser Oberfläche haftet, jede zu kontaktierende Kontaktfläche auf der Oberfläche wird durch Öffnen jeweiliger Fenster in der Folie freigelegt und jede freigelegte Kontaktfläche wird mit einer Schicht aus Metall flächig kontaktiert. Entsprechend herge¬ stellte Vorrichtungen sind insbesondere Leistungshalbleiterchips, die eine hohe Stromdichte erfordern und großflächige Kontaktierungen aufweisen.According to WO 2003/030247 A2, a method for surface contact of electrical contact surfaces of a substrate and a device made of a substrate with electrical contact surfaces is described. When contacting electrical contact surfaces on a surface of a substrate, a polyimide or epoxy-based film is vacuum-laminated to the surface such that the film covers and adheres the surface to the contact surfaces, adhering to each contact surface to be contacted The surface is exposed by opening respective windows in the foil and each exposed contact surface is contacted flat with a layer of metal. Accordingly Herge ¬ presented devices are particularly power semiconductor chips which require a high current density and have large area contacts.
Dieses Verfahren dient der Herstellung von planaren, das heißt flächigen, elektrischen Kontaktierungen dreidimensionaler Baugruppen. Für die erforderlichen Durchbrüche in den I- solierschichten müssen große Kontaktfenster in vergleichswei- se dicken Isoliermaterialien geöffnet werden. Die Dicken der Isoliermaterialien liegen herkömmlicher Weise im Bereich von 200 μm. Die Durchbrüche in den Isolierschichten dienen insbesondere der Durchkontaktierung von Substrat- und Chipkontakt- Oberflächen. Auf herkömmliche Weise erfolgt eine Öffnung von Kontaktfenstern über ein ganzflächiges Strukturieren per La- serablation. Dabei wird herkömmlicher Weise ein Bereich von einem cm^ in ca. 100 Sekunden geöffnet. Dies führt zu unerwünscht langen Bearbeitungszeiten und ist damit hinsichtlich eines geplanten Herstellungsverfahrens aus wirtschaftlicher Sicht nachteilig.This method is used to produce planar, that is flat, electrical contacts of three-dimensional assemblies. For the required breakthroughs in the insulating layers, large contact windows must be used in compari- se thick insulating materials are opened. The thicknesses of the insulating materials are conventionally in the range of 200 μm. The openings in the insulating layers are used in particular for the through-connection of substrate and chip contact surfaces. In the conventional manner, contact windows are opened by blanket structuring over the entire surface. Conventionally, a range of one cm ^ is opened in about 100 seconds. This leads to undesirably long processing times and is therefore disadvantageous in terms of a planned manufacturing process from an economic point of view.
Es ist Aufgabe der vorliegenden Erfindung bei einem elektrischen planaren Kontaktierungsverfahren in einer kurzen Bear- beitungszeit Kontaktfenster oder Öffnungen in einem Isoliermaterial bereitzustellen und insbesondere diese Kontaktfens¬ ter oder Öffnungen in Bezug zu Kontaktierungsflachen eines Substrats und/oder eines elektrischen Bauelements beziehungs¬ weise Halbleiterchips sehr genau zu positionieren.It is an object of the present invention to an electrical planar contacting method in a short machining time contact windows or apertures in an insulating material and particularly to provide this Kontaktfens ¬ ter or openings with respect to contact-making surfaces of a substrate and / or an electrical component relationship ¬ as semiconductor chips very accurately to position.
Die Aufgabe wird durch ein Verfahren gemäß dem Hauptanspruch und eine Vorrichtung gemäß dem Nebenanspruch gelöst .The object is achieved by a method according to the main claim and a device according to the independent claim.
Gemäß der vorliegenden Erfindung soll ein zeitaufwändiges La- serablationsverfahren zur Erzeugung von Öffnungen in einer Folie aus elektrisch isolierendem Kunststoffmaterial zur Freilegung von elektrischen Kontaktflächen eines Substrats und/oder eines Halbleiterchips verbessert werden. Es erfolgt ein Öffnen von Kontaktfenstern mittels eines vorteilhaften Laserschneidens. Laserschneiden bedeutet ein Durchtrennen, beispielsweise einer Folie, entlang einer Linie mittels eines Lasers, dessen räumliche Energieverteilung beispielsweise mit einem Gaußprofil erzeugt ist . Auf diese Weise wird ein zeit¬ aufwändiges flächiges Abtragen, wie dies beispielsweise bei einem so genannten Laserablationsverfahren erfolgt, vermieden. Aufgrund des linearen Laserschneidens können Kontaktöff¬ nungen in der Folie aus elektrisch isolierendem Kunststoffmaterial vergleichsweise schnell erzeugt werden. Damit sind das Verfahren und die entsprechend hergestellten Vorrichtungen kostengünstig bereitstellbar. Es wird ein kostengünstiges Strukturierungsverfahren zur Erzeugung von Kontaktierungsöff- nungen in der Folie aus elektrisch isolierendem Kunststoffma- terial mit kurzen Bearbeitungszeiten geschaffen. Gemäß der vorliegenden Erfindung erfolgt kein flächiger Materialabtrag. Es kann eine wesentliche Verkürzung der Bearbeitungszeiten und ebenso eine Reduzierung beziehungsweise Beseitigung von Ablationsresten auf den Kontaktflächen bewirkt werden. Die Laserbearbeitungszeiten sind ein wesentlicher Kostenfaktor und entscheiden damit ebenso über die Wirtschaftlichkeit e- lektrischer planarer Kontaktierungen. Bei dem Kontaktieren elektrischer Kontaktflächen auf einer Oberfläche eines Substrats wird eine Folie auf Polyimid- oder Epoxidbasis unter Vakuum auf die Oberfläche auflaminiert, so dass die Folie die Oberfläche mit den Kontaktflächen eng anliegend bedeckt und auf dieser Oberfläche haftet .According to the present invention, a time-consuming laser ablation method for producing openings in a foil of electrically insulating plastic material for exposing electrical contact surfaces of a substrate and / or a semiconductor chip is to be improved. There is an opening of contact windows by means of an advantageous laser cutting. Laser cutting means severing, for example a film, along a line by means of a laser whose spatial energy distribution is generated, for example, with a Gaussian profile. In this way, a time-consuming ¬ surface removal, as is done for example in a so-called laser ablation avoided. Due to the linear laser cutting Kontaktöff ¬ can voltages in the film of electrically insulating plastic material be relatively quickly generated. That's it Method and the corresponding manufactured devices inexpensive to provide. A cost-effective structuring method for producing contact openings in the film of electrically insulating plastic material with short processing times is provided. According to the present invention, no surface material removal takes place. It can be a significant reduction in processing times and also a reduction or elimination of Ablationsresten be effected on the contact surfaces. The laser processing times are a major cost factor and thus also decide on the economic viability of electrical planar contactations. In contacting electrical contact surfaces on a surface of a substrate, a polyimide or epoxy based film is vacuum laminated to the surface so that the film closely overlies the surface with the contact surfaces and adheres to that surface.
Weitere vorteilhafte Ausgestaltungen finden sich in den Un- teransprüchen .Further advantageous embodiments can be found in the dependent claims.
Gemäß einer vorteilhaften Ausgestaltung werden die Folienöffnungen entsprechend der individuellen Lage der Kontaktflächen oder entsprechend der individuellen Lage der Halbleiterchips, mittels eines automatischen optischen Inspektionsverfahrens (AOI) ermittelter Daten erzeugt. Die Folienöffnungen werden entsprechend der individuellen Lage der Bauelemente nach den ermittelten AOI-Daten geschnitten. Gemäß dem AOI werden mittels einer hoch auflösenden Kamera die Ist-Positionen der Bauteile, beispielsweise Halbleiterchips, in x- und y- Rich¬ tung und hinsichtlich einer Verdrehung der Bauteile, bestimmt. Mittels eines Prüffensters wird ein Ist- Sollwertvergleich der Positionen vorgenommen. Die tatsächlichen Positionen von Kontakten beziehungsweise Kontaktflächen der Bauteile werden genau bestimmt.According to an advantageous embodiment, the film openings are generated according to the individual position of the contact surfaces or according to the individual position of the semiconductor chips, by means of an automatic optical inspection method (AOI) determined data. The film openings are cut according to the individual position of the components according to the determined AOI data. According to the AOI, the actual positions of the components, for example semiconductor chips, in the x- and y- direction and with respect to a rotation of the components are determined by means of a high-resolution camera. By means of a check window an actual setpoint comparison of the positions is made. The actual positions of contacts or contact surfaces of the components are determined exactly.
Gemäß einer weiteren vorteilhaften Ausgestaltung erfolgt das Laserschneiden mit einer Schnittgeschwindigkeit im Bereich um 4 cm pro Sekunde. Auf diese Weise ist ein besonders günstiges Verhältnis von Schnittdauer zur Schnittqualität gegeben.According to a further advantageous embodiment, the laser cutting takes place at a cutting speed in the area around 4 cm per second. In this way, a particularly favorable ratio of cutting time to cut quality is given.
Gemäß einer weiteren vorteilhaften Ausgestaltung ist es be- sonders vorteilhaft, die Öffnungen im Isoliermaterial bezie¬ hungsweise in der Folie mit Bezug zu den Kontaktflächen sehr genau anzuordnen. Ein derartig präzises Positionieren kann besonders vorteilhaft nach dem Öffnen der Folie, das heißt nach dem Erzeugen jeweiliger Öffnungen, und vor dem Auflami- nieren der Folie auf das Substrat beziehungsweise auf denAccording to a further advantageous refinement, it is sawn Sonders advantageous, the openings in the insulating Bezie ¬ hung, in the film with respect to the contact surfaces very accurately locate. Such a precise positioning can be particularly advantageous after opening the film, that is to say after the respective openings have been produced, and before the film is laminated onto the substrate or onto the substrate
Halbleiterchip ausgeführt werden. Ein Justieren und Fixieren der Folie zur genauen Positionierung der Öffnungen relativ zu den Kontaktflächen auf der Oberfläche wird mittels geometrischer Formen durchgeführt. Die Öffnungen aufweisenden struk- turierten Folien werden insbesondere mittels geometrischerSemiconductor chip to be executed. An adjustment and fixing of the film for the precise positioning of the openings relative to the contact surfaces on the surface is performed by means of geometric shapes. The openings having structured films are in particular by means of geometric
Formen relativ zum Substrat justiert, danach fixiert und dar¬ auf folgend laminiert .Forms adjusted relative to the substrate, then fixed and is ¬ laminated on the following.
Gemäß einer weiteren vorteilhaften Ausgestaltung wird mindes- tens eine in der Folie erzeugte Öffnung mit einer geometri¬ schen Form auf einer auf dem Substrat erzeugte Struktur mit einer entsprechenden geometrischen Form zentriert. Die Zentrierung kann über geeignete Justierstrukturen optoelektronisch erfolgen. Dabei ist vorteilhaft die geometrische Form der erzeugten Öffnung gleich der geometrischen Form der erzeugten Struktur zu schaffen. Dabei können die in der Folie erzeugten Öffnungen und die Substratstrukturen als Marken bezeichnet werden. Bei einer Zentrierung können Symmetrieachsen und/oder Symmetriepunkte oder allgemein Achsen oder Punkte der geometrischen Formen zur Deckung gebracht werden.According to a further advantageous refinement least one opening formed in the film with a geometric rule ¬ mold is centered on a formed on the substrate structure with a corresponding geometric shape Any artwork. The centering can be done optoelectronically via suitable alignment structures. It is advantageous to create the geometric shape of the opening created equal to the geometric shape of the structure produced. In this case, the openings produced in the film and the substrate structures may be referred to as marks. When centering symmetry axes and / or points of symmetry or generally axes or points of the geometric shapes can be brought to coincide.
Gemäß weiteren vorteilhaften Ausgestaltungen sind die geometrischen Formen Kreuze, Quadrate oder Kreise. Bei Verwendung von Kreuzen können die Achsenmittelpunkte von Folie und Struktur deckungsgleich überlagert werden. Bei Verwendung von Quadraten oder Kreisen können die Umrandungslinien zur Übereinstimmung gebracht werden. Besonders vorteilhaft sind punkt- oder achsensymmetrische geometrische Formen. Gemäß einer weiteren vorteilhaften Ausgestaltung können die geometrischen Formen in der Folie mittels Laser, insbesondere Laserschneiden erzeugt werden. Die geometrischen Strukturen auf dem Substrat können besonders vorteilhaft mittels Ätzen erzeugt werden. Die geometrischen Formen können ebenso mittels Plasma-Ätzen oder mechanische Bearbeitungsverfahren insbesondere Stanzen erzeugt werden.According to further advantageous embodiments, the geometric shapes are crosses, squares or circles. When using crosses, the axis centers of film and structure can be superimposed congruent. When using squares or circles, the border lines can be matched. Particularly advantageous are point or axisymmetric geometric shapes. According to a further advantageous embodiment, the geometric shapes in the film by means of laser, in particular laser cutting can be generated. The geometric structures on the substrate can be produced particularly advantageously by means of etching. The geometric shapes can also be generated by means of plasma etching or mechanical processing methods, in particular punching.
Vom Schutzumfang umfasst sind ebenso alle Substrate und/oder Halbleiterchips, die nach einem oder mehreren der vorangehenden Verfahren elektrisch planar kontaktiert wurden.Also included in the scope of protection are all substrates and / or semiconductor chips which have been contacted in an electrically planar manner according to one or more of the preceding methods.
Die vorliegende Erfindung wird anhand von Ausführungsbeispie- len in Verbindung mit den Figuren näher beschreiben. Es zeigenThe present invention will be described in more detail by means of exemplary embodiments in conjunction with the figures. Show it
Figur 1 ein Ausführungsbeispiel einer erfindungsgemäßen Vorrichtung;Figure 1 shows an embodiment of a device according to the invention;
Figur 2 ein Ausführungsbeispiel von ausgeschnittenen Kontaktöffnungen;Figure 2 shows an embodiment of cut contact openings;
Figur 3 ein Ausführungsbeispiel von Justagesstrukturen .FIG. 3 shows an exemplary embodiment of adjustment structures.
Figur 1 zeigt ein Ausführungsbeispiel einer Vorrichtung gemäß der vorliegenden Erfindung. Auf einem Substrat 1 sind Halbleiterchips 2 angeordnet. Deutlich sichtbar sind die mittels Öffnungen 3 in der Folie freigelegten Kontaktflächen 6 der Halbleiterchips 2. Das Bezugszeichen 4 kennzeichnet eine Fo¬ lie. Figur 1 zeigt mit Laserschneiden hergestellte Kontakt¬ öffnungen in einer Folie, beispielsweise mit der Handelsbe¬ zeichnung TSA 15 bezeichnete Folien, mit einer Dicke von 200 μm. Aufgrund von Lageungenauigkeiten der Chips werden die Po- sitionen für die Kontaktöffnungen mittels automatischer optischer Inspektion (AOI) vor dem Laminieren ermittelt. Bei einem alternativen Stanzprozess kann die individuelle Lage der Chips nicht berücksichtigt werden. Figur 2 zeigt ein Ausführungsbeispiel von mittels Laser¬ schneiden ausgeschnittenen Kontaktöffnungen 3. Die Kontaktöffnungen 3 sind die Öffnungen 3 in der Folie 4 für einen freien Zugang zu Kontaktflächen 6 des Substrats 1 und/oder des Halbleiterchips 2. Bezugszeichen 3 zeigt die Kontaktöff¬ nungen 3. Bezugszeichen 4 die Isolierfolie 4. Die Kontaktöff¬ nungen 3 werden analog der ermittelten AOI-Chip-Positionen vor dem Laminieren geschnitten.Figure 1 shows an embodiment of a device according to the present invention. On a substrate 1 semiconductor chips 2 are arranged. Clearly visible are the exposed by means of openings 3 in the film contact surfaces 6 of the semiconductor chip 2. The reference numeral 4 denotes a Fo ¬ lie. 1 shows laser cutting contact ¬ prepared openings in a film, for example with the Handelsbe ¬ drawing TSA 15 designated films microns with a thickness of 200th Due to positional inaccuracies of the chips, the positions for the contact openings are determined by means of automatic optical inspection (AOI) prior to lamination. In an alternative punching process, the individual position of the chips can not be taken into account. Figure 2 shows an embodiment of laser ¬ cut cut contact openings 3. The contact openings 3 are showing the openings 3 in the film 4 for a free access to contact pads 6 of the substrate 1 and / or of the semiconductor chip 2. Reference numeral 3 the Kontaktöff ¬ calculations 3 Reference numeral 4, the insulating film 4. The Kontaktöff ¬ openings 3 are cut analogously to the determined AOI chip positions before lamination.
Figur 3 zeigt ein Ausführungsbeispiel von Justagestrukturen beziehungsweise geometrischen Formen 5. Nach dem Erzeugen von Öffnungen 3 in der Folie 4 und vor dem Auflaminieren der Folie 4 erfolgt ein Justieren und Fixieren der Folie 4 zur ge- nauen Positionierung der Öffnungen 3 relativ zu den Kontaktflächen 6 auf den Oberflächen des Substrats 1 beziehungsweise des Halbleiterchips 2 mittels geometrischer Formen 5. Es wird mindestens eine in der Folie 4 erzeugte Öffnung mit einer ge¬ ometrischen Form 5 zu einer auf dem Substrat 1 erzeugten Struktur mit einer entsprechenden geometrischen Form 5 zentriert. Gemäß dem Ausführungsbeispiel ist die geometrische Form 5 ein Kreuz. Beispielsweise kann das Kreuz auf dem Sub¬ strat 1 mittels Ätzen erzeugt werden. Die geometrische Form 5 als Öffnung in der Folie 4 ist hier ebenso ein Kreuz. Dieses kann ebenso mittels Laserschneiden erzeugt sein. Um das ge¬ ätzte Kreuz des Substrats 1 ist eine Kupferschicht sichtbar. Es ist ebenso möglich das Kreuz 5 auf dem Substrat 1 als Kup¬ ferschicht auszubilden, die von weg geätzten Bereichen des Substrats 1 umgeben ist. Die Mitte des Kreuzes 5 der Folie 4 wird auf die Mitte des Kreuzes 5 des Substrats 1 geschoben und damit erfolgt die Zentrierung. Besonders vorteilhaft ist die Verwendung von zwei derartigen Zentrierungsstellen. Diese können beispielsweise diagonal zueinander angeordnet sein. Andere Positionen zueinander sind ebenso möglich. Die Zent- rierung kann manuell mittels eines Mikroskops erfolgen, auto¬ matische Zentrierungen beispielsweise mittels eines Automaten sind ebenso möglich. Figur 3 zeigt JustageStrukturen beziehungsweise geometrische Formen 5 in der Folie 4 und in dem darunter liegenden Substrat 1. Das Justieren der Folie 4 zum Substrat 1 erfolgt al¬ so über die entsprechenden Strukturen mit den geometrischen Formen 5. Es kommt insbesondere ein so genanntes "Panelalign- ment" zur Anwendung. Es ist besonders vorteilhaft, wenn ein Halbleiterchip 2 ein Leistungshalbleiterchip ist. FIG. 3 shows an exemplary embodiment of adjustment structures or geometric shapes 5. After producing openings 3 in the film 4 and before laminating the film 4, the film 4 is adjusted and fixed for precise positioning of the openings 3 relative to the contact surfaces 6 5. on the surfaces of the substrate 1 and the semiconductor chip 2 by means of geometric shapes is at least one centered opening created in the film 4 with a ge ¬ ometrischen form 5 to a formed on the substrate 1 structure with a corresponding geometric shape. 5 According to the embodiment, the geometric shape 5 is a cross. For example, the cross on the sub ¬ can strat 1 are produced by etching. The geometric shape 5 as an opening in the film 4 is here also a cross. This can also be generated by means of laser cutting. In order ge ¬ etched cross of the substrate 1, a copper layer is visible. It is also possible to form the cross ferschicht 5 on the substrate 1 as Kup ¬, which is surrounded by the etched away portions of the substrate. 1 The center of the cross 5 of the film 4 is pushed onto the center of the cross 5 of the substrate 1 and thus the centering takes place. Particularly advantageous is the use of two such centering points. These may for example be arranged diagonally to each other. Other positions to each other are also possible. The centering can be done manually by means of a microscope, auto ¬ matic centering, for example by means of a machine are also possible. FIG. 3 shows alignment structures or geometric shapes 5 in the film 4 and in the underlying substrate 1. The adjustment of the film 4 to the substrate 1 takes place al ¬ so on the corresponding structures with the geometric shapes 5. It comes in particular a so-called "Panelalign - ment "for use. It is particularly advantageous if a semiconductor chip 2 is a power semiconductor chip.

Claims

Patentansprüche claims
1. Verfahren zum Kontaktieren mindestens einer elektrischen Kontaktfläche (6) auf einer Oberfläche eines Substrats (1) und/oder einer Oberfläche eines auf dem Substrat (1) angeord¬ neten elektronischen Bauelements (2), mit den Schritten1. A method for contacting at least one electrical contact surface (6) on a surface of a substrate (1) and / or a surface of an on the substrate (1) angeord ¬ Neten electronic component (2), with the steps
- Auflaminieren einer Folie (4) aus elektrisch isolierendem Kunststoffmaterial auf die Oberfläche, und- Laminating a film (4) made of electrically insulating plastic material on the surface, and
- flächiges Kontaktieren der mittels Öffnungen (3) in der Fo- lie (4) frei zugänglichen Kontaktfläche (6) mit einer Schicht aus elektrisch leitendem Material, dadurch gekennzeichnet, dass vor dem Auflaminieren ein Erzeugen jeweiliger Öffnungen (3) in der Folie (4) im Bereich der zu kontaktierenden Kontaktfläche (6) mittels Laserschneiden erfolgt .- surface contact of the openings (3) in the film (4) freely accessible contact surface (6) with a layer of electrically conductive material, characterized in that prior to the lamination generating respective openings (3) in the film (4 ) in the region of the contact surface (6) to be contacted by means of laser cutting.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Folienöffnungen (3) entsprechend der individuellen Lage der Kontaktflächen (6) entsprechend ermittelter Daten gemäß Automatischer Optischer Inspektion (AOI) erzeugt werden.2. The method according to claim 1, characterized in that the film openings (3) corresponding to the individual position of the contact surfaces (6) according to determined data according to Automatic Optical Inspection (AOI) are generated.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass das Laserschneiden mit einer Schnittgeschwindigkeit von circa 4cm/s ausgeführt wird.3. The method according to claim 1 or 2, characterized in that the laser cutting is performed at a cutting speed of about 4cm / s.
4. Verfahren nach Anspruch 1, 2 oder 3, dadurch gekennzeichnet, dass nach dem Öffnen und vor dem Auflaminieren ein Justieren und4. The method of claim 1, 2 or 3, characterized in that after opening and before the lamination an adjustment and
Fixieren der Folie (4) zur genauen Positionierung der Öffnungen (3) relativ zu den Kontaktflächen (6) auf den Oberflächen mittels geometrischen Formen (5) erfolgt.Fixing the film (4) for accurate positioning of the openings (3) relative to the contact surfaces (6) on the surfaces by means of geometric shapes (5).
5. Verfahren nach Anspruch 4, dadurch gekennzeichnet, dass mindestens eine in der Folie (4) erzeugte Öffnung mit einer geometrischen Form (5) zu einer auf dem Substrat (1) erzeug- ten Struktur mit einer entsprechenden geometrischen Form (5) zentriert wird.5. The method according to claim 4, characterized in that at least one in the film (4) produced opening with a geometric shape (5) to a on the substrate (1) produced on the th structure with a corresponding geometric shape (5) is centered.
6. Verfahren nach Anspruch 4 oder 5, dadurch gekennzeichnet, dass die geometrischen Formen (5) Kreuze, Quadrate oder Kreise sind.6. The method according to claim 4 or 5, characterized in that the geometric shapes (5) are crosses, squares or circles.
7. Verfahren nach Anspruch 4, 5 oder 6, dadurch gekennzeichnet, dass die geometrischen Formen (5) mittels Lasers, insbesondere La¬ serschneiden, und/oder Ätzen und/oder Stanzen erzeugt werden7. The method according to claim 4, 5 or 6, characterized in that the geometric shapes (5) by means of laser, in particular La ¬ serschneiden, and / or etching and / or punching are generated
8. Vorrichtung dadurch gekennzeichnet, dass dieses ein Substrat (1) und/oder ein elektronisches Bauele¬ ment (2) sind/ist, die/das/der nach einem oder mehreren der vorangehenden Verfahren 1 bis 7 elektrisch, planar kontaktiert wurde/n.8. A device characterized in that it is a substrate (1) and / or an electronic Bauele ¬ ment (2) /, the / electrically the / key according to one or more of the preceding processes 1 to 7, was contacted planar / n ,
9. Vorrichtung nach Anspruch 9, dadurch gekennzeichnet, dass das elektronische Bauelement ein Halbleiterchip (2), ein Leistungshalbleiterchip, ein LED-Chip, ein Surface Mounted Device-Bauteil oder ein passives Bauelement ist. 9. Device according to claim 9, characterized in that the electronic component is a semiconductor chip (2), a power semiconductor chip, an LED chip, a surface mounted device component or a passive component.
EP06849411A 2006-02-20 2006-12-20 Method for producing planar insulating layers with breakthroughs at the correct position by means of laser cutting and devices produced accordingly Withdrawn EP1987532A1 (en)

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DE102006010523A DE102006010523B3 (en) 2006-02-20 2006-03-07 Method and device for contacting an electrical contact surface on a substrate and/or a component on the substrate laminates an insulating film with laser-cut openings and applies electrically conductive material
PCT/EP2006/070021 WO2007096017A1 (en) 2006-02-20 2006-12-20 Method for producing planar insulating layers with breakthroughs at the correct position by means of laser cutting and devices produced accordingly

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