Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
  • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Definitions

• the present invention relates to a method of estimating the noise generated in an electronic system and a method of assaying associated immunity.
• the purpose of the invention is notably to determine the good or the bad operation of the system from a noise analysis in this system.
• the invention has a particularly advantageous application in the field of mixed electronic systems comprising analog and digital components.
• electronic systems include integrated circuits on a single silicon block, or on several silicon substrates in the same housing, as well as the assembly of components (integrated or not) on a printed circuit.
• noise generating circuits the aggressors
• noise sensitive circuits the victims
• noise generators all the circuits of the system can be considered as noise generators (aggressors).
• noise generating circuits in the group comprising: digital circuits, memory cells, analog and radio-frequency (RF) circuits, such as VCOs (Voltage Controllers). Oscillator in English), power amplifiers, and input-output circuits.
• RF radio-frequency
• digital circuits tend to generate noise when switching their input signals.
• a circuit comprising at least one noise generating circuit is itself considered as a noise generating circuit.
• the noise-sensitive circuits are selected from the group consisting of: analog and RF circuits, such as amplifiers, filters, oscillators, mixers, sample-and-hold devices, memory type digital circuits, phase, input-output circuits and voltage references.
• analog and RF circuits such as amplifiers, filters, oscillators, mixers, sample-and-hold devices, memory type digital circuits, phase, input-output circuits and voltage references.
• a circuit comprising at least one noise-sensitive circuit is itself considered to be sensitive to noise.
• noise generated by the aggressors spreads to the victims through the substrates on which the circuits, the metal interconnections and the housings are mounted. This noise tends to degrade the performance of the victims. Thus, noise is any signal generated by an aggressor block that has an unwanted influence on the victims.
• SPICE software such as SPICE makes it possible to analyze the effect of the aggressor blocks on the victims.
• impedance models to the SPICE models of the original mixed system to model the substrate.
• SPICE models require too much system resources. For these large systems, it is therefore rather implement processes that use approximate models of the substrate and model the injection of noise into the substrate by current sources.
• a cell is an elementary system of the analog or digital type circuit.
• a cell performs a given function, and can take the form of a logic gate or a set of logic gates, for example.
• Each cell is associated with a macro-model that models the noise injected by the cell into the substrate, the parasitic elements of the cell and the connection to the rest of the system.
• This macro-model includes current sources that inject a noise current into the interior of the substrate, for example, a switching noise current generated by the cell.
• the macro-model includes resistors, capacitors and possibly inductors that model links between the terminals of the cell, the supply nodes and the connection to the substrate.
• the noise current injected by the cell is calculated using a very detailed simulation model of the cell.
• the noise associated with a cell is then calculated by switching its inputs. Switching patterns that characterize the passage of the inputs of the cell from one state to another are thus defined for a given extraction phase. And during an application of these switching patterns on the input terminals of a cell, the noise generating currents of this cell are measured and extracted.
• the macro models of the cells and the noise signals they generate are combined by introducing a switching delay between the changes of state of the cells. Because the cells do not inject all the noise at the same time into the substrate. The macro-models and the noise signals are thus combined according to a modeling of the switching instants of the cells of the circuit.
• the method presented in document US-6941258 proposes to calculate an overall macro-model of the whole circuit which is a combination of the macro-models of the cells of the circuit, while taking into account the offsets in the injection of noise by the cells in the rest of the integrated circuit.
• the noise sources of this global macro-model are thus combinations of the noise sources of the macro-models of each cell.
• Such a noise calculation method makes it possible to simulate the noise that can be observed in a single-silicon integrated circuit and to obtain results that are close to reality. Indeed, the result of this simulation is close to that obtained by a transistor simulation of digital circuits.
• a simulation method does not allow to affirm with certainty the proper functioning of a circuit. Indeed, this method determines the noise injected only in the integrated circuit substrate and does not include not account for the noise associated with the interconnections of the cells with each other, whether on silicon, in housings or on printed circuit boards.
• this method is a simulation closest to that allows to have a precise idea of the average noise generated by the digital circuits.
• this method does not take into account the marginal operations of the system in terms of switching activity, nor the unpredictability of production that can degrade the performance of the system.
• the present invention therefore proposes to provide more relevant information on the noise injected into the electronic system so that it can be definitely determined whether the desired operation of the system is substantially affected or not by the noise injected by its cells, in particular by its digital cells.
• the invention calculates, in a worst case, the highest noise that can be observed in the system.
• all the cells inject into the system the highest noise that they can inject.
• the test fails, that is to say that the noise calculated in the system is higher than the tolerance thresholds of the sensitive circuits, then one computes by simulation in the best case, the lowest possible noise being able to be observed in the system. In one implementation, to calculate this noise, all the cells inject into the system the lowest noise that they can inject.
• noise sensitivity test fails in this best case, then the architecture of the system is strongly questioned and often the whole system needs to be modified to fulfill noise immunity requirements. For this purpose, it will be necessary to modify the positioning of the components, the distribution of the input / output signals on the terminals of the integrated circuits, and introduce, if necessary, shieldings around the victims of the noise. A failure Best case testing may also require the use of a more expensive case for embedded components.
• the sensitivity test fails in the worst case but succeeds in the best case, then some aspects of the system need to be changed.
• Other modelizations can still be implemented, like a modeling of the average case where the system is modeled with sources of noise which inject a medium noise into the substrate. All these modelizations of the system and the noise sensitivity tests associated with them give indications on the noise immunity of the system to be tested. It should be noted that the extreme cases of noise injection are developed taking into account the reality of their occurrence. Indeed, to make sense, the best and the worst case must be able to be met in a mode of operation of the system. The worst case (respectively best case) should not be too pessimistic (respectively too optimistic) so as to give a precise idea of the noise immunity of the studied system.
• a macromodel of the noise injected into the system through the substrate, the interconnections and the cell housing is defined for each circuit of the system.
• This macro-model comprises a set of sources that represent the different modes of noise injection (worst case and worst case), as well as a set of passive elements, in particular capacitances, resistances and inductances, which translate the interactions interferences between the different sources of the model as well as the couplings with the substrate, the interconnections and the housing components.
• the modeling of the sources of noise is adjusted, the passive elements of the macromodels of the circuits remaining identical from one case to another.
• the current sources are extracted from this macro-model. For that, we first model each cell in the most precise way possible by using the most complete possible models of transistors, available in the Designkit of the elementary digital cells (or Corelib). A test environment is then defined for the cell to be tested, which environment is defined by input voltage sources having a particular rise / fall time between two state changes, a capacitive load connected to each output of the cell, and a power supply model.
• Input voltage sources are subject to switching patterns. These switching patterns define the passage of the inputs of the cell from one voltage level to another. These reasons can be exhaustive, that is to say that all the variations of possible entries will be applied at the input of the cell, or pseudo exhaustive, that is to say that only part of the input variations possible will be applied to the input of the cell.
• SPICE simulation of the cell in its test environment waveforms (one for each switching reason) are obtained for which a statistical classification is made. These waveforms can thus be classified according to their spectral density.
• the waveforms are transposed in the frequency domain and are then approximated by polynomial functions that facilitate the storage of these waveforms and the reuse of these waveforms for the reconstitution of a sum of currents injected into the system by a given block.
• circuit in an electronic system means elements that can be at various levels of block hierarchy.
• the first level is a component such as a transistor.
• the second level is a basic function such as an AND gate or an OR gate.
• the third level is an assembly of elementary functions to perform a given function, the number of levels of hierarchy being not limited.
• an equivalent noise injection model is defined that models the current noise injection during current calls at the cell level.
• a modeling of the activity of switching that defines when the digital blocks or the cells that compose them inject their noise into the system.
• the noise can be calculated in the system for blocks of different hierarchy, the noise of these blocks can then be combined with each other to calculate the overall noise observable in the system.
• Each injection model can be refined in terms of the definition of the macro-model, the definition of the sets of parameters chosen for the extraction of current sources in the various cases considered, and the reuse of noise sources within a block. according to a distribution of switching times of the cells.
• the method according to the invention can be implemented with an electronic system comprising a single integrated silicon circuit in its case, a plurality of silicon integrated circuits in a case, or a plurality of electronic components, optionally with integrated circuits connected to a circuit. printed.
• the invention therefore relates to a method for estimating a noise generated in a mixed system of digital, and analog and / or radio frequency, this system comprising elementary cells each performing a function, this method comprising the following steps: model each digital and / or analog and / or radiofrequency cell by a noise injection macro-model, this macro-model comprising current sources for modeling the noise injected into the system by the cell,
• the step of reuse of the sources within the macro-models comprises the next step :
• the invention furthermore relates to a noise immunity test method of a mixed system of digital and analog and / or radio frequency type, this system comprising cells interconnected via nodes of the circuit, each node corresponding to a connection between two cells or between a cell and a power supply network of the system, this method comprising the following steps:
• these macro-models including passive connection elements of the RLC type, and noise sources that model a noise injection by the cells in the system, - connect these macro-models with the rest of the system using the connection elements of these macro-models,
• the source reuse step within the macro-models comprises the following step:
• FIG. 1 a schematic representation of a conventional mixed electronic system comprising digital and analog cells
• FIG. 2 a schematic representation of a known macro-model modeling a digital cell
• FIG. 3 a schematic representation of a cell and its test environment for extracting sources of noise in the method according to the invention
• FIG. 4 a block diagram representing the steps of extraction of the noise sources of the macro-models and the reuse of these sources in the method according to the invention
• FIGS. 5 graphical representations of waveforms obtained in the time domain and in the frequency domain for different switching patterns during extraction of the noise sources according to the invention
• FIG. 6 a histogram representing the number of cells of the system that can be called on each time interval [ti; ti + 1 [;
• FIG. 7 a table according to the invention indicating a decision of acceptance or non-acceptance of systems based on sensitivity test results in different cases of operation of these systems.
• FIG. 1 shows an integrated circuit 1 which includes cells 2.1.
• These cells which may for example be sets of logic gates, are mounted on a substrate 3 of this circuit 1.
• the digital cells inject noise into the circuit during their switching operation.
• the injection of the noise of each digital cell inside the substrate 3 can be modeled by a known macro-model 4 represented in FIG. 2.
• This macro-model 4 comprises four current sources IPvdd, IPgnd, IBsub and IBcais which model the noise generated by the switching of the NMOS and PMOS transistors, and injected into the rest of the circuit 1, the substrate 3 and all the interconnections and power networks of the circuit 1.
• the IPvdd current is the current consumed by the cell for switching.
• the current IPgnd is different from the supplied current IPvdd, since a part of the supplied current IPvdd is diverted to output charges and to the substrate 3 of the circuit.
• Current IBsub is a leakage current to the substrate, while current IBcais is a leakage current to the box of circuit 1.
• the links between terminals of the cell and the substrate 3 are modeled by these impedances Z1-Z6 connected to each other.
• a capacitor C connecting two resistor networks models the connection between the portion of the N-doped substrate and the P-doped substrate.
• the macro-model 4 is connected to the rest of the integrated circuit 1 via resistors R1-R4.
• the values of elements Z1-Z6, C and R1-R4, which depend in particular on a geometry of the cell, are known a priori for each cell studied.
• the macro-models may comprise several power supplies.
• the parasitic elements of the NMOS and PMOS structures can also be modeled differently.
• each cell 2.1-2.4 is modeled in a test environment.
• Cell 2.1 which has inputs E1-EN and outputs S1-SM is thus represented in its test environment in FIG. 3.
• test environment is meant all the parameters outside the cell which have an influence on its behavior, in particular on the noise that it is likely to inject in the circuit 1.
• this cell 2.1 is modeled using a model contained in a set of data files called Designkit. These data files are used by digital circuit design and verification software of the VHDL, SPICE, or VITAL type. This model precisely models each physical phenomenon occurring in cell 2.1, and allows a modeling of the different modes of noise injection of the transistors that compose it.
• the cell 2.1 is modeled by a SPICE model of the EKV, MM9, BSIM3v3 or BSIM4 type, and various parasitic elements, such as capacitors, resistors, and diodes.
• Cell 2.1 is powered by a generator 4 that can be modeled as being ideal. However, it is also possible to a generator model that models the parasites and couplings of the supply lines to each digital cell.
• the rise times RT and the descent times FT of the signals U1-UN applied to the inputs E1-EN of the cell 2.1 are fixed.
• These rise times RT and descent FT can be the minimum, maximum or average switching times of the digital cells that can control the inputs of the cell in question.
• the value of the capacitive charges C1-CM connected to the outputs S1-SM of the cell 2.1 is fixed. These C1-CM charges correspond to an internal input capacity of subsequent cells connected to the outputs of cell 2.1.
• Several sets of capabilities can be used, the output capacitance values influencing cell switching times, as well as the noise generated by the switching cell 2.1.
• the switching patterns that will be applied to the inputs E1-EN of the circuit are then defined using U1-UN. It is recalled that these patterns define the passage of the levels of the inputs of the cell from one state to another. For example, a switching pattern is shown at the top right of FIG. 3.
• a switching pattern is shown at the top right of FIG. 3.
• the number of states that can change in the pattern is defined.
• a number of switching patterns are chosen to be applied to the inputs E1-EN.
• a limited number of patterns are preferably chosen by randomly selecting the patterns that will be simulated, all patterns being equiprobable. From experience, such a limitation of the grounds allows a relevant estimate Worst case and best case waveforms, provided the sample size or estimator is sufficient.
• This limitation of the patterns makes it possible to save time in performing the extraction of the current sources and makes the power source extraction tool according to the invention easy to integrate into a software application.
• the patterns may be weighted to take into account those most likely to be observed at the input of the cell 2.1.
• the different switching patterns are applied to the inputs of the cell 2.1. For each switching pattern, simulation data stored in a memory 13 shown in FIG. 4 is obtained.
• the time waveforms corresponding to the noise of the cell can be represented for each switching pattern in a step 14.
• the time waveforms 15 are shown.
• These waveforms 15-17 may have different minimum and maximum values l (t) and dl / dt at different times. It is therefore very difficult to establish which waveform represents the worst case or the best case. The effect of these waveforms on the victims is also difficult to estimate.
• a least squares approximation technique is applied to the real and imaginary parts of the frequency spectra.
• This step 24 makes it possible to approach each frequency spectrum 19-22 by two polynomials: a first approximating the real part of the spectrum and a second the imaginary part of the spectrum. We then obtains a set of polynomials whose coefficients are stored in a memory 26.
• Such a storage of coefficients has the advantage of taking up less space than the storage of the points of the spectra, and of allowing reuse of the waveforms to reproduce different values of periods of the same signal corresponding to line spacings in the domain. frequency. Indeed, it is possible to reuse the spectra for different periods of the waveforms, lines of these spectra 41-43 multiple of 1 / T being selectable, T being the clock period.
• Another advantage of storing polynomials is the reduction of the execution time when calculating sums of spectra for the noise calculation of a block, as well as the good accuracy of the result obtained.
• the blocks 14, 18, 23-25 that make up the block 33 thus represent the steps of extraction of the noise sources of the macro-models. Once the noise sources have been extracted, the spectra obtained are statistically classified so as to identify the minimum and maximum noise sources of each cell corresponding to a worst case and to a better case of noise injection by the cell.
• the spectral densities of the spectra are calculated from their spectral lines. To achieve a ranking of the spectra according to their noise level, it is considered that the higher the spectral density, the greater the noise level. And the lower the spectral density, the lower the level of noise generated by the cell.
• the worst case source of the cell is thus extracted by extracting the waveform having the largest spectral density. And we extract the best case source by extracting the waveform with the lowest spectral density.
• the spectral density can be calculated over the entire frequency spectrum. However, this spectral density can also be calculated for a frequency range Df or for a particular frequency line. Different classifications of waveforms are therefore possible depending on the type of spectral density calculation chosen and the frequency range chosen. In this step, it is also possible to determine an average spectrum, a standard deviation between the spectra, or any other statistical data giving an indication as to the injectable noise by the cells. Alternatively, other methods could be used to compare the different spectra between them and classify them.
• the following blocks 26-30 of FIG. 4 represent a phase 32 of reconstruction of a noise model for a digital circuit.
• these blocks 26-30 represent steps of using the extracted macro-models and current sources to compute worst case, best case or other noise in a particular circuit.
• the noise 26 best or worst cases of each cell are injected in spectral form taking into account cell switching times.
• FIG. 6 thus shows the example of a histogram modeling a discrete distribution of the current calls during a clock period T.
• This graph indicates the number of cells (integers) that can be called on each interval of time [ti, ti + 1 [.
• the instants t1-tP constitute a discrete division of the period T into P time intervals.
• the number of switching cells evolves, the digital cells transmitting the signals to the follower cells step by step.
• This graph thus models a switching activity specific to each clock period, this activity being linked to a modification of the inputs of a digital block.
• the number of cells switched increases to a peak. This increase depends on a fanout parameter which indicates the number of cells connected at the output of each cell whose outputs change state. After the peak, the number of cells switched decreases to zero.
• the switching activity model 27 From the switching activity model 27, it is possible to determine when the cells inject their noise into the substrate. Each cell is then associated with a switching delay with respect to a circuit clock edge, this delay representing the effective call time of the cell and therefore the moment of injection of the noise of the cell. Depending on the case chosen (better or worse), the cell switching activity model can also be adapted. In particular, the number of cells that can switch and therefore inject their noise may vary from one case to another.
• each cell is associated with different noise injection spectra according to the selected operating case. In the worst case of operation, it is considered that most or all cells inject the extracted waveform corresponding to their maximum noise. In the best case of operation, it is considered that most or all cells inject the extracted waveform corresponding to their minimum noise. In the case of average operation, calculations are performed on the extracted waveforms to determine the average waveforms of the noise sources of each cell. For a large number of called cells, one can choose random waveforms from those extracted and available for each cell.
• Each cell is therefore associated with a noise spectrum and a noise injection delay.
• a frequency sum of these spectra and these delays is then carried out in a step 28.
• a resultant noise spectrum 29 is then obtained in the frequency domain.
• This noise spectrum 29 can then be, according to the needs of the analysis of the system, transformed into a temporal signal of noise resulting with the aid of a cell 31 of inverse Fourier transform.
• the block 32 thus makes it possible to obtain a temporal or frequency waveform of injectable noise by a digital block based on an understanding of the noise sources of the cells internal to this block extracted and of a switching model.
• noise sensitivity mask that gives the threshold of sensitivity to the noise of the victim for each frequency is considered.
• a noise sensitivity test is then performed by comparing the calculated block noise and the template.
• the table in Figure 7 shows the decisions of acceptance or non-acceptance of three systems based on a result of their sensitivity test performed in the worst case, the average case and the best case of noise injection.
• the letter R means that the test performed on the system has been successful, ie that the noise level calculated in the system is acceptable taking into account the sensitivity templates of the victims considered or the sensitivity test protocols of each victim.
• the letter NR means that the test performed on the system has failed, ie the noise level calculated in the system is not acceptable given the sensitivity patterns considered or sensitivity test protocols of each victim.
• System 1 passed the noise sensitivity tests in the worst case, the best case, and the average case of noise injection.
• System 1 therefore has good noise immunity and is therefore considered acceptable.
• This decision is made when the test performed with the worst noise is successful. Under these conditions, it is certain that the system operates whatever the level of noise injected in all its modes of use, including marginal modes.
• the noise sensitivity test failed for all noise injection cases.
• System 2 is therefore considered to have poor noise immunity and must therefore be excluded from production. This choice is made when it is highlighted that the sensitivity test failed in the best case of noise injection. Under these conditions, it is certain that the system 2 can never function properly.
• a sensitivity test is carried out first with the worst case, then with the best case and finally with the average case.
• the worst case test has failed, further analysis is needed (best case, average case) to further analyze the system.
• the worst case (respectively the best case) of operation is not necessarily obtained for a choice of the worst, (respectively better) switching parameters, environment and noise source of the different cells. Indeed, these different cases of operation must be observed in a real system operation. In other words, these cases of operation are not cases artificial but cases that can be encountered when the system works in its margins. A choice of all worst (respectively best) noise injection parameters may therefore not correspond to the worst (respectively best) noise injection case of a given system as such a case might never occur.
• Tests and experiments can guide relevant modeling choices for the worst case (respectively best case) that should not be too pessimistic (respectively too optimistic).

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