EP1926139A2 - Substrat SOQ et son procédé de fabrication - Google Patents

Substrat SOQ et son procédé de fabrication Download PDF

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Publication number
EP1926139A2
EP1926139A2 EP07022103A EP07022103A EP1926139A2 EP 1926139 A2 EP1926139 A2 EP 1926139A2 EP 07022103 A EP07022103 A EP 07022103A EP 07022103 A EP07022103 A EP 07022103A EP 1926139 A2 EP1926139 A2 EP 1926139A2
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EP
European Patent Office
Prior art keywords
substrate
soq
film
silicon
single crystal
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Granted
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EP07022103A
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German (de)
English (en)
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EP1926139B1 (fr
EP1926139A3 (fr
Inventor
Shoji c/o Advanced Functional Materials Research Center Akiyama
Yoshihiro c/o Advanced Functional Materials Research Center Kubota
Atsuo c/o Advanced Functional Materials Research Center Ito
Koichi c/o Advanced Functional Materials Research Center Tanaka
Makoto c/o Advanced Functional Materials Research Center Kawai
Yuuji c/o Advanced Functional Materials Research Center Tobisaka
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Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Publication of EP1926139A3 publication Critical patent/EP1926139A3/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Definitions

  • the present invention relates to an SOQ substrate where a silicon film is formed on a quartz substrate and a method for manufacturing the same.
  • An SOQ (Silicon on Quartz) substrate having a silicon thin film formed on a quartz substrate is an SOI substrate expected to be applied to optical devices, for example, a device for manufacturing a TFT liquid crystal monitor.
  • this substrate has received attentions as a substrate intended for applications other than a general SOI substrate.
  • a method of bonding substrates of different materials, a silicon substrate for forming an SOI layer and a quartz substrate as a handling substrate to form a silicon thin film on the quartz substrate is proposed.
  • a SOITEC method SmartCut method
  • This method bonds a silicon substrate prepared by implanting hydrogen ions into a bonding surface side to a handling substrate and performs heat treatment at approximately 500°C or more to thermally delaminate a silicon thin film from a region implanted with hydrogen ions in the highest concentration.
  • This method is based on a mechanism that "air bubbles” called “hydrogen blisters” generated at high density through hydrogen ion implantation are let “grow” under heating, and a silicon thin film is delaminated through the "bubble growth" (for example, Japanese Patent No. 3048201 or A. J.
  • a silicon substrate and a support substrate are bonded together and then, thermally delamination is executed along a hydrogen ion implanted boundary at a temperature of 500°C or more.
  • a thermal strain is caused by a thermal expansion coefficient difference between the two substrates, and delamination along a bonded surface or cracking tends to occur due to the thermal strain. Therefore, it is desirable to complete delamination of a silicon thin film with a lower-temperature process.
  • two substrates that are bonded together should be subjected to heat treatment at higher temperature in order to ensure a satisfactory bonded state throughout the entire bonding surfaces of the silicon substrate and the quartz substrate, and high bonding strength.
  • an SOI layer surface is made rough upon the delamination.
  • a difference in height of about 65 nm in terms of Peak to Valley (PV value) is involved in as small an area as 1 ⁇ m x 1 ⁇ m.
  • Conceivable examples of a method of flattening such a rough surface include mirror polishing and heat treatment at high temperatures (about 1100 to 1200°C) with an atmospheric gas such as argon. Considering quartz grass transition temperatures of 1050 to 1090°C, the latter flattening method based on the high-temperature heat treatment is unsuitable as a method for manufacturing an SOQ substrate.
  • the surface is flattened by the former method (mirror polishing).
  • the SOQ substrate would have a difference in height of 100 nm or more throughout the entire surface, which value is derived from the above surface roughness (about 65 nm in terms of PV value in a 1 ⁇ m x 1 ⁇ m area).
  • stock removal for example, stock removal of 100 nm or more is required.
  • a subtle difference in polishing condition becomes apparent between a central portion and a peripheral portion of the substrate, making it difficult to ensure a uniform SOQ layer thickness throughout the entire surface of the SOQ substrate.
  • the present invention has been accomplished in view of the above problems. It is accordingly an object of the present invention to reduce the degree of surface roughness of an SOQ film immediately after delamination and realize a mirror-finished surface of the SOQ film through hydrogen heat treatment at lower temperatures (1000°C or less).
  • the present invention provides a method for manufacturing an SOQ substrate, including: an ion implantation step of forming a hydrogen ion implanted layer on a main surface of a silicon substrate; a surface treatment step of performing activation on at least one of a main surface of a quartz substrate and a main surface of the silicon substrate; a step of bonding the main surface of the quartz substrate and the main surface of the silicon substrate; a delamination step of mechanically delaminating a silicon thin film from the silicon substrate of the bonded substrate without heating to form a silicon film on the main surface of the quartz substrate; and a step of performing hydrogen heat treatment on the silicon film at a temperature of 1000°C or less.
  • a temperature range for the hydrogen heat treatment is preferably 800°C or more, and a hydrogen concentration in an atmosphere of the hydrogen heat treatment is preferably 0.5% or more.
  • the activation may be performed through at least one of a plasma treatment and an ozone treatment, and the method may include a step of performing heat treatment on the quartz substrate and silicon substrate, which are bonded together, at a temperature of 350°C or less after the bonding step and before the delamination step.
  • a silicon oxide film may be formed on the main surface of the silicon substrate, and the silicon oxide film has a thickness of, for example, 0.2 ⁇ m or more.
  • a process temperature for an SOQ substrate manufacturing process can be lowered, so it is possible to omit delamination in a higher temperature region unlike a conventional method to reduce the degree of surface roughness of an SOQ film immediately after being delaminated, ensure a uniform SOQ film thinness throughout the SOQ substrate, and provide a high-quality SOQ substrate because the whole process is a low-temperature one and thus, transference defects or slip dislocation generation is suppressed.
  • FIGS. 1 are explanatory views of a process example of the method for manufacturing an SOQ substrate according to the present invention.
  • an oxide film is formed beforehand on a silicon substrate surface, but the oxide film may be omitted, and a general silicon substrate having no oxide film may be used.
  • a silicon substrate 10 of FIG. 1(A) is a single crystal Si substrate basically, and a handling substrate is a quartz substrate 20.
  • the single crystal Si substrate 10 is a commercially available Si substrate grown by a Czochralski method (CZ method), for example. Its electric characteristic value such as a conductivity type or a specific resistance, or crystal orientation or crystal diameter is appropriately determined depending on a design value or process of a device using an SOQ substrate manufactured by the method of the present invention or a display area of a manufactured device.
  • the oxide film 11 may be formed in advance on a surface (bonding surface) of the single crystal Si substrate 10 through thermal oxidation, for example, as described above.
  • the single crystal Si substrate 10 and the quartz substrate 20 that are bonded together have substantially the same diameter. It is advantageous to form orientation flat (OF) also in the quartz substrate 20 similar to OF formed in the single crystal Si substrate 10 and bond the substrates together while aligning the OFs with an aim to facilitate a subsequent device manufacturing process.
  • OF orientation flat
  • hydrogen ions are implanted to the surface of the single crystal Si substrate 10 through the oxide film 11(FIG. 1(B)).
  • the ion-implanted surface serves as a "bonded surface” (bonding surface) later.
  • an ion implanted layer 12 is uniformly formed at a predetermined depth from the surface of the single crystal Si substrate 10 (average ion implantation depth L), and a localized "micro bubble layer” is formed in a region corresponding to the average ion implantation depth L in a surface region of the single crystal Si substrate 10 (FIG. 1(C)).
  • the dosage is appropriately selected from a range of, for example, 1x10 16 to 4x10 17 atoms/cm 2 in accordance with specifications of the SOQ substrate or the like.
  • the dosage is generally set to about 7x10 16 atoms/cm 2 .
  • the silicon thin film can be delaminated at low temperature as in the present invention, diffusion of hydrogen atoms in the delamination process is considerably suppressed, so even if hydrogen ions are implanted with a high dosage, the SOI layer surface is not made rough.
  • the present inventors have executed implantation of hydrogen ions with varying dosages and examined an influence of the implantation on surface roughness of the SOI layer. The examination result shows that the surface is not made rough with at least a dosage of 4x10 17 atoms/cm 2 or less as long as a silicon thin film is delaminated trough low-temperature heat treatment at only about 350°C.
  • a depth of the ion implanted layer 12 from the surface of the single crystal Si substrate 10 (boundary with the oxide film 11) (average ion implantation depth L) is controlled in accordance with an acceleration voltage of implanted ions and is determined depending on a thickness of an SOQ layer to be delaminated.
  • the average ion implantation depth L is set to 0.5 ⁇ m or less, and the acceleration voltage is set to 50 to 100 keV.
  • an insul,ator film such as an oxide film may be formed beforehand on an ion implantation surface of the single crystal Si substrate 10 to implant ions through the insulator film.
  • the bonded surface of both of the single crystal Si substrate 10 having the ion implanted layer 12 formed thereon as above and the quartz substrate 20 is subjected to a plasma treatment or an ozone treatment for cleaning and activating the surface (FIG. 1(D)).
  • This surface treatment is carried out for the purpose of removing an organic material from the surface as the bonded surface or increasing OH groups on the surface to activate the surface, and the treatment is not necessarily performed on both of the bonded surfaces of the single crystal Si substrate 10 and the quartz substrate 20 but may be performed on one of the bonded surfaces.
  • a single crystal Si substrate and/or a quartz substrate with the surface being cleaned by RCA cleaning is placed on a sample stage in a vacuum chamber, and a plasma gas is introduced to the vacuum chamber up to a predetermined vacuum degree.
  • the usable plasma gas include an oxygen gas, a hydrogen gas, an argon gas, and a mixed gas thereof, or a mixed gas of a hydrogen gas and a helium gas.
  • radio-frequency (RF) plasma having a power of about 100 W is generated and then applied to the surface of the single crystal Si substrate and/or the quartz substrate as a plasma treatment target for about 5 to 10 seconds, and the treatment is completed.
  • a single crystal Si substrate and/or a quartz substrate with the surface being cleaned by RCA cleaning is placed on a sample stage in a chamber kept in an atmosphere containing an oxygen, and plasma gas such as a nitrogen gas or an argon gas is introduced into the chamber, after which an RF plasma having a predetermined power is generated, and the oxygen in the atmosphere is turned into an ozone by the plasma to apply treatment to the surface of the target single crystal Si substrate and/or quartz substrate for a predetermined period.
  • plasma gas such as a nitrogen gas or an argon gas
  • the surfaces of the surface-treated single crystal Si substrate 10 and the quartz substrate 20 as bonding surfaces are closely bonded (FIG. 1(E)).
  • the surface (bonding surface) of at least one of the single crystal Si substrate 10 and the quartz substrate 20 undergoes surface treatment through the plasma treatment or ozone treatment and thus is activated, so a bonding strength, which is high enough to withstand mechanical delamination or polishing in a subsequent step even in a closely-attached (bonded) state at room temperatures, can be obtained.
  • This heat treatment step mainly aims at enhancing strength of bonding between the quartz substrate 20 and the oxide film 11 formed on the single crystal silicon substrate 10.
  • the main reason for setting the heat treatment temperature to 350°C or less is to prevent occurrences of "hydrogen blisters" as described above.
  • this temperature is set in consideration of a difference in thermal expansion coefficient between single crystal silicon and quartz, a damage resulting from the thermal expansion coefficient difference, and the damage and thicknesses of the single crystal silicon substrate 10 and the quartz substrate 20.
  • the single crystal Si substrate 10 and the quartz substrate 20 have approximately the same thickness, a large difference arises between a thermal expansion coefficient (2.33x10 -6 ) of single crystal silicon and a thermal expansion coefficient (0.6x10 -6 ) of quartz and thus, upon heat treatment at a temperature of more than 350°C, cracking or delamination along the bonding surface might occur due to a thermal strain resulting from a rigidity difference between the two substrates; in an extreme case, the signal crystal silicon substrate or quartz substrate would be broken. From this point of view, the upper limit of heat treatment temperature is set to 350°C.
  • this heat treatment can be expected to cause a secondary effect of generating a thermal stress caused by the thermal expansion coefficient difference between the single crystal Si substrate 10 and the quartz substrate 20 to weaken chemical bonds of silicon atoms in the ion implanted layer 12.
  • Si-H bonds or Si atoms having dangling bonds are generated at high density in the ion implanted layer 12. If the bonded substrate is subjected to heat treatment, a large stress is generated between the two substrates throughout the entire surface of the bonded substrate due to the fact that silicon crystal has a larger thermal expansion coefficient than that of quartz.
  • an external shock is applied onto the bonded substrate with any method to mechanically delaminate a silicon film 13 from a single crystal silicon bulk 14 to obtain an SOQ film that is formed on the quartz substrate 20 through the oxide film 11 (FIG. 1(F)).
  • any method to mechanically delaminate a silicon film 13 from a single crystal silicon bulk 14 to obtain an SOQ film that is formed on the quartz substrate 20 through the oxide film 11 (FIG. 1(F)).
  • various methods are conceivable for applying an external shock to delaminate a silicon thin film. The delamination is carried out without heating here.
  • hydrogen heat treatment is performed at 1000°C or less below a quartz glass transition point (FIG. 1(G)).
  • the hydrogen heat treatment also produces a recovery effect from a damage caused by hydrogen ion implantation.
  • the temperature is 800 to 1000°C, and a hydrogen concentration in the atmosphere is 0.5% or more.
  • This example shows a thickness of an oxide film formed on a main surface of the silicon substrate 10.
  • FIGS. 2 are a sectional view schematically illustrating a bonding surface of a single crystal Si substrate used in the method for manufacturing an SOQ substrate according to the present invention (FIG. 2(A)), and a schematic sectional view of an SOQ substrate including a delaminated silicon film (FIG. 2 (B)) .
  • the silicon oxide film 11 having a film thickness tox is formed on one main surface (bonding surface) of the single crystal Si substrate 10, and the hydrogen ion implanted layer 12 is formed near the substrate surface with an average ion implantation depth L.
  • the film thickness tox of the oxide film 11 is set to 0.2 ⁇ m or more to suppress transference defects or slip dislocation generation in a step of delaminating a silicon thin film after bonding the substrate to the quartz substrate.
  • the silicon thin film is delaminated at the average ion implantation depth L as indicated by reference numeral 12 in FIG. 2 (A) . Then, the silicon thin film is transferred onto the quartz substrate 20 through the oxide film 11 to form the SOQ film 13 (FIG. 2(B)).
  • the bonding surface of the quartz substrate 20 is not an ideal, completely flat surface but involves irregularities because of microscopic roughness, adherence of microparticles to the bonding surface, or the like. If the quartz substrate 20 having such a bonding surface is bonded to the single crystal Si substrate 10, the irregularities of the quartz substrate 20 surface are reflected to the bonding surfaces, and a "clearance" is locally formed between the bonding surfaces. As a result, a region concentratedly applied with a damage is locally formed.
  • the method for manufacturing an SOQ substrate according to the present invention employs a low-temperature process for the purpose of reducing a thermal strain (thermal stress) resulting from a thermal expansion coefficient difference between the silicon substrate and the quartz substrate, and thus does not involve higher-temperature heat treatment for increasing a strength of bonding between the two substrates and sets a large film thickness tox of the oxide film 11 to 0.2 ⁇ m or more, to thereby impart enough mechanical strength to a thin film delaminated from the single crystal silicon substrate side, and absorb and alleviate the damage with the relatively thick oxide film to suppress the generation of transference defects during the delamination step.
  • a thermal strain thermal stress
  • the main reason for setting the film thickness tox of the oxide film 11 to 0.2 ⁇ m or more in the present invention is to increase the total thickness of the thin films delaminated from the single crystal Si substrate side (that is, the oxide film and the silicon film) to enhance the mechanical strength and to absorb and alleviate a damage with the oxide film to suppress the generation of "transference defects" in the delamination step.
  • the oxide film thickness of 0.2 ⁇ m or more, which is selected in the present invention is an elliptically determined effective for preventing transference defects or slip dislocation from reaching up to the silicon thin film from the bonding boundary.
  • the generation of "transference defects" in the delamination step can be more suppressed.
  • the thickness of the oxide film 11 is as small as about 0.1 ⁇ m, and a "clearance" is locally formed due to particles between the bonding surfaces of the oxide film 11 and the quartz substrate 20, a damage tends to be localized in the region, so transference defects or slip dislocation is likely to be generated from that region. If the oxide film 11 has a thickness of 0.2 ⁇ m or more, the damage is alleviated in the oxide film 11 and a stress applied to the silicon film (SOQ film) formed thereon is reduced.
  • SOQ film silicon film
  • the thickness of the oxide film as an SOI layer is generally about 0.1 ⁇ m.
  • a handling substrate is a quartz substrate based on Si-O bonds, so a problem does not occur even if an oxide film including Si-O bonds and formed on one main surface of the single crystal silicon substrate has a large thickness of 0.2 ⁇ m or more.
  • the oxide film 11 can realize high quality by thermally oxidizing the surface of the single crystal silicon substrate.
  • the experiments made by the present inventors reveal that if the film thickness (tox) of the oxide film 11 formed on the single crystal Si substrate is twice or more as large as the thickness (that is, L and tSi) of the SOQ film (2L ⁇ tox), generation of defects in the delamination step can be effectively suppressed.
  • a damage locally applied between the bonding surfaces could be alleviated by the oxide film having the thickness twice or more as large as the thickness of the SOQ film (2L ⁇ tox), and a stress applied to the silicon film (SOQ film) formed thereon can be reduced.
  • a substrate that can satisfy 2L ⁇ tox as a relation between the film thickness (tox) of the oxide film and the average ion implantation depth L of the hydrogen ion implanted layer may be used.
  • the present invention it is possible to lower a process temperature for an SOQ substrate manufacturing process, reduce the degree of surface roughness of an SOQ film, and provide a high-quality SOQ substrate.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
EP07022103.1A 2006-11-22 2007-11-14 Substrat SOQ et son procédé de fabrication Active EP1926139B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006315363A JP5249511B2 (ja) 2006-11-22 2006-11-22 Ｓｏｑ基板およびｓｏｑ基板の製造方法

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EP1926139A2 true EP1926139A2 (fr) 2008-05-28
EP1926139A3 EP1926139A3 (fr) 2011-05-04
EP1926139B1 EP1926139B1 (fr) 2013-10-23

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US (1) US7790571B2 (fr)
EP (1) EP1926139B1 (fr)
JP (1) JP5249511B2 (fr)
CN (1) CN101188190B (fr)

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EP1998368A3 (fr) * 2007-05-31 2012-05-23 Shin-Etsu Chemical Company, Ltd. Procédé de fabrication d'une tranche SOI
EP3168862A4 (fr) * 2014-07-10 2018-06-20 Sicoxs Corporation Substrat semi-conducteur et procédé de fabrication de substrat semi-conducteur

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JP4967842B2 (ja) * 2007-06-18 2012-07-04 セイコーエプソン株式会社 シリコン基材の接合方法、液滴吐出ヘッド、液滴吐出装置および電子デバイス
JP5248838B2 (ja) * 2007-10-25 2013-07-31 信越化学工業株式会社 半導体基板の製造方法
US7820527B2 (en) * 2008-02-20 2010-10-26 Varian Semiconductor Equipment Associates, Inc. Cleave initiation using varying ion implant dose
JP5868003B2 (ja) * 2011-01-14 2016-02-24 三菱電機株式会社 平面導波路型レーザ装置およびその製造方法
CN102259829A (zh) * 2011-07-04 2011-11-30 上海先进半导体制造股份有限公司 隔离腔体及其制造方法
US12007695B2 (en) * 2020-01-15 2024-06-11 Board Of Regents, The University Of Texas System Rapid large-scale fabrication of metasurfaces with complex unit cells
JP7466961B1 (ja) 2023-05-29 2024-04-15 大 西田 連結具及び施工方法

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1998368A3 (fr) * 2007-05-31 2012-05-23 Shin-Etsu Chemical Company, Ltd. Procédé de fabrication d'une tranche SOI
US8268700B2 (en) 2007-05-31 2012-09-18 Shin-Etsu Chemical Co., Ltd. Method for manufacturing SOI wafer
EP3168862A4 (fr) * 2014-07-10 2018-06-20 Sicoxs Corporation Substrat semi-conducteur et procédé de fabrication de substrat semi-conducteur

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CN101188190A (zh) 2008-05-28
US7790571B2 (en) 2010-09-07
JP2008130884A (ja) 2008-06-05
JP5249511B2 (ja) 2013-07-31
EP1926139B1 (fr) 2013-10-23
US20080119028A1 (en) 2008-05-22
EP1926139A3 (fr) 2011-05-04

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