Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
  • H01L29/51—Insulating materials associated therewith
  • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate

Definitions

• the present invention relates to the field of integrated circuits, and more particularly to that of transistors, and aims to present a microelectronic device having one or more transistors with improved electrical performance, and for which the limitations related to the effect tunnel are reduced.
• This device uses means, in particular piezoelectric means capable of inducing a mechanical stress, of a kind and / or scalable amplitude (s), on the channel of the latter.
• piezoelectric means may be formed over the grids and at least a portion of the respective active regions of the transistors, or between the grids and at least a portion of the respective channel structures of the transistors.
• a constrained channel is generally formed of a first semiconductor layer on which a mechanical stress, voltage or compression is applied via a second layer underlying, or located on, said semiconductor layer .
• the second layer may be formed for example based on a crystalline semiconductor material with a mesh parameter different from said first semiconductor material, or a dielectric material.
• CMOS complementary metal-oxide-semiconductor
• NMOS transistor channels NMOS transistor channels
• epitaxially-based SiGe-based layers may be employed to allow a bi-axial compression stress to be applied to the PMOS transistor channels.
• US 5,883,419 discloses a microelectronic device comprising a transistor, having a piezoelectric material based layer, located between the gate and the channel of the transistor.
• the transistor channel is formed based on MoC, a metal material and piezoresistive, and is likely to be constrained, when applying a voltage on the gate of piezoelectric material.
• the object of the present invention is to present a microelectronic device comprising means for applying a mechanical stress of the type and / or scalable amplitude (s) on the channels of the transistors. These means give the transistors improvements, especially in terms of electrical performance.
• the present invention relates in particular to a microelectronic device comprising:
• At least one first transistor having at least one source region, at least one drain region, at least one structure forming at least one channel, connecting the source region and the drain region and at least one gate
• the device further comprising: means in particular of piezoelectric type, resting on at least a portion of the gate and above at least a portion of at least one of said source region and / or drain, capable of inducing a mechanical stress or several types of different mechanical stresses on the channel of the transistor.
• types different, it refers to forces that the piezoelectric means are likely to induce or exert on the channel, meaning and / or different directions.
• the piezoelectric type means are capable, depending in particular on their state of polarization, of inducing at least a first type of stress, for example a stress in tension, and at least a second type of mechanical stress, for example a constraint. in compression, on the transistor channel.
• the piezoelectric type means are capable, depending in particular on their state of polarization, of inducing at least a first stress of a first intensity, and at least a second mechanical stress of a second intensity different from the first intensity.
• Said piezoelectric means may comprise at least one thin layer based on piezoelectric material situated above at least one portion of the source of said first transistor and resting on at least a portion of the gate of the first transistor.
• the layer based on piezoelectric material, and said portion of the source may be separated by an intermediate layer, for example based on an insulating material.
• the intermediate layer may be designed to attenuate the mechanical stress exerted by the piezoelectric layer.
• the intermediate layer may also serve as an etch stop layer.
• the intermediate layer can also be used to electrically isolate the source and the piezoelectric layer.
• the layer based on piezoelectric material can rest on the source region and be in contact with the latter.
• said piezoelectric layer may cover at least partially at least one side of the gate.
• Said piezoelectric layer may possibly cover the sides of the grid and thus allow to act as spacers.
• the piezoelectric layer can be asymmetrical with respect to a normal to a main plane of the substrate passing through the gate. This can help focus a mechanical stress induced by the piezoelectric layer on a given area of the channel of the first transistor.
• the piezoelectric layer may possibly be situated, mainly or solely, on the source region and on at least a portion of the gate of the first transistor. This may make it possible to concentrate a mechanical stress on the input, or on an area of the channel of the first transistor, located near the source region.
• the magnitude and / or the type of mechanical stress induced by the piezoelectric means on the channel of the first transistor may be dependent or controlled by the bias state of the first transistor.
• the microelectronic device may further comprise:
• At least one first contact or contact pad in contact with the source region and able to be connected to polarization means of the source region
• At least a second contact or contact pad in contact with the gate and adapted to be connected to means for biasing the gate, the first contact and the second contact being in contact with the piezoelectric layer.
• the magnitude and / or the type of mechanical stress induced by the piezoelectric means on the channel of the first transistor may be dependent or controlled by the state of polarization of the gate and the source of the first transistor.
• the latter may furthermore comprise:
• At least a third contact or third contact pad disjoint from the piezoelectric layer, and adapted to be connected to means for biasing the drain region.
• the magnitude and / or the type of mechanical stress induced by the piezoelectric means on the channel of the first transistor may be independent of the bias of the drain of the first transistor.
• microelectronic device may furthermore comprise:
• means for biasing the drain region means for biasing the source region and means for biasing the gate being electrically connected to the piezoelectric layer via the first contact or contact pad and the second contact respectively of contact.
• the piezoelectric means used according to the invention are capable of applying several different types of constraints, they can make it possible to improve both the operation of PMOS transistors and NMOS transistors, this for each of the respective states “passing” or “blocked” that these transistors are likely to adopt.
• this device in which the first transistor is a PMOS transistor, this device can furthermore comprise:
• At least one second NMOS transistor respectively provided with at least one source region and at least one drain region formed in second semiconductor regions of the substrate with at least one channel structure connecting the region source and the drain region and at least one gate resting on the channel, piezoelectric type means resting on at least a portion of the gate and above at least a portion of at least one said second semiconductor regions, capable of inducing a mechanical stress on the channel of the second transistor.
• microelectronic device comprising:
• the device further comprising: piezoelectric type means situated under the gate, between the gate and the substrate, the piezoelectric type means being able to induce a mechanical stress or several types of different mechanical stresses on the transistor channel.
• the piezoelectric means may comprise at least one layer based on piezoelectric material, the layer based on piezoelectric material being located between the gate and at least one gate dielectric layer resting on the channel structure.
• the piezoelectric means may comprise at least one layer based on piezoelectric material, the layer based on piezoelectric material being situated between at least one gate dielectric layer and the channel structure.
• the piezoelectric means may comprise at least one layer based on piezoelectric material in contact with the gate and the channel structure.
• the piezoelectric layer may be able to act as gate dielectric.
• the piezoelectric means may comprise at least a layer of piezoelectric and semiconductor material belonging to the channel structure.
• the semiconductor piezoelectric material may for example be AsGa.
• the invention also relates to a method for producing a microelectronic device comprising steps of: a) forming on a substrate of at least a first transistor provided respectively with at least one source region, at least one region of drain, as well as at least one channel structure, connecting the source region and the drain region and at least one gate on the channel structure, b) forming at least one piezoelectric layer above at least one a portion of said source and drain region and resting on at least a portion of the grid.
• the latter may further comprise, after step b), a step c) of forming at least one first conductive pad in contact with the source region and the piezoelectric layer, and which may be for example intended to be connected to means for biasing the source, and at least one second conductive pad in contact with the gate and with the piezoelectric layer, and which may be for example intended to be connected to polarization means of the gate.
• the method for producing the microelectronic device may further comprise, at the step c): the formation of at least one third conductive pad in contact with the drain region and advantageously disjoint or not in contact with the piezoelectric layer, and which may be for example intended to be connected to means of polarization of the transistor source.
• the invention also relates to a method for producing a microelectronic device comprising the steps of: a) forming on a substrate at least a first transistor having at least one source region and at least one drain region as well as at least one semiconductor structure, connecting the source region and the drain region, b) forming at least one piezoelectric layer above and at least opposite the semiconductor structure, c ) forming at least one gate above and at least opposite the piezoelectric layer and the semiconductor structure.
• the piezoelectric layer may be based on at least one semiconductor material, for example AsGa and be formed on the semiconductor structure, the semiconductor structure and the piezoelectric layer. being intended to form a channel for said transistor.
• the grid may be formed on the piezoelectric layer.
• the piezoelectric layer may be formed on the semiconductor structure, so as to be in contact with the semiconductor structure.
• the method may further comprise: forming at least one gate dielectric layer prior to step c).
• FIGS. 1A and 1B illustrate examples of microelectronic devices according to the invention, equipped with transistors and piezoelectric means, capable of modulating the state of constraint of the channel of these transistors
• FIGS. 2A, 2B, 2C, 2D illustrate different modes of operation of a device according to the invention
• FIGS. 3A to 3D illustrate, in a sectional view, the steps of an exemplary method for producing a microelectronic device according to the invention
• FIGS. 4A to 4B illustrate, in a sectional view, the steps of another example of process for producing a microelectronic device according to the invention
• FIGS. 5, 6, 7, 8 illustrate variants of microelectronic devices equipped with at least one transistor and piezoelectric means, able to modulate the state of stress of the channel of this transistor
• This device firstly comprises a substrate 100, which may be of the semiconductor-on-insulator type, for example of the SOI (SOI) type, provided with a first layer of silicon-on-insulator.
• a substrate 100 which may be of the semiconductor-on-insulator type, for example of the SOI (SOI) type, provided with a first layer of silicon-on-insulator.
• support for example based on sapphire or semiconductor, covered by an insulating layer, for example based on SiO 2, itself covered by a semiconductor layer 102, able to act as an active layer.
• the semiconductor layer 102 may for example be based on at least a semiconductor material among the following materials: Si, Ge, SiGe, GaAs.
• a first active zone of a transistor T 1 for example in MOS technology (MOS for Metal Oxide semiconductor or "metal oxide semiconductor"), is formed.
• This first active zone comprises a first doped region, able to act as a source region 104 of the transistor Ti, a second doped region, able to act as a drain region 108 of the transistor Ti, and at least one structure channel 112, connecting the source region 104 and the drain region 108.
• the transistor Ti also comprises at least one gate 116 resting on a gate dielectric layer 113 116.
• the transistor Ti may for example be a write transistor a cell of a dynamic memory DRAM (DRAM for dynamic random access memory).
• the microelectronic device also comprises means, in particular of the piezoelectric type, for exerting or inducing a mechanical stress on the channel structure 112, in particular a constraint of magnitude as well as of variable type.
• magnitude reference is made to an intensity of forces that these piezoelectric means are likely to induce or exert on the channel.
• Type means the nature of the forces, for example shear forces or compressive forces, or the direction (s) and direction (s) of forces, which such piezoelectric means are likely to induce or cause. exercise on the canal.
• these piezoelectric means are suitable, in particular when they are in a first state of polarization to exert a first type of forces, or to induce a first type of constraint, for example a voltage constraint, on the channel structure 112 of the transistor Ti, and are also suitable, in particular when they are in a second state of polarization different from the first state, to exert a second type of forces, or to inducing a second type of stress, for example a compressive stress, on the channel structure 112 of the transistor T 1 .
• the piezoelectric means may comprise a layer 120 based on piezoelectric material formed above, for example on the gate 116 and above, for example on the first active zone.
• the piezoelectric layer 120 may be arranged to at least partially cover the source region 104, as well as at least partially the upper face of the gate 116 of the transistor Ti.
• the piezoelectric layer 120 may optionally be arranged, as in FIG. 1A, so as to cover the drain region 108 of the transistor Ti.
• the piezoelectric layer 120 may be optionally continuous on the transistor Ti and arranged so as to cover the sidewalls or side faces of the gate 116.
• the layer 120 in addition to making it possible to induce a stress on the channel 112, the layer 120 enables to form spacers ("spacers" according to the English terminology) for the grid 116.
• the piezoelectric layer 120 may be formed on the first active zone, in particular on the source 104 and drain 108 regions, and in direct contact with these regions 104, 108.
• the piezoelectric layer 120 can be formed above the first active area, in particular above the source 104 and drain 108 regions, and be separated from the source and drain regions by a thin intermediate layer, for example based on a insulating material. This intermediate layer may be a layer for attenuating the mechanical stress exerted by the piezoelectric layer 120.
• the intermediate layer may also serve as an etch stop layer. According to one possibility, the intermediate layer can also serve to electrically isolate the source and the piezoelectric layer 120.
• the insulating intermediate layer may for example be based on TeOS thermal oxide, and of thickness for example between 1 nanometer and 15 nanometers.
• the piezoelectric layer 120 may have a thickness for example between 1 nanometer and 1 micrometer or for example between 10 nanometers and 300 nanometers, or a thickness to apply a stress of the order of 1 GPa or between 0.5 GPa and 5 GPa.
• the piezoelectric layer 120 may be based on a piezoelectric material, such as, for example, PbZrTiO 3 or PZT (PZT for lead-zirconate titanate) or BaSrTiO 3 or BST (barium-strontium-titanate oxide), or ZnO, or LiNbO 3 .
• PbZrTiO 3 or PZT PZT for lead-zirconate titanate
• BaSrTiO 3 or BST barium-strontium-titanate oxide
• ZnO or LiNbO 3
• the magnitude as well as the nature of the forces, compression or shear, or stress, in tension or compression, that the layer 120 is likely to exert or induce on the channel structure 112, can be modulated depending on how the layer 120 of piezoelectric material is polarized.
• the device may also comprise conductive pads 142, 144, 146, in contact respectively with the source region 104, the gate 116, and the drain region 108 of the transistor T 1 , and inserted into the piezoelectric layer 120.
• These pads conductors 142, 144, 146 are used to connect or electrically connect source biasing means, gate biasing means, drain biasing means (not shown), respectively, to the source region, the grid, to the drain region.
• the conductive pads 142, 144, 146 also make it possible to connect all of said biasing means respectively to the piezoelectric layer 120.
• the piezoelectric layer 120 is likely to deform and applying or inducing at least two different types of constraints on the channel 112.
• the intensity of the forces or the magnitude of the stress, as well as the direction and / or directions of the forces or the nature of the stress, that the layer 120 is capable of applying or inducing on the channel 112, can be slaved or modulated by the respective potentials Vs, Vg, Vd, applied by the biasing means on the electrodes of the transistor T 1 .
• the device is capable of adopting at least a first polarization state or a first set of values for the potentials Vs, Vg, Vd, for which the piezoelectric layer 120 extends and applies or induces a first type of constraint on the channel 112 of the transistor Ti, for example a voltage stress.
• the device is also capable of adopting at least a second polarization state or a second set of values for the potentials Vs, Vg, Vd, for which the piezoelectric layer 120 retracts or compresses and applies or induces a second type of constraint on the channel 112 of the transistor T 1, for example a compressive stress.
• the drain contact conductive pad 146 may be electrically isolated from the piezoelectric layer 120 by means of a spacer (not shown) based on insulating material, for example Si 3 N 4 .
• the stress induced by the piezoelectric layer 120 on the channel structure 112 is independent of the potential Vd applied to the drain 108, and is modulated only as a function of the value of potentials Vs, Vg, applied respectively, by polarization means (not shown) of the source 104, and the gate 116 of the transistor 110.
• piezoelectric type means making it possible to apply a modulable mechanical stress on the channel structure 112 of the transistor Ti, but arranged in a different manner.
• These means comprise in particular a piezoelectric layer denoted 220, of thickness and composition which may be similar or equal to those of the layer 120, but arranged with respect to the transistor Ti, in a different manner with respect to the piezoelectric layer 120.
• the piezoelectric layer 220 is asymmetrical with respect to an axis ⁇ , orthogonal to a main plane of the substrate (the principal plane of the substrate being defined as a plane passing through the substrate 100 and parallel to a plane [0; i; k] of the reference orthogonal [0; i; j; Jc] in FIG. 1B) passing through the gate 116 of the transistor Ti.
• the piezoelectric layer 220 may be asymmetrical with respect to a plane perpendicular to a source-drain axis (defined in a direction parallel to a vector i of the orthogonal reference line [O; i; j; k] in FIG. 1B), and passing through the gate 116.
• the piezoelectric layer 220 is formed on at least a portion of the source region 104 as well as on a sidewall and a portion of the upper or upper face of the gate 116 of the transistor Ti, only. Another portion of the upper face of the gate 116, a sidewall of the gate 116 located on the side of the drain region 108, as well as the drain region 108, they are not covered by the piezoelectric material layer 220.
• Conductive pads 242, 244, 246 are also provided for connecting or electrically connecting source biasing means, gate biasing means, drain biasing means (not shown), respectively to the source region. 104, to the gate 116, and to the drain region 108 of the transistor Ti.
• the conductive pad 246, in contact with the drain region 108 is not in contact with this piezoelectric layer 220.
• the stress induced by the piezoelectric layer 220 on the channel structure 112 is independent of the potential Vd applied to the drain 108, and is modulated only as a function of the value of potentials Vs, Vg, respectively applied, by polarization means (not shown) of the source 104, and the gate 116 of the transistor 110.
• the device is capable of adopting at least a first polarization state or a first set of values for the potentials Vs, Vg, for which the piezoelectric layer 120 extends and applies or induces a first type of constraint at the input of the channel 112 of the transistor T 1, for example a voltage stress.
• the device is also capable of adopting at least a second polarization state or a second set of values for the potentials Vs, Vg, for which the piezoelectric layer 120 retracts or compresses and applies or induces a second type of stress to the the input of the channel 112 of the transistor T 1, for example a compressive stress.
• the piezoelectric layer 220 may have, for example, a piezoelectric constant of the order of 600 * 10-12 m ⁇ V "1. Considering a potential V g applied to the gate of the order of IV or IV, a relative deformation of the layer 220 of the order of 6 * 10 ⁇ 3 or a stress of about 1.5 GPa can be obtained.
• the microelectronic device according to the invention is not limited to a single transistor Ti and may comprise a plurality of transistors, for example made in CMOS technology, and respectively covered with piezoelectric type means as previously described, capable of applying a constraint, of a kind and / or scalable amplitude (s), on the respective channels of these transistors.
• FIGS. 2A, 2B, 2C, 2D illustrate the operation of a microelectronic device in CMOS technology, implemented according to the invention, provided with transistors T 2 and T 3 , realized respectively in NMOS and PMOS technology, and comprising respectively a source region 204, 304, a drain region (not shown), a channel structure 212, 312, and a gate 216, 316.
• the channel structure 212, 312 may be based on at least one semiconductor material, for example based on at least one semiconductor material from among the following materials: Si, Ge, SiGe, GaAs.
• the transistors T 2 and T 3 are also respectively surmounted by piezoelectric type means as described previously, able to exert a mechanical stress on the channel 212, 312, of nature and / or scalable scale.
• These means respectively comprise a piezoelectric layer 220 formed on their source region and on a portion of their gate, able to deform when it is polarized and to adopt several positions, depending on the value of bias potentials applied thereto. .
• the piezoelectric means implemented according to the invention make it possible to improve the performances of both the NMOS and PMOS transistors.
• a potential VgI and a potential VsI are respectively applied to the gate 216 and the source 204 of the transistor T 2 in NMOS technology, such that VgI-VsI ⁇ Vt, with Vt a voltage value for which the piezoelectric layer passes from a first state of stress, for example from compressive stress to a second state of stress, for example voltage stress, Vt may be for example the threshold voltage of the transistor T 2 .
• the potentials VgI and VsI are also applied to the piezoelectric layer 220 associated with the transistor T 2 .
• the latter tends to compress and then induces a constraint 240 in uniaxial compression (whose direction and direction are similar to those of the vector i of an orthogonal coordinate system [0; i; j; k] defined in FIG.
• the stress 240 applied to the channel 212 makes it possible to to increase the effective mass of the electrons in the channel 212 and to limit the leakage current.
• a potential VgI and a potential VsI are respectively applied to the gate 216 and to the source 204 of the transistor T 2 , such that VgI-VsI> Vt.
• the piezoelectric layer 220 associated with the transistor T 2 tends to extend and induces a uniaxial voltage stress 250 at the input of the channel 212 (whose direction is similar to that of the vector i of an orthogonal reference [0; i; j; k], and whose direction is opposite to that vector i of an orthogonal coordinate system [O; i; j; k] defined in FIG. 2B), a constraint which is favorable to the transport of electrons.
• the stress 250 applied to the channel 212 makes it possible to improve or increase the saturation current in the channel 212.
• a potential Vg2 and a potential Vs2 are applied respectively to the gate 316 and to the source 304 of the PMOS transistor T 3 , such that Vg2-Vs2 ⁇ Vt.
• the piezoelectric layer associated with the transistor T 3 tends to compress and induce a stress 260 (whose direction and direction are similar to those of the vector i of an orthogonal reference [O; i; j; k] defined on Figure 2C) in uniaxial compression at the inlet of the channel 312, constraint which is favorable to the transport of the holes.
• the constraint 260 makes it possible to reduce the effective mass of the holes and increase the saturation current in the channel 312.
• a potential Vg2 and a potential Vs2 are applied respectively to the gate 316 and to the source 304 of the transistor T 3 in PMOS technology.
• the piezoelectric layer 220 associated with the transistor T 3 induces a uniaxial compressive stress at the input of the channel 312 (whose direction is similar to that of the vector i of an orthogonal reference [0; i; j; k]), and whose direction is opposite to that of the vector i of an orthogonal coordinate system [0; i; j; Jc] defined in FIG. 2B), a constraint which is unfavorable for the transport of the holes.
• the stress 270 makes it possible to increase the effective mass of the holes and to reduce the leakage current.
• the transistors T 2 and T 3 can be integrated in the same substrate 100. According to one variant, the transistors T 2 and T 3 can optionally be controlled by the same potential.
• One or the other of the microelectronic devices previously described in connection with FIGS. 1A, 1B, 2A-2D may be implemented in a dynamic random access memory (DRAM) system.
• DRAM dynamic random access memory
• a dynamic access memory device comprising a plurality of cells having at least one write transistor dynamic memory, associated according to the invention with piezoelectric means as described above, able to exert a mechanical stress of a kind and / or scalable amplitude on its channel, has improved performance in terms of speed and consumption.
• the piezoelectric means associated with a write transistor of such a device are capable of applying a first type of stress on the channel of the transistor, making it possible to increase the saturation current of the transistor, and in particular to improve the speed writing by the transistor of an information, for example in a storage capacitor to which this transistor is associated.
• These piezoelectric means are capable of applying a second type of stress on the channel of the transistor, making it possible to reduce the leakage current of the transistor, and in particular to prevent unwanted or inappropriate writing of information or to better protect the information contained in the storage capacitor.
• the device according to the invention is no more limited to a semiconductor-on-insulator substrate, and can be implemented for example on a solid semiconductor substrate.
• the microelectronic device according to the invention is also not limited to one or more "classical” single-gate transistors such as that Ti, described above, and may comprise transistors, for example one or more double-gate transistors and / or or several transistors of type called "Finfet” as in document [1]: "Sub 50 FinFET nm: PMOS ", Huang et al., 1999 IEEE ,, and / or said one or more so-called” trigate "or triple-gate transistors as in document [2]:” Tri-Gate Fully Depleted CMOS Transistors: Manufacturing , Design and Layout, B.
• GAA transistors GAA transistors
• VLSI Technology Digest Papers respectively comprising means, in particular piezoelectric, capable of exerting a mechanical stress on their channel type and / or scalable amplitude.
• FIGS. 3A to 3F An example of a method according to the invention for producing a microelectronic device, of the type described above in connection with FIG. 1A, will now be given in conjunction with FIGS. 3A to 3F.
• the starting material of the process may be a substrate formed of a layer of solid semiconductor material, or a semiconductor-on-insulator type substrate 100, comprising a first support layer, which may be semiconducting and for example silicon-based. on which an insulating layer rests, for example a layer of silicon oxide ("burried oxide" according to the terminology Anglo-Saxon) based on SiO 2, itself covered with a semiconductor layer 102, capable of serving as an active layer, and for example based on Si or Ge or SiGe or on a III-V compound such as AsGa, or a compound II-VI such as Hg-Cd or Hg-Te.
• At least one transistor for example in MOS technology, having at least one source region 104, of at least one drain region 108, is formed.
• the channel 112 may for example be formed of a P-doped zone or island in the semiconductor layer 102 for an NMOS transistor, or of an N-doped island in the semiconductor layer 102 for a transistor of the type PMOS.
• the source 104 and drain 108 regions may, for example, be respectively formed of N-doped zones of the semiconductor layer 102, on either side of a P-doped island, for an NMOS transistor or formed of doped zones. P on both sides of an N-doped island for an NMOS transistor.
• At least one gate 112 can be formed on said active zone. This gate 112 may be formed, for example, by deposition of a gate dielectric material 113 or by oxidation of a semiconductor material, so as to form a gate dielectric material 113.
• the gate dielectric material 113 may be example based on SiO2, or HfO2, or HfSi x Oy.
• metal such as for example TiN, or W, or WSi x , or TaN, or semiconductor such as for example polysilicon
• a deposit of a layer 120 based on piezoelectric material 119 such as, for example, PbZrTiO 3 or PZT (PZT for lead zirconate-titanate) or BaSrTiO 3 or BST (barium strontium titanate), or ZnO or LiNbO 3 , is carried out on at least a portion of the active zone and the gate 116.
• the deposition of a layer 120 to Piezoelectric material base 119, such as PZT can be made for example by sputtering in an RF magnetron type reactor.
• the deposited layer of piezoelectric material 120 preferably has a thickness less than that of the dielectric layers usually used in microelectronic devices to isolate two levels of metal between them, for example a thickness of less than 1 micrometer.
• the layer based on piezoelectric material 120 may have a thickness, for example between 1 nanometer and 1 micrometer or for example between 5 nanometers and 300 nanometers.
• the layer of piezoelectric material may be continuous and formed so as to cover the upper face and the sidewalls or side faces of the gate 116 of the transistor, as well as the active area, and in particular the source 104 and drain 108 regions of the semiconductor layer 102 ( Figure 3B).
• the layer 120 may then be optionally etched between the different active zones.
• This insulating layer 130 may have a thickness of between 0.2 ⁇ m and 1, 5 microns, for example of the order of 0.8 .mu.m.
• openings 132, 134, 136 are made respectively revealing, the source region 104, the gate 116, and the drain region 108.
• These openings 132, 134, 136 can be achieved for example by forming a masking (not shown) on the insulating layer 130, then etching the insulating layer 130 and the layer 120 through said masking, for example using a gas fluorocarbon or wet etching with HF or HCl.
• the openings 132, 134, 136 are filled with a conductive material 140, for example based on tungsten, or aluminum in order to form conductive pads 142, 144, 146, in contact respectively with the source region 104, the drain region 108, and the gate 116 of the transistor on the one hand, and on the other hand in contact with the piezoelectric layer 120.
• the conductive pads 142, 144, 146 are intended to electrically connect or respectively connect the source regions 104, the drain regions 108, and the gates 116 of the transistors to respective biasing means of the source region 104, the gate 116, and drain region 108.
• a variant of the example of embodiment previously described allowing the implementation of a device of the type of that described above in connection with FIG. 1B, comprises after the realization of the source regions 104, drain 108, and gate 116, the formation of a layer 220 of piezoelectric material 119 only on the source region 104 or a portion of the source region 104, as well as on the gate 116 or a portion of the gate 116.
• a withdrawal of the latter may be carried out in zones situated opposite or above the drain region 108, and Preferably the entire piezoelectric material 119 may also be withdrawn on a sidewall of the gate 116 located on the drain region side, as well as on a portion of the upper face of the gate 116.
• This removal of the piezoelectric material 119 may for example comprise the realization of a masking (not shown) protecting the source region 108, as well as a lateral flank of the gate 116, located on the side of the source region 108 and a portion of the upper face of the gate 116 in the extension of this sidewall, then an etching of the piezoelectric material 119, for example an HcI-based wet etching through the masking (FIG. 4A).
• the deposition of the insulating layer 130 is carried out, then, openings are formed through the latter, respectively revealing, the source region 104, the gate 116, and the drain region 108.
• openings formed only those revealing respectively the source region 104 and the drain region 108 also reveal the piezoelectric layer 220.
• the openings are filled with a conductive material 140, for example based on tungsten, aluminum to form conductive pads 242, 244, 246 respectively.
• a conductive material 140 for example based on tungsten, aluminum to form conductive pads 242, 244, 246 respectively.
• the pads 242 and 244 in contact respectively with the source region 104 and the gate 116, are also in contact with the piezoelectric layer 220.
• the conductive pad 246 in contact with the drain region 108 is disjoint or not in contact with the piezoelectric layer 220.
• the conductive pads 242, 244, 246 are intended to electrically connect or respectively connect the source regions 104, the drain regions 108, and the grids 116, respectively, of the transistors to polarization means of the region of source 104, gate 116, and drain region 108.
• a step of forming a thin intermediate layer on the active zone may be provided prior to the formation of the piezoelectric layer 120 or 220.
• the piezoelectric layer is then formed on this thin insulating intermediate layer and above or opposite to at least a portion of the source 104, as well as on at least a portion of the gate 116.
• the thin insulating intermediate layer may be intended to reduce the mechanical stress exerted by the piezoelectric layer.
• the thin intermediate insulating layer can also serve as an etch stop layer.
• the method according to the invention is not limited to the formation of conventional transistor structures and may comprise, for example, replacing the transistor (s) embodiment described in connection with FIG. at least one double gate transistor, or / and at least one type of transistor called “FinFet” such as in document [1] (referenced above) or / and at least one transistor called “trigate” or " triple grid “as in document [2] (referenced above), and / or at least one so-called” coating "gate transistor such as in document [3] (referenced above), commonly called GAA (GAA for "spoils garlic around” according to the English terminology).
• Another exemplary embodiment method implements a formation on a substrate of at least a first transistor having at least one source region and at least one drain region, as well as at least one semiconductor structure, connecting the source region and the drain region, then an embodiment of at least one piezoelectric layer on the semiconductor structure, then forming at least one gate above the piezoelectric layer .
• the gate may be formed on the piezoelectric layer, so as to be in contact with this piezoelectric layer.
• the piezoelectric layer may be formed on a gate dielectric layer.
• the piezoelectric layer may be formed on the semicircular structure conductive, so as to be in contact with the semiconductor structure for forming a channel.
• the piezoelectric layer may be formed prior to the deposition of a gate dielectric layer and a gate on the gate dielectric layer.
• the piezoelectric layer can be made on the semiconductor structure. A grid is then formed on the piezoelectric layer. According to this third possibility, the piezoelectric layer may act as gate dielectric.
• the piezoelectric layer is based on at least one semiconductor material, and the semiconductor structure is formed. According to this fourth possibility, the semiconductor structure and the piezoelectric layer are intended to form a channel for said transistor.
• FIG. 5 illustrates another variant of a device that also implements piezoelectric type means making it possible to apply a modulable mechanical stress on the channel structure 112 of a transistor T 4 .
• the channel structure may be based on at least one semiconductor material, for example based on at least one semiconductor material among the following materials: Si, Ge, SiGe, GaAs.
• the piezoelectric means comprise in particular a piezoelectric layer denoted 320, of composition which may be similar to that of the layers 120 or 220, but arranged differently.
• the piezoelectric layer 320 is located between the gate 116 of the transistor T 4 and the gate dielectric 113 of this transistor.
• the piezoelectric layer 320 may be in contact with both the gate 116 and the gate dielectric 113 of the transistor T 4 .
• FIG. 6 illustrates another variant of a device that also implements piezoelectric type means making it possible to apply a modulable mechanical stress on the channel structure 112 of a transistor T 5 .
• the channel structure may be based on at least one semiconductor material, for example based on at least one semiconductor material among the following materials: Si, Ge, SiGe, GaAs.
• the piezoelectric means comprise in particular a piezoelectric layer denoted 420, of composition which may be similar to that of the layers 120 or 220 or 320, but arranged differently.
• the piezoelectric layer 420 is located between the gate dielectric 133 of the transistor T 5 and the channel 112 of this transistor.
• the piezoelectric layer 420 may be in contact with both the gate dielectric 113 and the channel 112 of the transistor T 5 .
• FIG. 7 illustrates another variant of a device that also implements piezoelectric type means making it possible to apply a modulable mechanical stress on the channel structure 112 of a transistor T 6 .
• These piezoelectric means comprise in particular a piezoelectric layer denoted 520, of composition which may be similar to that of the layers 120 or 220 or 320, or 420, but arranged differently.
• the piezoelectric layer 520 is located between the gate 116 of the transistor T 6 and the channel 112 of this transistor, and serves as gate dielectric 116.
• the piezoelectric layer 520 may be in contact with both the gate 116 and with the channel 112 of the transistor T 6 .
• FIG. 8 illustrates another variant of a device that also implements piezoelectric type means making it possible to apply a modulable mechanical stress on the channel structure 112 of a transistor T 7 .
• the channel structure 112 may be based on at least one semiconductor material, for example based on at least one semiconductor material from among the following materials: Si, Ge, SiGe, GaAs.
• the piezoelectric means comprise in particular a piezoelectric layer denoted 620, of composition which may be different from that of the layers 120 or 220 or 320, or 420, and arranged with respect to the transistor T 7 , differently from the piezoelectric layers 120, 220, 320 , 420.
• the piezoelectric layer 620 may be based on a semiconductor and piezoelectric material 419 such as AsGa.
• the piezoelectric layer 620 can also be located under the gate dielectric 113 of the transistor T 7 and belong to the channel 112 of this transistor.
• the piezoelectric layer 720 may be in contact with the gate dielectric 113 and belong to the channel 112 of the transistor T 7 .

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