EP1803156A1 - Circuit integre relevant de la technologie dite "smart power" - Google Patents

Circuit integre relevant de la technologie dite "smart power"

Info

Publication number
EP1803156A1
EP1803156A1 EP05779140A EP05779140A EP1803156A1 EP 1803156 A1 EP1803156 A1 EP 1803156A1 EP 05779140 A EP05779140 A EP 05779140A EP 05779140 A EP05779140 A EP 05779140A EP 1803156 A1 EP1803156 A1 EP 1803156A1
Authority
EP
European Patent Office
Prior art keywords
voltage
gate
integrated circuit
mosfet
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05779140A
Other languages
German (de)
English (en)
Inventor
Wolfgang Wilkening
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1803156A1 publication Critical patent/EP1803156A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to an integrated circuit in smart power technology.
  • Such smart power circuits include drivers or a final stage in which currents of a few amperes are switched, and so-called smart circuit parts, which are designed for currents of a few micro to milli-ampere. They are used in particular in automotive applications in a voltage range from 40 to 60 V.
  • the components of the smart circuit components are isolated in the smart power technology from the substrate via PN or NP junctions with high breakdown voltages.
  • This z. B. in N-channel MOSFETs below serving as a body connection P-well a deep N-well, z. B. deep N-WeII or N-Epi, on a P-substrate, which isolates the connection of the low-voltage N-channel transistors ge compared to the substrate.
  • the breakdown voltage of the low-lying N-well with respect to the substrate is greater than 15V, z. In the range of 40-80 V.
  • ESD protection switching devices For protection against electrostatic discharge (ESD) special protective structures or ESD protection switching devices are provided. They have an HVMOS transistor, eg DMOS, which has a dielectric strength of, for example, 20 to 80 V.
  • the drain and source are located between the connection pads, between which the ESD current flows.
  • the gate is connected to the source via a gate resistor.
  • the gate Under ESD loading, the gate is controlled via the parasitic drain-gate capacitance of the MOSFET, so that the MOSFET dissipates the ESD current via the opened MOS channel.
  • the transistor is sufficiently large, is This limits the occurring ESD voltage, so that no damage to the drivers or the output stage or the smart power circuit parts or low-voltage circuit parts occurs.
  • the gate resistor pulls the gate to ground potential during normal operation so that the transistor blocks.
  • the gate resistance is typically 5 kohms to 100 kohms.
  • regions diffused for the gate resistance e.g. pwell, pbody, pfield - resistors trained.
  • Such resistances can be formed in the above-mentioned dimensions by diffusion with a relatively low surface covering and thus low costs.
  • the diffused gate resistances form parasitic transistors together with the P-type substrate.
  • the first parasitic substrate transistor is the PNP vertical parasitic transistor which is P-diffused, e.g. pbody as emitter, N-well, e.g. N-epi and P-substrate is formed.
  • the second parasitic transistor is the lateral NPN transistor connected between an N-well of another device or device block, e.g. a digital well, as emitter, p-substrate as Ba ⁇ sis and the N-well of the diffused Widertandes can be effective as a collector.
  • the integrated circuit according to the invention has some advantages.
  • the gate resistance is formed as a poly resistor, ie, made of polycrystalline silicon.
  • a poly resistor ie, made of polycrystalline silicon.
  • the ESD strength can be increased by up to a factor of two for the same area or cost.
  • the chip area or the costs for a given ESD strength can be reduced.
  • a gate limiting the turn-off control voltage UGS e.g. a Zener diode
  • a diode blocking the operating voltage between gate and drain e.g. Zener diode, or be connected in accordance with a chain of diodes, in order to additionally control the gate via this path.
  • FIG. 1 is a circuit diagram of an integrated circuit according to the invention with ESD protection transistor circuit according to ei ⁇ ner first embodiment
  • FIG. 3 shows an ESD protection transistor circuit according to a further embodiment.
  • An integrated circuit 1 has an output stage 2 in which currents of a few amperes are switched, and a smart circuit device 3 with smart circuit elements which are suitable for currents from a few micro to MiI - Ii amps are designed.
  • the output stage 2 and the smart circuit device 3 are connected between a high-voltage connection pad a1 for a high-voltage voltage U H > 15V and a ground connection pad a2 and, if appropriate, further connection pads; this z. B. in accordance with FIG. 1 in all embodiments, a further connection pad a3 for a Nieder ⁇ voltêt UL, z. B. less than or equal to 5 V, and optionally provided a further ground pad.
  • the low-voltage components of the smart circuit device 3 can also be connected to the high-voltage U H via corresponding series resistors.
  • the output stage 2 can also be arranged outside the integrating circuit 1 and is therefore shown by dashed lines in FIG. 1 and not shown in the further figures by way of example.
  • the components of the smart circuit device 3 are insulated from the substrate of the chip via PN or NP junctions with high breakdown voltages.
  • the breakdown voltage of the low-lying N-well with respect to the substrate is greater than 15V, z. In the range of 40-80 V.
  • an ESD protection transistor switching device 4 which, according to the embodiment of FIG. 1, comprises an HVMOS transistor T1, e.g. a DMOS transistor T1 having a withstand voltage of e.g. 20 to 80 V owns.
  • Drain D is shown in FIG. 1 at the high-voltage terminal pad a1 and S source on the ground terminal pad a2.
  • drain D may also be located directly on an input or output pad whose voltage resistance exceeds 15V.
  • the gate G is connected to source S via a resistor Rg. Under ESD stress, the gate G becomes across the parasitic drain-gate capacitance turned on by T1. Then T1 diverts the ESD current between drain D and source S via the open MOS channel. By T1 is dimensioned sufficiently large, thereby the voltage is limited, so that no damage occurs.
  • Rg is designed sufficiently high-impedance, so that under an ESD load the above-described capacitive control of T1 is achieved. For this purpose, Rg is typically 5 kohms to 100 kohms.
  • the high-voltage U H can on the one hand be a high-voltage supply voltage, if z. B. the dashed line output stage 2 is connected to the pads a1 and a2; furthermore, the pedestal a1 can also serve as a high-voltage generator.
  • Rg is referred to as poly-resistance, i. made of polycrystalline silicon.
  • a diode D1 for example a Zener diode, is connected between gate G and source S.
  • D1 is intended to limit the gate-source voltage UGS.
  • a diode D2 blocking the operating voltage U H , in particular a zener diode, or a chain of diodes between the drain D and the gate G, in order to additionally control the gate G via this path, ie with an ESD pulse via the reverse-biased diode when exceeding its limit voltage to pull the gate voltage upwards.
  • FIG. 3 shows a further embodiment in which the gate drive of the transistor T1 is connected via a correspondingly connected pre-stage 5, the corresponding 2 of the switching device 4 is formed amplified physiologicalsteu ⁇ is.
  • the pre-stage 5 thus has a second MOSFET T2, a zwi ⁇ tween its gate G2 and the source S2 of the second MOSFETs T2 connected resistor R2 and diodes D3 and D4.
  • R2 is again designed as a poly resistor.
  • a polarity reversal protection diode D5 can be connected between the connection pad a1 and drain D, which is shown by way of example in FIG.
  • the transistors T2 and T2 may in particular also be HVPMOS transistors.
  • the high voltage is at source and the ground at drain.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit intégré relevant de la technologie dite 'smart power', s'utilisant notamment dans le domaine automobile, qui présente au moins: des connexions haute tension (a1, a2) pour raccorder à une haute tension (UH), un dispositif de commutation intelligent (3) avec des composants basse tension et un circuit de protection ESD (4) commuté entre les connexions haute tension (a1, a2), qui présentent un transistor à effet de champ à portée isolée (T1) raccordé aux connexions haute tension (a1, a2) par sa source (S) et par son drain (D), la grille (G) dudit transistor est reliée par l'intermédiaire d'une résistance (Rg) à sa source (S). La résistance de grille (Rg) se compose de silicium polycristallin. Selon l'invention, l'utilisation de la polyrésistance en tant que résistance de grille (Rg) permet d'obtenir une résistance ESD élevée, avec une utilisation superficielle relativement réduite et des frais réduits. Une diode de protection (D1, D2) peut être avantageusement commutée entre la source (S) et la grille (G), ainsi qu'entre la grille (G) et le drain (D) du transistor à effet de champ à portée isolée (T1), dans chaque cas dans le sens de fermeture, ladite diode de protection bloquant au-dessus de la tension d'alimentation (UH).
EP05779140A 2004-10-16 2005-08-16 Circuit integre relevant de la technologie dite "smart power" Withdrawn EP1803156A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004050767A DE102004050767A1 (de) 2004-10-16 2004-10-16 Integrierte Schaltung in Smart-Power-Technologie
PCT/EP2005/054023 WO2006040211A1 (fr) 2004-10-16 2005-08-16 Circuit integre relevant de la technologie dite 'smart power'

Publications (1)

Publication Number Publication Date
EP1803156A1 true EP1803156A1 (fr) 2007-07-04

Family

ID=35445748

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05779140A Withdrawn EP1803156A1 (fr) 2004-10-16 2005-08-16 Circuit integre relevant de la technologie dite "smart power"

Country Status (6)

Country Link
US (1) US20080116519A1 (fr)
EP (1) EP1803156A1 (fr)
JP (1) JP2008517452A (fr)
CN (1) CN101040380A (fr)
DE (1) DE102004050767A1 (fr)
WO (1) WO2006040211A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8077440B2 (en) 2007-06-21 2011-12-13 Nxp B.V. ESD protection circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953192B2 (ja) * 1991-05-29 1999-09-27 日本電気株式会社 半導体集積回路
DE9403928U1 (de) * 1994-03-09 1994-08-04 Ic Haus Gmbh Schaltungsanordnung zur Verpolsicherung bei integrierten Schaltungen
EP0697757A1 (fr) * 1994-08-16 1996-02-21 United Memories, Inc. Circuit de protection contre les décharges électrostatiques pour dispositif de circuit intégré
US6064249A (en) * 1997-06-20 2000-05-16 Texas Instruments Incorporated Lateral DMOS design for ESD protection
US7280332B2 (en) * 2002-01-18 2007-10-09 The Regents Of The University Of California On-chip ESD protection circuit for compound semiconductor heterojunction bipolar transistor RF circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006040211A1 *

Also Published As

Publication number Publication date
US20080116519A1 (en) 2008-05-22
WO2006040211A1 (fr) 2006-04-20
DE102004050767A1 (de) 2006-04-20
CN101040380A (zh) 2007-09-19
JP2008517452A (ja) 2008-05-22

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