EP1777739A2 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents
Dispositif à semi-conducteurs et son procédé de fabrication Download PDFInfo
- Publication number
- EP1777739A2 EP1777739A2 EP07001638A EP07001638A EP1777739A2 EP 1777739 A2 EP1777739 A2 EP 1777739A2 EP 07001638 A EP07001638 A EP 07001638A EP 07001638 A EP07001638 A EP 07001638A EP 1777739 A2 EP1777739 A2 EP 1777739A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- insulating layer
- layer
- film
- hole
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000274426A JP4484345B2 (ja) | 2000-09-11 | 2000-09-11 | 半導体装置及びその製造方法 |
JP2000274427A JP2002083870A (ja) | 2000-09-11 | 2000-09-11 | 半導体装置及びその製造方法 |
EP01965571A EP1320884A2 (fr) | 2000-09-11 | 2001-09-11 | Dispositif semi-conducteur et procede de fabrication |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01965571A Division EP1320884A2 (fr) | 2000-09-11 | 2001-09-11 | Dispositif semi-conducteur et procede de fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1777739A2 true EP1777739A2 (fr) | 2007-04-25 |
EP1777739A3 EP1777739A3 (fr) | 2008-09-17 |
Family
ID=26599616
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01965571A Withdrawn EP1320884A2 (fr) | 2000-09-11 | 2001-09-11 | Dispositif semi-conducteur et procede de fabrication |
EP07001638A Withdrawn EP1777739A3 (fr) | 2000-09-11 | 2001-09-11 | Dispositif à semi-conducteurs et son procédé de fabrication |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01965571A Withdrawn EP1320884A2 (fr) | 2000-09-11 | 2001-09-11 | Dispositif semi-conducteur et procede de fabrication |
Country Status (5)
Country | Link |
---|---|
US (1) | US6949829B2 (fr) |
EP (2) | EP1320884A2 (fr) |
KR (1) | KR100479796B1 (fr) |
TW (1) | TW530380B (fr) |
WO (1) | WO2002023625A2 (fr) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4257051B2 (ja) * | 2001-08-10 | 2009-04-22 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
DE10250889B4 (de) | 2002-10-31 | 2006-12-07 | Advanced Micro Devices, Inc., Sunnyvale | Verbesserte SiC-Barrierenschicht für eine Kupfermetallisierungsschicht mit einem Dielektrikum mit kleinem ε und Verfahren zur Herstellung derselben |
US7449780B2 (en) * | 2003-03-31 | 2008-11-11 | Intel Corporation | Apparatus to minimize thermal impedance using copper on die backside |
US20050006770A1 (en) * | 2003-07-08 | 2005-01-13 | Valeriy Sukharev | Copper-low-K dual damascene interconnect with improved reliability |
JP3841092B2 (ja) | 2003-08-26 | 2006-11-01 | 住友電気工業株式会社 | 発光装置 |
KR100593737B1 (ko) | 2004-01-28 | 2006-06-28 | 삼성전자주식회사 | 반도체 소자의 배선 방법 및 배선 구조체 |
US7915735B2 (en) * | 2005-08-05 | 2011-03-29 | Micron Technology, Inc. | Selective metal deposition over dielectric layers |
KR100731085B1 (ko) * | 2005-09-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 듀얼 다마신 공정을 이용한 구리 배선 형성 방법 |
JPWO2007043100A1 (ja) * | 2005-09-30 | 2009-04-16 | スパンション エルエルシー | 半導体装置およびその製造方法 |
JP5019741B2 (ja) * | 2005-11-30 | 2012-09-05 | 東京エレクトロン株式会社 | 半導体装置の製造方法および基板処理システム |
JP5100057B2 (ja) * | 2006-08-18 | 2012-12-19 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US8021975B2 (en) * | 2007-07-24 | 2011-09-20 | Tokyo Electron Limited | Plasma processing method for forming a film and an electronic component manufactured by the method |
US7902641B2 (en) * | 2008-07-24 | 2011-03-08 | Tokyo Electron Limited | Semiconductor device and manufacturing method therefor |
TWI423461B (zh) * | 2008-09-18 | 2014-01-11 | Atomic Energy Council | 微晶矽薄膜鍍膜之生成方法及其生成裝置 |
TWI449802B (zh) * | 2012-06-06 | 2014-08-21 | Univ Nat Chiao Tung | 掺碳氮化矽薄膜及其製造方法與裝置 |
US10157933B2 (en) | 2016-04-19 | 2018-12-18 | Micron Technology, Inc. | Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus |
US11329062B2 (en) | 2018-10-17 | 2022-05-10 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array |
US11177278B2 (en) | 2019-11-06 | 2021-11-16 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array comprising strings of memory cells |
US11177159B2 (en) | 2019-11-13 | 2021-11-16 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array comprising strings of memory cells |
US11121144B2 (en) | 2019-11-13 | 2021-09-14 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array comprising strings of memory cells |
US11706918B2 (en) | 2020-07-01 | 2023-07-18 | Micron Technology, Inc. | Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells |
US11889683B2 (en) | 2020-07-01 | 2024-01-30 | Micron Technology, Inc. | Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223758A (ja) * | 1996-12-06 | 1998-08-21 | Sony Corp | 半導体装置 |
WO1999033102A1 (fr) * | 1997-12-19 | 1999-07-01 | Applied Materials, Inc. | Couche d'arret de gravure pour procede de double damasquinage |
WO2000021124A1 (fr) * | 1998-10-05 | 2000-04-13 | Tokyo Electron Limited | Dispositif a semi-conducteurs et procede de fabrication de ce dernier |
EP1146555A1 (fr) * | 1999-03-09 | 2001-10-17 | Tokyo Electron Limited | Dispositif semi-conducteur et procede de fabrication correspondant |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6140226A (en) * | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
US6068884A (en) * | 1998-04-28 | 2000-05-30 | Silcon Valley Group Thermal Systems, Llc | Method of making low κ dielectric inorganic/organic hybrid films |
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6312874B1 (en) * | 1998-11-06 | 2001-11-06 | Advanced Micro Devices, Inc. | Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials |
US6054398A (en) * | 1999-05-14 | 2000-04-25 | Advanced Micro Devices, Inc. | Semiconductor interconnect barrier for fluorinated dielectrics |
-
2001
- 2001-09-11 EP EP01965571A patent/EP1320884A2/fr not_active Withdrawn
- 2001-09-11 TW TW090122485A patent/TW530380B/zh not_active IP Right Cessation
- 2001-09-11 EP EP07001638A patent/EP1777739A3/fr not_active Withdrawn
- 2001-09-11 WO PCT/JP2001/007880 patent/WO2002023625A2/fr not_active Application Discontinuation
- 2001-09-11 US US10/380,038 patent/US6949829B2/en not_active Expired - Lifetime
- 2001-09-11 KR KR10-2003-7003543A patent/KR100479796B1/ko not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223758A (ja) * | 1996-12-06 | 1998-08-21 | Sony Corp | 半導体装置 |
WO1999033102A1 (fr) * | 1997-12-19 | 1999-07-01 | Applied Materials, Inc. | Couche d'arret de gravure pour procede de double damasquinage |
WO2000021124A1 (fr) * | 1998-10-05 | 2000-04-13 | Tokyo Electron Limited | Dispositif a semi-conducteurs et procede de fabrication de ce dernier |
EP1146555A1 (fr) * | 1999-03-09 | 2001-10-17 | Tokyo Electron Limited | Dispositif semi-conducteur et procede de fabrication correspondant |
Non-Patent Citations (1)
Title |
---|
FREEMAN D ET AL: "PROPERTIES OF LOW-PRESSURE CHEMICAL VAPOR DEPOSITED DIELECTRIC FILMS FROM HEXAMETHYLDISILAZANE" JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART A, AVS /AIP, MELVILLE, NY, US, vol. 7, no. 3, PART 01, 1 May 1989 (1989-05-01), pages 1446-1450, XP000126093 ISSN: 0734-2101 * |
Also Published As
Publication number | Publication date |
---|---|
WO2002023625A2 (fr) | 2002-03-21 |
WO2002023625A3 (fr) | 2003-03-06 |
US20040041266A1 (en) | 2004-03-04 |
TW530380B (en) | 2003-05-01 |
WO2002023625A8 (fr) | 2003-05-01 |
US6949829B2 (en) | 2005-09-27 |
EP1320884A2 (fr) | 2003-06-25 |
KR20030038736A (ko) | 2003-05-16 |
KR100479796B1 (ko) | 2005-03-31 |
EP1777739A3 (fr) | 2008-09-17 |
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