TW511233B - Oxygen-doped silicon carbide etch stop layer - Google Patents

Abstract

A low-k (k < 4.2) oxygen-doped SiC layer acts as an etch stop layer for dual-damascene applications. A dual-damascene structure includes: a base layer; a first dielectric layer formed on the base layer; an oxygen-doped silicon carbide etch stop layer formed on the first dielectric layer; and a second dielectric layer formed on the etch stop layer. The second dielectric layer is deposited by using a chemical vapor deposition (CVD) method. The novel oxygen-doped etch stop layer presents a lower dielectric constant (k ~ 4.1), better mechanical properties, and improved electrical properties.

Description

511233 V. Description of the invention (l) Field of the invention The present invention provides an integrated circuit structure (especially an air-doped (〇Xygen_d〇ped) Shi Xi carbon compound money stop layer, especially for double Dual-damascene interconnect applications. Background In recent years, as the demand for high speed devices has increased, the development of low dielectric constant materials and low conductivity materials has continued. Basically, the efficiency and speed of the interconnect structure can be expressed as RC delay (RC del ay), where R is the resistance of the wire and C is the capacitance of the dielectric material between the two wires. Therefore, the use of a dielectric material with a lower dielectric constant can reduce the inter-metal capacitance, resulting in lower RC delay and higher operating efficiency. The dual damascene process is a metal interconnect technology widely used in high-speed logic device manufacturing below 0.25 microns. In a dual damascene process, metal interconnects are defined in a trench pre-etched into a dielectric layer. At present, the most common metal wire used in the dual damascene process is copper, and the contact window plugs that play the role of connecting different layers of wires are also formed in a via hole (v i a h ο 1 e) together with the copper wires. As if you are familiar with this technique

Page 5 511233 V. Description of the invention (2) The artist knows that 'typical dual-mosaic technology includes a (via-first) process; (2) self-alignment f) interstitial hole priority Ά (^ V' # ^. • Dry, self-aligned) process and (3) trench-first process. Before the formation of the double-conformation method, a two-layer, four-layer structure is constructed. As shown in Figure 1, no matter which book is used, the dielectric layer 22 and # # r u 通 23 will be on the upper and lower layers. Dielectric layer 22, which is the accumulation between μ p L 4T-etch stop layer, stacked dielectric secondary layer 23-traditional double damascene-the underlying dielectric layer, the layer below the 3 ° is usually a wire layer! 2. 〃 3 has the metal covered by the -resistance layer 21. See Figure 2 and Figure 2 for the dielectric layer structure. As shown in the figure, after forming the double damascene structure, it is not formed in the dielectric layer 22, and the etching stop layer 23 can be divided into a trench structure 42: a U-shaped structure 41 and a shape layer in the dielectric layer 24 22 and the barrier layer 2 = ,, and the structure 41 passes through the #etch stop layer 23 and the dielectric layer 12. The conventional method for reaching the metal wires in the underlying dielectric layer 10 is generally adopted. However, due to the decrease in the operating speed of the dielectric interconnects of silicon nitride, it is proposed to use SiC in No. 103, No. 2 and No. 5 (the dielectric A constant of approximately 4 silicon nitride is used as a material for the etch stop layer 2 3. An excessively high electric constant (&gt; 6.5) will result in gold. Furumura et al., In US Patent No. 5, silicon carbide (silicon carbide, ~ 5) as a Shixi substrate and a metal guide

511233 V. Description of the invention (3) Barrier material for wire layer. In US Patent No. 5,818, 071, Mark et al. Further applied an amorphous silicon (—01 ^ 110 ^ 13) silicon-carbon compound barrier material between the metal wire and the dielectric layer to prevent metal diffusion. Although Shi Xi carbon compound has low dielectric constant, it still has some disadvantages in application, including ... (1) low breakdown voltage (breakdown v ο 11 age); (2) leakage current of 咼; and (3 ) Unstable film characteristics. For this reason, some studies in recent years have found that doping nitrogen into silicon carbon compounds can improve these characteristics. However, doping nitrogen in silicon carbon compounds may produce amine compounds, resulting in deep ^ να blocking footing effect and vU blinding. Summary of the Invention • Therefore 'The main object of the present invention is to provide a metal interconnect structure with high performance. Another object of the present invention is to provide an application of an oxygen-doped silicon carbon compound layer' to improve the reliability of the metal interconnect. According to the purpose of the present invention, a preferred embodiment of the present invention discloses an integrated circuit structure, which includes: a bottom layer; a first-dielectric layer, forming

511233 V. Description of the invention (4) on the bottom layer; an etch stop layer on the first dielectric layer; and a second dielectric layer formed on the tooth layer; wherein the etch stop layer The soil layer is composed of oxygen-doped SiC, and the second dielectric layer is formed by a CVD process. According to the purpose of the present invention, another aspect of the present invention is A better implementation of a dual-mosaic interconnect structure includes a bottom layer with a conductive layer thereon; a first dielectric layer formed on the bottom layer; a stop layer formed on the first layer On the dielectric layer; a dielectric layer is full of holes), formed in the first dielectric layer and the stop layer, and part of the conductive layer, a first dielectric layer is formed on a trench line on the stop layer, A metal wire is contained in the second dielectric formed above the dielectric hole; wherein the stop layer is made of oxygen-doped SiC, and the second dielectric layer is A vapor deposition (C VD) process is formed. ′ Detailed description of the invention The technical feature of the present invention is that an oxygen-doped SiC layer is used as an etching stop layer. Double damascene metal interconnect process. Oxygen-doped silicon-carbon compounds ^ acoustic constants (k &lt; 4.2), high breakdown voltage, and excellent thickness can improve component reliability and operating efficiency. ^ MU Cheng was stopped at the moment of the J-Chemistry J-series exposure. Formed &gt; Stop Layer 1 (via exposed •; and 'Used for ▲ Compound I chemical layer for low dielectrics'. Therefore 511233 V. Invention Explanation (5) Please refer to FIG. 3, which is a schematic cross-sectional view of the stacked dielectric layer 300 of the present invention after completing the dual damascene structure 140. As shown in FIG. 3, the stacked dielectric layer 300 includes a first dielectric An electrical layer 22 0 is formed on a barrier layer 21 0, an etch stop layer 2 30 having a thickness of about 500 Angstroms (A) is formed on the first dielectric layer 2 2 0 and a second dielectric layer 24 0 is formed on the money stop layer 230. The barrier layer 2 10 is formed on a bottom layer 100. The bottom layer 100 includes a conductive layer 120. The dual damascene structure 140 includes a trench. The line structure 1 4 2 is formed in the second dielectric layer 2 4 0, and a via hole 1 4 1 is formed in the etch stop layer 2 3 0, the first dielectric layer 2 2 0, and the barrier layer 2 1 0. &quot; The via hole i 4 1 exposes a part of the conductive layer 1 2 0. The method of the double mosaic structure 1 4 0 can adopt a contact window priority (via-f 丨 rst) process, part of the contact (Partia 1-via) process, self-aligned process, trench-first process, or other inlaid metal interconnect process. The technique of forming a double inlaid structure 1 40 is known to the art It is well known to those skilled in the art, and is not the focus of the present invention, so it will not be described in detail. For the related double setting process, please refer to US Patent No. 6,197,6 1 and US Patent No. 6,0 0 4 , 1 8 8th.

The material of the first dielectric layer 220 and the second dielectric layer 240 can be selected from one of the following combinations: fluorinated silicon glass (FSG), HSQ, MSQ (methyl silsesquioxane), and black diamond Materials, Coral, porous Shixi glass

511233 V. Description of the invention (6) silica), amorphous fluorocarbon polymers, fluorinated polyimide, PTFE, poly (arylene ether), benzocyclobutene , SiLKT ^ &amp; FLARE%, etc. It is generally recommended that the dielectric constants of the first dielectric layer 220 and the second dielectric layer 240 be better than 3.2. In a preferred embodiment of the present invention, the second dielectric layer 240 is deposited by a chemical vapor deposition (CVD) process, and a precursor gas used includes methyl sintered species, such as methyl Shiyaki (methylsilane, Si (CH3) H3), 2-methylsilane (Si (CH3) 2H2), trimethylsilane (Si (CH3) 3H), and tetramethyl Shi Xiyao (4-methylsilane, Si (CH3) 4). The metal wire layer 120 is composed of copper. The method of forming the copper metal wire layer is based on conventional techniques such as physical vapor deposition (PVD), electroplating, sputtering, or eiectron beam evaporation # ^ 〇 The method of forming the engraved stop layer 2 3 0 is formed by a plasma-enhanced chemical vapor deposition (PECVD) process. PECVD process parameters, including gas, operating pressure: temperature, and reaction time, can be adjusted for 5 weeks depending on the type of machine or process. For example, a process parameter package for depositing an etch stop layer 2 3 0

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The flow rate of dimethyl silane is about 60 〇sccm; the flow rate of oxygen is about 30 Sc ^ m; the radio frequency of the radio frequency (HFRF) is about 500,000 Watts (Watts), the operating pressure is about 0.5 to 5 Torr The ear is preferably 2 Torr; and the temperature is about 350 to 450 ° C, and preferably 40 fc. In other embodiments of the present invention, the process precursor gas may be methyl silane, dimethyl silane, or dimethyl silane. Please refer to Table 1. Table 1 is an etch stop layer of the present invention (500A hybrid electric hJVI test table. In the table-at the same time, the electrical properties of the same thickness of the unblended money etch stop layer are compared. The dielectric constant of the ii If engraved stop layer can reach about ^ 'cm (U / cW). Compared to I.01. 9 amps per square meter: the dielectric constant is about 4 5 ', the electrical properties of the tftt carbon compound layer, including ^ about 1.3E-8 amps per square \ electric manpower ^ 3.5 The MV / Cm 'leakage current stop layer obviously has better voltage. Modification (A / Cin2), the etching stop of the present invention The above description is only an equivalent variation range made by the scope of this patent. In the preferred embodiment of the month, any application for A and modification according to the present invention shall fall within the scope of the present invention patent.

511233 Simple illustration of the diagram. Simple illustration of the diagram. Figure 1 shows the stacked dielectric layer structure of the conventional method before forming the dual damascene structure. Figure 2 shows the stacked dielectric layer structure of the conventional method after forming the dual damascene structure. This is a schematic cross-sectional view of the stacked dielectric layer after the dual damascene structure is completed. Table 1 shows the electrical measurement values of the etch stop layer (50 OA S i 0 XC y) according to the present invention. Explanation of symbols in the figure 10 bottom layer 12 conductive layer 21 barrier layer 22 first dielectric layer 23 last stop layer 24 second dielectric layer 30 stacked dielectric layer structure 41 via hole 42 trench line 100 bottom layer 120 conductive layer 140 Double damascene structure 141 Dielectric hole 142 Trench line 210 Barrier layer 220 First dielectric layer 230 1 Moss stop layer 240 Second dielectric layer 300 Stacked dielectric layer structure

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Claims (1)

511233 6. Scope of patent application 1. An integrated circuit including: a bottom layer; a first dielectric layer formed on the bottom layer; a #etch stop layer formed on the bottom layer The first dielectric layer; and a second dielectric layer formed on the etch stop layer; wherein the etch stop layer is composed of an oxygen-doped silicon carbon compound (S i 0 XC y). 2. The integrated circuit of item 1 of the patent application, wherein the thickness of the etch stop layer is about 500 angstroms. 3. The integrated circuit of item 1 in the patent application scope, wherein the etching stop layer is formed by a plasma-enhanced chemical vapor deposition (PECVD) process. 4. If the integrated circuit of item 1 of the patent application scope, wherein the dielectric constants of the first dielectric layer and the second dielectric layer are less than 3.2. 5. The integrated circuit of item 1 of the patent application, wherein the second dielectric layer is a chemical vapor deposition (CVD) film. 6. If the integrated circuit of item 5 of the patent application scope, wherein the second dielectric Page 13 511233 _Case No. 90127191_Qiao 丨 Year 丨 October) Date Amendment_ VI. Scope of patent application The layer is deposited by using methyl crushed gas as a precursor (p r e c u r s 〇 r). '7. For the integrated circuit of item 6 in the scope of patent application, wherein the methyl silane gas includes methyls i lane (Si (CH 3) H3), dimethyl stone yaki (2-methylsilane) , Si (CH3) 2H2), 3-methylsilane, Si (CH3) 3H, and 4-methylsilane, Si (CH3) 4. The integrated circuit of item 1, wherein the dielectric constant of the etch stop layer is about 4.1. 9. For the integrated circuit of item 1 of the scope of patent application, wherein the breakdown electric field of the etch stop layer is about 5.0 MV / cm (under the condition that the thickness of the stop layer is 500 angstroms). 1 0. A dual-mosaic interconnect structure including: a bottom layer on which a conductive layer is formed; a first dielectric layer formed on the bottom layer; a stop layer formed on the bottom layer On the first dielectric layer; a via hole is formed in the first dielectric layer and the stop layer, and a part of the conductive layer is exposed; a second dielectric layer is formed in the stop layer And a trench line formed in the second dielectric layer above the dielectric hole, Page 14 511233 _Case No. 90127191_% Year 3 Amendment_ VI. The scope of the patent application is used to accommodate a metal wire; among them, the stop layer is made of oxygen-doped stone carbon compounds (〇U ge η-d 〇ped S i C), and the second dielectric layer is formed by a chemical vapor deposition (CVD) process. 1 1. The dual damascene interconnect structure according to item 10 of the application, wherein the stop layer is formed by a plasma enhanced chemical vapor deposition (PECVD) process. 1 2. The dual-mosaic interconnect structure according to item 10 of the application, wherein the second dielectric layer is deposited by using a methyl silane gas as a precursor. 1 3. The dual-mosaic interconnect structure according to item 12 of the patent application scope, wherein the methyl silane gas includes methyl silane (Si (CH3) H 3), dimethyl silane (Si (CH3) 2H2 ), Trimethylsilane (Si (CH3) 3H), and tetramethylsilane (Si (CH3) 4). 14. The dual-mosaic interconnect structure according to item 10 of the patent application, wherein the dielectric constant of the stop layer is approximately 4.1. 1 5. According to the dual-mosaic interconnect structure of the 10th in the scope of the patent application, wherein the stoppage layer has a breakdown power of about _ about 5.0 MV / cm (under the condition that the thickness of the stop layer is 50 Angstroms) . Page 15