EP1750453A1 - Digitaler signalempfänger und steuerverfahren dafür - Google Patents

Digitaler signalempfänger und steuerverfahren dafür Download PDF

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Publication number
EP1750453A1
EP1750453A1 EP04807080A EP04807080A EP1750453A1 EP 1750453 A1 EP1750453 A1 EP 1750453A1 EP 04807080 A EP04807080 A EP 04807080A EP 04807080 A EP04807080 A EP 04807080A EP 1750453 A1 EP1750453 A1 EP 1750453A1
Authority
EP
European Patent Office
Prior art keywords
signal
section
digital
video data
audio data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP04807080A
Other languages
English (en)
French (fr)
Other versions
EP1750453A4 (de
Inventor
Satoshi Mats. El. Ind. Co. IPROC IP TAKAHASHI
Ryogo Mats. El. Ind. Co. IPROC Ip YANAGISAWA
Shuji Mats. El. Ind. Co. IPROC IP Dev Ct KATO
Shinichi Mats. El. Ind. Co. IPROC IP HASHIMOTO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of EP1750453A1 publication Critical patent/EP1750453A1/de
Publication of EP1750453A4 publication Critical patent/EP1750453A4/de
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H04N21/4341—Demultiplexing of audio and video streams
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4436—Power management, e.g. shutting down unused components of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
    • H04N5/602—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals for digital sound signals

Definitions

  • the present invention relates to a digital signal receiver, and more particularly, to a digital signal receiver suitable for receivers for digital AV (audio and video) signals, such as digital televisions, flat display panels, digital video recorders, and the like.
  • digital AV audio and video
  • a digital AV signal in which video data and audio data are multiplexed is serially transmitted.
  • Digital signal receivers decode received a digital AV signal, and further, separate the digital AV signal into video data and audio data, which are in turn output.
  • Audio data is typically overlaid, in the form of packets, on blanking intervals of video data.
  • An audio data processing section in the digital signal receiver converts audio data in the form of packets into audio data in the form of a stream, which is in turn output.
  • a video data processing section in the digital signal receiver performs a process, such as format conversion or the like, with respect to the separated video data, and outputs the processed video data.
  • a clock signal is transmitted in a transmission line separated from an AV signal transmission line.
  • the digital signal receiver generates its own operation clock signal from the given clock signal.
  • a digital signal receiver which comprises a plurality of signal receiving sections each receiving a digital AV signal and a clock signal and can receive a plurality of channels of digital AV signals.
  • Such an apparatus typically comprises a selection section for selecting any one of a plurality of channels of digital AV signals and clock signals.
  • a video data processing section and an audio data processing section process video data and audio data of a channel selected by the selection section. In other words, each signal receiving section is exclusively used.
  • Patent Document 1 Japanese Patent Unexamined Publication No. 2000-261497 (page 4, figure 1)
  • the above-described operation clock signal is generated by a phase locked loop provided in the digital signal receiver.
  • some time is required for the phase locked loop to output a stable signal after receiving a clock signal.
  • a section for receiving and processing a digital AV signal, a section for decoding data, and the like are operated even during the time when the operation clock signal is not yet stable.
  • the video data processing section and/or the audio data processing section is operated.
  • signal receiving sections for channels which are not selected are operated.
  • power is wasted in many respects.
  • encryption information needs to be added to a packet header in order to determine whether or not data is encrypted, in units of a packet. Further, a header separating means for separating a packet header and a header analyzing means for analyzing a header are required, resulting in an increase in circuit scale of the apparatus.
  • an object of the present invention is to provide a digital signal receiver which reduces power consumption in the apparatus without particularly increasing the circuit scale.
  • a digital signal receiver comprises a signal separating section for separating video data and audio data from a given digital AV signal, a video data processing section for processing the video data separated by the signal separating section, an audio data processing section for processing the audio data separated by the signal separating section, and a clock signal generating section for, from a given first clock signal, generating a second clock signal for operating the signal separating section, the video data processing section, and the audio data processing section.
  • the digital signal receiver further comprises a control section for controlling an operating state of a control subject based on a clock stability signal indicating that the second clock signal generated by the clock signal generating section is stable, where the control subject is at least one of the signal separating section, the video data processing section, and the audio data processing section, wherein the control section pauses the control subject until receiving the clock stability signal.
  • a digital signal receiver comprises a signal separating section for separating video data and audio data from a given digital AV signal, a video data processing section for processing the video data separated by the signal separating section, and an audio data processing section for processing the audio data separated by the signal separating section.
  • the digital signal receiver further comprises a control section for controlling an operating state of a control subject based on a determination signal indicating whether or not video data and audio data are included in the digital AV signal, where the control subject is at least one of the video data processing section and the audio data processing section, wherein the control section pauses the video data processing section when the determination signal indicates that video data is not included in the digital AV signal, and pauses the audio data processing section when the determination signal indicates that audio data is not included in the digital AV signal.
  • the video data processing section for processing video data is not operated. Also, when the determination signal indicates that audio data is not included in the digital AV signal, the audio data processing section for processing audio data is not operated.
  • a digital signal receiver comprises a plurality of signal receiving sections each having a signal separating section for separating video data and audio data from a given digital AV signal, and a clock signal generating section for generating, from a given first clock signal, a second clock signal for operating the signal separating section, and a selection section for selecting any one of the plurality of signal receiving sections based on a given select signal, and outputting the audio data, the video data and the second clock signal output from the selected signal receiving section.
  • the digital signal receiver further comprises a control section for controlling an operating state of a control subject based on the select signal, where the control subject is at least one of the signal separating section and the clock signal generating section, wherein the control section pauses the control subject belonging to one of the plurality of signal receiving sections which is not selected by the select signal.
  • a control subject is paused until receiving a clock stability signal indicating that the second clock signal generated by the clock signal generating section is stable, where the control subject is at least one of the signal separating section, the video data processing section, and the audio data processing section.
  • the video data processing section is paused when a determination signal indicating whether or not video data and audio data are included in the digital AV signal, indicates that video data is not included in the digital AV signal, and the audio data processing section is paused when the determination signal indicates that audio data is not included in the digital AV signal.
  • the video data processing section for processing video data is not operated. Also, when the determination signal indicates that audio data is not included in the digital AV signal, the audio data processing section for processing audio data is not operated.
  • a digital signal receiver which comprises a plurality of signal receiving sections each having a signal separating section for separating video data and audio data from a given digital AV signal, and a clock signal generating section for generating, from a given first clock signal, a second clock signal for operating the signal separating section, and a selection section for selecting any one of the plurality of signal receiving sections based on a given select signal, and outputting audio data, video data and a second clock signal output from the selected signal receiving section, a control subject belonging to one of the plurality of signal receiving sections which is not selected by the select signal is paused, where the control subject is at least one of the signal separating section and the clock signal generating section.
  • a portion which is not required for an operation is paused, depending on the state of the digital signal receiver. Specifically, a portion which is not required in the digital signal receiver is paused when a cable for linking to a transmitter is not connected, when the transmitter, if connected, is not powered ON, when the transmitter, if connected, does is not transmitting valid data, when audio or video data is not included in a digital AV signal, when a plurality of signal receiving sections are exclusively used, or the like, thereby reducing power consumption in the apparatus.
  • FIG. 4 schematically illustrates an AV signal before being encoded.
  • Line 1 to line X+Y which are output continuously in time series constitute the pre-encoded AV signal (hereinafter simply referred to as a "signal") 301.
  • signal 301 hatched portions from line X+1 to line X+Y indicate a video signal, and the other portions indicate an audio signal and a control signal.
  • the control signal includes a vertical synchronizing signal indicating a boundary between each frame, a horizontal synchronizing signal indicating a boundary between each line, a data enable signal indicating a boundary between video data and other data in each line, and the like.
  • the above-described signal 301 is encoded, and further, is transmitted as a signal by a predetermined transmission technique (e.g., a differential signal).
  • FIG. 1 illustrates a configuration of a digital signal receiver according to a first embodiment of the present invention.
  • the digital signal receiver of this embodiment comprises a signal receiving section 13 composed of a signal separating section 11 and a clock signal generating section 12, an output section 16 composed of a video data processing section 14 and an audio data processing section 15, and a control section 17.
  • the signal separating section 11 restores and decodes encoded data from a given digital AV signal 101, and separates and outputs video data 102 and audio data 103 from the decoded data.
  • the clock signal generating section 12 multiplies a frequency of an input clock signal 104 to output a clock signal 105.
  • the clock signal generating section 12 comprises a phase locked loop (not shown), and uses the phase locked loop to multiply the frequency of the clock signal 104 to generate the clock signal 105.
  • the video data processing section 14 processes the video data 102 to output a video signal 106.
  • the audio data processing section 15 processes the audio data 103 to output an audio signal 107.
  • the signal separating section 11, the video data processing section 14, and the audio data processing section 15 are each operated using the clock signal 105 as an operation clock signal.
  • the clock signal generating section 12 outputs a clock stability signal 108 indicating that the clock signal 105 is stable.
  • a clock stability signal 108 for example, a lock signal which is output from a phase comparator (not shown) in the phase locked loop, may be used. This is because the outputting of the lock signal from the phase comparator indicates that an output of the phase locked loop is locked to a predetermined frequency.
  • the control section 17 outputs a control signal 109 to control operating states of the signal separating section 11, the video data processing section 14, and the audio data processing section 15, which are subjects to be controlled. Specifically, the control section 17 pauses the control subject until receiving the clock stability signal 108. After receiving the clock stability signal 108, the control section 17 operates the control subject.
  • control section 17 Next, some examples of the control by the control section 17 will be illustrated.
  • the control section 17 interrupts power supplied to the control subject until receiving the clock stability signal 108. After receiving the clock stability signal 108, the control section 17 supplies power to the control subject.
  • the control section 17 interrupts the clock signal 105 which is supplied to a flip-flop (not shown) in the control subject until receiving the clock stability signal 108. After receiving the clock stability signal 108, the control section 17 supplies the clock signal 105 to each flip-flop.
  • the control section 17 asserts the control signal 109 as a reset signal with respect to the control subject until receiving the clock stability signal 108. After receiving the clock stability signal 108, the control section 17 deasserts the control signal 109.
  • the control section 17 gives a fixed signal, instead of the digital AV signal 101, to the signal separating section 11 until receiving the clock stability signal 108. After receiving the clock stability signal 108, the control section 17 gives the digital AV signal 101 to the signal separating section 11.
  • the signal separating section 11, the video data processing section 14, and the audio data processing section 15 are not operated until the clock signal 105 becomes stable, so that power is not wasted.
  • the control section 17 has a relatively small circuit scale. Therefore, power consumption in the digital signal receiver can be reduced without increasing the circuit scale.
  • FIG. 2 illustrates a configuration of a digital signal receiver according to a second embodiment of the present invention.
  • the digital signal receiver of this embodiment is different from that of the first embodiment in the operation of the control section 17.
  • the digital signal receiver of this embodiment is similar to that of the first embodiment and will not be described in detail.
  • a signal separating section 11 detects whether or not video data and audio data are included in an input digital AV signal 101 to output a determination signal 110 indicating a result of the detection. Specifically, the signal separating section 11 detects whether or not video data is present in data obtained by decoding the digital AV signal 101, and when video data is present, detects whether or not an audio sample packet is present during a video data blanking interval. For techniques of multiplexing and transmitting packet data other than video data during video data blanking intervals, a process of separating packet data and video data is essentially required. The signal separating section 11 outputs information which is secondarily generated in such a separation process, as the determination signal 110.
  • a control section 17 receives the determination signal 110, and based this, controls operating states of a video data processing section 14 and an audio data processing section 15. Specifically, when the control section 17 determines, based on the determination signal 110, that video data is not included in the digital AV signal 101 for a predetermined time, the control section 17 pauses the video data processing section 14. Also, when the control section 17 determines that an audio sample packet is not included for a predetermined time, the control section 17 pauses the audio data processing section 15.
  • the video data processing section 14 and the audio data processing section 15 may be paused by interrupting power supply, interrupting a clock, or asserting a reset signal, as in the first to third control examples. Also, these methods may be combined as appropriate.
  • the video data processing section 14 when video data is not included in the digital AV signal 101, the video data processing section 14 is paused, and when audio data is not included, the audio data processing section 15 is paused, whereby power is not wasted.
  • the control section 17 has a relatively small circuit scale. Therefore, power consumption in the digital signal receiver is reduced without increasing the circuit scale.
  • FIG. 3 illustrates a configuration of a digital signal receiver according to a third embodiment of the present invention.
  • the digital signal receiver of this embodiment comprises two signal receiving sections 13, an output section 16, a control section 17, and a selection section 18, and can receive two channels of digital AV signals 101 and clock signals 104. Note that the signal receiving section 13 and the output section 16 are similar to those of the first embodiment and will not be described.
  • the selection section 18 receives a select signal 111, and based on this, selects any one of the two signal receiving sections 13. Thereafter, the selection section 18 outputs video data 102, audio data 103, and a clock signal 105 which are received from the selected signal receiving section 13.
  • the control section 17 receives the select signal 111, and based on this, controls operating states of the signal separating section 11 and the clock signal generating section 12 as control subjects. Specifically, the control section 17 pauses a control subject included in the signal receiving section 13 which is not selected by the select signal 111.
  • the control subject is paused by interrupting power supply, interrupting a clock, asserting a reset signal, or inputting a fixed signal instead of a digital AV signal, as in the first to fourth control examples. Also, these methods may be combined as appropriate.
  • a signal receiving section 13 which is not selected is paused, so that power is not wasted.
  • the control section 17 has a relatively small circuit scale. Therefore, power consumption in the digital signal receiver is reduced without particularly increasing the circuit scale.
  • control section 17 may be provided outside the digital signal receiver.
  • the operating states of the signal separating section 11, the clock signal generating section 12, the video data processing section 14, and the audio data processing section 15 inside the digital signal receiver may be controlled by an external microcontroller as the control section.
  • control information may be written from the external control section into a register inside the digital signal receiver, and by referencing a value of the register, the operating states of the signal separating section 11, the clock signal generating section 12, the video data processing section 14, and the audio data processing section 15 may be controlled.
  • the digital signal receiver of the present invention is useful as a receiver in a system which transmits mainly a digital AV signal serially without compression, or, not limited to such a system, a receiver in a transmission system which overlays audio data on video data, a receiver which comprises a plurality of signal receiving sections and uses these exclusively, and the like.
  • the digital signal receiver of the present invention is useful as a receiver for which low power consumption is required.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Television Systems (AREA)
  • Television Receiver Circuits (AREA)
EP04807080A 2004-05-26 2004-12-15 Digitaler signalempfänger und steuerverfahren dafür Ceased EP1750453A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004156337 2004-05-26
PCT/JP2004/018721 WO2005117451A1 (ja) 2004-05-26 2004-12-15 デジタル信号受信装置及びその制御方法

Publications (2)

Publication Number Publication Date
EP1750453A1 true EP1750453A1 (de) 2007-02-07
EP1750453A4 EP1750453A4 (de) 2010-08-04

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EP04807080A Ceased EP1750453A4 (de) 2004-05-26 2004-12-15 Digitaler signalempfänger und steuerverfahren dafür

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US (1) US8089565B2 (de)
EP (1) EP1750453A4 (de)
JP (1) JP4512591B2 (de)
WO (1) WO2005117451A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5054542B2 (ja) * 2005-12-20 2012-10-24 パナソニック株式会社 機器連携装置、機器連携方法、プログラムおよび集積回路
JP5048534B2 (ja) * 2008-01-28 2012-10-17 マスプロ電工株式会社 信号レベル測定回路及び信号レベル測定装置

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EP1288892A2 (de) * 2001-08-29 2003-03-05 Samsung Electronics Co., Ltd. Skalierungschip und Anzeigegerät
US20040080671A1 (en) * 2002-06-14 2004-04-29 Duane Siemens Method and circuit for generating time stamp data from an embedded-clock audio data stream and a video clock

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JPH0670264A (ja) 1992-08-20 1994-03-11 Fujitsu Ltd テレビ受像機
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JP3288196B2 (ja) * 1995-05-09 2002-06-04 三菱電機株式会社 移動体通信端末
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US20040080671A1 (en) * 2002-06-14 2004-04-29 Duane Siemens Method and circuit for generating time stamp data from an embedded-clock audio data stream and a video clock

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STEVAN EIDSON ET AL: "30.2: HDMI: High-Definition Multimedia Interface" 2003 SID INTERNATIONAL SYMPOSIUM - MAY 20, 2003, BALTIMORE, MARYLAND, vol. XXXIV, 20 May 2003 (2003-05-20), page 1024, XP007008293 *

Also Published As

Publication number Publication date
JPWO2005117451A1 (ja) 2008-04-03
US20080136970A1 (en) 2008-06-12
US8089565B2 (en) 2012-01-03
JP4512591B2 (ja) 2010-07-28
WO2005117451A1 (ja) 2005-12-08
EP1750453A4 (de) 2010-08-04

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