EP1728269A1 - Procede de realisation d"un transistor a effet de champ a canal en carbone diamant et transistor obtenu - Google Patents
Procede de realisation d"un transistor a effet de champ a canal en carbone diamant et transistor obtenuInfo
- Publication number
- EP1728269A1 EP1728269A1 EP05744607A EP05744607A EP1728269A1 EP 1728269 A1 EP1728269 A1 EP 1728269A1 EP 05744607 A EP05744607 A EP 05744607A EP 05744607 A EP05744607 A EP 05744607A EP 1728269 A1 EP1728269 A1 EP 1728269A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- channel
- transistor
- diamond
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 229910052799 carbon Inorganic materials 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000012212 insulator Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011810 insulating material Substances 0.000 claims abstract description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 31
- 239000010432 diamond Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 23
- 230000008021 deposition Effects 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the invention relates to a method for producing a field effect transistor comprising a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator, the channel being constituted by a carbon layer. diamond.
- a field effect transistor has a source and a drain which are connected by a channel.
- a gate electrode separated from the channel by a gate insulator, makes it possible to control the conduction state of the channel.
- the source, the drain and the channel of the field effect transistors are made from semiconductor material, for example silicon.
- CMOS type inverter For the production of a CMOS type inverter, a PMOS type transistor and an NMOS type transistor are assembled. Optimal operation of the inverter requires that the saturation current in the PMOS transistor be equal to the saturation current in the NMOS transistor.
- the electric current flowing through the channel In an NMOS transistor, the electric current flowing through the channel is an electron current, while in a PMOS transistor, the electric current flowing through the channel is a hole current.
- the current is proportional to the mobility of the corresponding charge carriers. Since the mobility of electrons in silicon is greater than the mobility of holes in silicon, the dimensions of the NMOS and PMOS transistors are adapted so as to obtain equal saturation currents in the NMOS and PMOS transistors.
- the PMOS transistor of a CMOS inverter for example, has a channel width greater than the channel width of the associated NMOS transistor. The miniaturization of the CMOS inverter is then limited by the dimensions of the PMOS transistor.
- Field effect transistors having diamond channels are well known.
- a P-doped semiconductor diamond layer forms a channel.
- a source and a drain are formed by N-doped semiconductor diamond layers.
- a diamond gate insulator is placed on the channel and a gate electrode is placed on this gate insulator.
- the document US Pat. No. 5,107,315 also describes a transistor having an N-doped channel and P-doped source and drain. The fabrication of the transistor consists in successively making the channel, the source and drain, the gate insulator and the gate. Such a transistor may have parasitic capacitances between drain and gate and between source and gate, which deteriorates the performance of the transistor.
- the object of the invention is to remedy these drawbacks and in particular to make it possible to produce transistors and logic gates of small dimensions having low parasitic capacities.
- the method successively comprises the deposition of a layer of diamond carbon on a substrate, depositing a gate insulating layer on the diamond carbon layer, depositing, on the gate insulating layer, at least one conductive layer and its etching, so as to form the gate electrode, depositing 'an insulating material on the sides of the gate electrode to constitute a lateral insulator, the etching of the insulating gate layer, the etching of the diamond carbon layer so as to delimit the channel, the deposition, on both sides and 'other of the channel, a semiconductor material intended to constitute the source and a semiconductor material intended to constitute the drain.
- Another object of the invention is a transistor obtained by the method according to the invention and a CMOS type logic gate comprising such transistors.
- FIG. 1 to 5 illustrate a particular embodiment of a method for producing a transistor according to the invention.
- FIG. 6 schematically represents a CMOS inverter comprising transistors according to the invention. Description of particular embodiments
- the field effect transistor according to the invention comprises a channel formed by a diamond carbon layer.
- the channel can be doped with N type dopants to form a PMOS type transistor or P type dopants to form an NMOS type transistor.
- N type dopants for a doping of 10 15 atoms per cubic centimeter, diamond carbon has, at room temperature, an electron mobility of 1800cm 2 / Vs and a hole mobility of 1800cm 2 / Vs.
- a layer 1 of diamond carbon is deposited on a substrate 2, as shown in FIG. 1.
- the substrate may comprise, on its surface, a thin insulating layer, for example an oxide layer having a high dielectric constant , for example alumina.
- an insulating grid layer 3 is deposited on the diamond carbon layer 1.
- a conductive layer 4 is deposited on the insulating grid layer 3.
- the conductive layer 4 can be constituted by the superposition of a first conductive layer 4a and a second layer 4b, conductive or no, which can be used as an etching or implantation masking layer.
- the conductive layer 4a can be deposited by low pressure chemical vapor deposition or by epitaxy.
- An etching step makes it possible to delimit the conductive layer 4 laterally, by means of a mask (not shown), so as to form the gate electrode 5.
- the deposition of an insulating material on the sides of the gate electrode 5 makes it possible to constitute a lateral insulator 6 of the gate electrode 5.
- the lateral electrical insulator 6 can be produced by deposition, around the gate electrode 5, a layer having a thickness corresponding to the thickness of the conductive layer 4, followed by etching by means of a mask (not shown).
- FIG. 2 is shown the etching of the gate insulating layer 3 in the areas of the substrate 2 not covered by the gate electrode 5 and the insulator 6. This etching can be carried out using chlorinated mixtures and a technique of hot cathode type.
- the etching of the layer 1 of diamond carbon makes it possible to delimit the channel 7 laterally. To attack the diamond carbon, it is sufficient to oxidize it.
- a mixture of oxygen and argon can be used, serving as a carrier gas and making it possible to dilute the oxygen with a view to finely regulating the attack speed.
- Layer 1 of diamond carbon can be etched by anisotropic or isotropic etching, as shown in FIG. 3. By isotropic etching, we obtain a shrinkage 8 of layer 1 of diamond carbon under the insulating grid layer 3, preferably up to the gate electrode 5.
- the isotropic etching can be carried out by low energy oxygen plasma or by means of an oxygen flow directed onto the layer 1 of diamond carbon.
- Anisotropic etching can be carried out by reactive ion etching using an oxygen plasma.
- the substrate 2 can be densified by oxygen plasma at the end of the etching of the diamond carbon layer 1.
- FIG. 4 shows the deposition on the substrate 2, on either side of the channel 7, for example by epitaxy, of a semiconductor material 9a and 9b intended to constitute the source and the drain respectively.
- An anisotropic etching of the semiconductor material 9a and 9b in the areas of the substrate 2 not covered by the gate electrode and the lateral insulator 6 makes it possible to delimit the semiconductor material 9a and 9b laterally and to form the source 10 and the drain 11, as shown in FIG. 5.
- the etching of the semiconductor material makes it possible in particular to obtain a small transistor.
- the fabrication of the transistor ends with the formation of contact elements connected to the source 10 and to the drain 11, by depositing a metal 12 on the substrate 2, planarization, for example by chemical-mechanical route, and etching of the metal. 12.
- the source 10 and the drain 11 can be made of different materials.
- the materials 9a and 9b can then be anisotropically etched to delimit the source 10 and the drain 11 respectively, as previously.
- the semiconductor material 9a can, for example, be diamond, constituting the source 10 of an NMOS or PMOS type transistor.
- the semiconductor material 9b can, for example, be diamond, germanium, gallium arsenide or indium antimonide to constitute the drain 11 of an NMOS transistor, and diamond or germanium to constitute the drain 11 of a PMOS transistor.
- the method described above makes it possible in particular to automatically align the source and the drain with respect to the grid. This avoids the formation of parasitic capacitances between drain and gate and between source and gate, which deteriorate the performances of the transistor.
- the assembly constituted by the gate electrode 5, the lateral insulator 6 and the corresponding part of the gate insulator 3, serves as a mask for etching the layer 1 of diamond carbon, so as to delimit the channel 7. Then , the source and the drain are positioned around the channel, at the same level, under said assembly.
- a PMOS transistor 13 and an NMOS transistor 14, constituting a CMOS type inverter, respectively comprise a source 10, a drain 11 and a gate electrode.
- Their gate electrodes 5 are connected to a common conductor 15.
- the PMOS and NMOS transistors have substantially the same dimensions, in particular their channel widths L are identical.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0403073A FR2868209B1 (fr) | 2004-03-25 | 2004-03-25 | Transistor a effet de champ a canal en carbone diamant |
PCT/FR2005/000717 WO2005093794A1 (fr) | 2004-03-25 | 2005-03-25 | Procede de realisation d’un transistor a effet de champ a canal en carbone diamant et transistor obtenu |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1728269A1 true EP1728269A1 (fr) | 2006-12-06 |
Family
ID=34944502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05744607A Withdrawn EP1728269A1 (fr) | 2004-03-25 | 2005-03-25 | Procede de realisation d"un transistor a effet de champ a canal en carbone diamant et transistor obtenu |
Country Status (5)
Country | Link |
---|---|
US (1) | US7553693B2 (fr) |
EP (1) | EP1728269A1 (fr) |
JP (1) | JP5107027B2 (fr) |
FR (1) | FR2868209B1 (fr) |
WO (1) | WO2005093794A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4817813B2 (ja) * | 2005-11-15 | 2011-11-16 | 株式会社神戸製鋼所 | ダイヤモンド半導体素子及びその製造方法 |
US7816240B2 (en) | 2006-02-23 | 2010-10-19 | Acorn Technologies, Inc. | Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) |
US8193032B2 (en) * | 2010-06-29 | 2012-06-05 | International Business Machines Corporation | Ultrathin spacer formation for carbon-based FET |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020164841A1 (en) * | 2001-05-03 | 2002-11-07 | International Business Machines Corporation | Soi transistor with polysilicon seed |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4090289A (en) * | 1976-08-18 | 1978-05-23 | International Business Machines Corporation | Method of fabrication for field effect transistors (FETs) having a common channel stopper and FET channel doping with the channel stopper doping self-aligned to the dielectric isolation between FETS |
GB8812235D0 (en) | 1988-05-24 | 1988-06-29 | Jones B L | Manufacturing electronic devices |
JP2670309B2 (ja) * | 1988-09-28 | 1997-10-29 | 株式会社東芝 | 半導体装置の製造方法 |
WO1990007796A1 (fr) * | 1989-01-03 | 1990-07-12 | Massachusetts Institute Of Technology | Production de films isolants sur du diamant |
JP2813023B2 (ja) * | 1990-03-13 | 1998-10-22 | 株式会社神戸製鋼所 | Mis型ダイヤモンド電界効果トランジスタ |
JPH0799318A (ja) * | 1993-09-28 | 1995-04-11 | Kobe Steel Ltd | ダイヤモンド薄膜電界効果トランジスタ及びその製造方法 |
JPH07142741A (ja) * | 1993-11-20 | 1995-06-02 | Ricoh Co Ltd | C−mos薄膜トランジスタおよびその作製方法 |
US5455432A (en) * | 1994-10-11 | 1995-10-03 | Kobe Steel Usa | Diamond semiconductor device with carbide interlayer |
JPH08213607A (ja) * | 1995-02-08 | 1996-08-20 | Ngk Insulators Ltd | 半導体装置およびその製造方法 |
FR2749977B1 (fr) * | 1996-06-14 | 1998-10-09 | Commissariat Energie Atomique | Transistor mos a puits quantique et procedes de fabrication de celui-ci |
JP3364119B2 (ja) * | 1996-09-02 | 2003-01-08 | 東京瓦斯株式会社 | 水素終端ダイヤモンドmisfetおよびその製造方法 |
US6013191A (en) * | 1997-10-27 | 2000-01-11 | Advanced Refractory Technologies, Inc. | Method of polishing CVD diamond films by oxygen plasma |
US6198114B1 (en) * | 1997-10-28 | 2001-03-06 | Stmicroelectronics, Inc. | Field effect transistor having dielectrically isolated sources and drains and method for making same |
KR20010080432A (ko) | 1998-11-12 | 2001-08-22 | 피터 엔. 데트킨 | 계단식 소스/드레인 접합을 갖는 전계 효과 트랜지스터 구조 |
US6573565B2 (en) * | 1999-07-28 | 2003-06-03 | International Business Machines Corporation | Method and structure for providing improved thermal conduction for silicon semiconductor devices |
FR2806832B1 (fr) * | 2000-03-22 | 2002-10-25 | Commissariat Energie Atomique | Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor |
JP4153984B2 (ja) * | 2000-09-01 | 2008-09-24 | 株式会社神戸製鋼所 | トランジスタ |
ATE449420T1 (de) * | 2001-08-09 | 2009-12-15 | Amberwave Systems Corp | Cmos bauelemente mit doppelter schicht |
US6492216B1 (en) * | 2002-02-07 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
JP3626734B2 (ja) * | 2002-03-11 | 2005-03-09 | 日本電気株式会社 | 薄膜半導体装置 |
US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
US7119417B2 (en) * | 2003-09-25 | 2006-10-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and fabrication method thereof |
US7598516B2 (en) * | 2005-01-07 | 2009-10-06 | International Business Machines Corporation | Self-aligned process for nanotube/nanowire FETs |
-
2004
- 2004-03-25 FR FR0403073A patent/FR2868209B1/fr not_active Expired - Fee Related
-
2005
- 2005-03-25 US US10/593,335 patent/US7553693B2/en not_active Expired - Fee Related
- 2005-03-25 WO PCT/FR2005/000717 patent/WO2005093794A1/fr not_active Application Discontinuation
- 2005-03-25 JP JP2007504450A patent/JP5107027B2/ja not_active Expired - Fee Related
- 2005-03-25 EP EP05744607A patent/EP1728269A1/fr not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020164841A1 (en) * | 2001-05-03 | 2002-11-07 | International Business Machines Corporation | Soi transistor with polysilicon seed |
Non-Patent Citations (3)
Title |
---|
M. YOSHIMOTO ET AL.: "Epitaxial diamond growth on sapphire in an oxidizing environment", NATURE, vol. 399, 27 May 1999 (1999-05-27), pages 340 - 342 * |
See also references of WO2005093794A1 * |
VESCAN A ET AL: "High-Temperature, High-Voltage Operation of Pulse-Doped Diamond MESFET", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 18, no. 5, 1 May 1997 (1997-05-01), XP011018247, ISSN: 0741-3106 * |
Also Published As
Publication number | Publication date |
---|---|
FR2868209A1 (fr) | 2005-09-30 |
JP2007531257A (ja) | 2007-11-01 |
US7553693B2 (en) | 2009-06-30 |
WO2005093794A1 (fr) | 2005-10-06 |
FR2868209B1 (fr) | 2006-06-16 |
US20070218600A1 (en) | 2007-09-20 |
JP5107027B2 (ja) | 2012-12-26 |
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