EP1192653A1 - Procede de gravure laterale par trous pour fabriquer des dispositifs semi-conducteurs - Google Patents
Procede de gravure laterale par trous pour fabriquer des dispositifs semi-conducteursInfo
- Publication number
- EP1192653A1 EP1192653A1 EP00946027A EP00946027A EP1192653A1 EP 1192653 A1 EP1192653 A1 EP 1192653A1 EP 00946027 A EP00946027 A EP 00946027A EP 00946027 A EP00946027 A EP 00946027A EP 1192653 A1 EP1192653 A1 EP 1192653A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- silicon
- layer
- germanium
- grid
- stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 title claims description 27
- 239000010703 silicon Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 15
- 229910000676 Si alloy Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 17
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 12
- 230000000712 assembly Effects 0.000 abstract description 2
- 238000000429 assembly Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000011800 void material Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 31
- 235000012239 silicon dioxide Nutrition 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- 229910045601 alloy Inorganic materials 0.000 description 12
- 239000000956 alloy Substances 0.000 description 12
- 238000002955 isolation Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 230000004913 activation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/515—Insulating materials associated therewith with cavities, e.g. containing a gas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Definitions
- the present invention relates to a method of lateral etching by holes for manufacturing semiconductor elements. It finds an interesting application in high performance CMOS semiconductor devices for rapid signal processing and / or low voltage / low power applications, and more particularly in MOS field effect transistors (MOSFET).
- MOSFET MOS field effect transistors
- MOSFETs of silicon on insulator (SOI) architecture One of the limiting factors of conventional solid architecture MOSFETs is the substrate effect which affects the performance of the transistor. This drawback is avoided in MOSFETs of silicon on insulator (SOI) architecture by separating the thin silicon film from the substrate by a buried layer of silicon oxide.
- SOI silicon on insulator
- semiconductor devices based on so-called "SON" architecture silicon on nothing
- SOI silicon on insulator
- predetermined minimum length of the channel region is understood to mean the shortest channel length usable in a device of given technology.
- the insulating cavity can be made of any suitable solid or gaseous dielectric material but is preferably a cavity filled with air.
- the manufacturing process of the semiconductor device comprises: - the formation on a top surface of a silicon substrate 1 of a layer of a selectively eliminable material which preferably ensures a continuity of mesh with the silicon substrate 1;
- the formation of the source and drain regions 5 and 6 is preferably done by an epitaxial growth of silicon then an ion implantation of dopants.
- the implantation is advantageously followed by annealing to make the dopants implanted in the source and drain regions 5 and 6 electrically active.
- the annealing is of short duration under high temperatures.
- the creation of the cavity 2 after formation of the grid 7 and before formation of the source and drain regions 5 and 6 has drawbacks in the case where it is desired to leave this cavity 2 filled with air. Indeed, the activation (annealing) of the source and drain regions 5 and 6 results in the exposure of the cavity 2 to high temperatures. Exposing air-filled cavities to high annealing temperatures can lead to deterioration of the cavities.
- the object of the present invention is to remedy the drawbacks of the aforementioned method by forming a cavity filled with air after activation of the source and drain regions 5 and 6.
- the present invention therefore relates to a method of manufacturing a semiconductor device with an SON structure (Silicon on
- the invention therefore proposes a method for manufacturing a semiconductor element with an SON structure comprising the following steps:
- the source and drain regions are first produced while the selectively eliminable layers of germanium or alloy of germanium and silicon are present. It is only after the source and drain regions have formed that the selectively eliminable material is etched through the hole to form the tunnel (s), ie a cavity or cavities filled with air.
- the etching of the hole consists in making at least one vertical hole passing through the grid, the thin layer of grid dielectric and the stack under the grid up to the layer lower of germanium or germanium and silicon alloy of the first set. It will be readily apparent to those skilled in the art that to the extent that the dimensions of the grid allow, several holes can be made through the grid.
- At least two vertical holes are etched each passing respectively through the source region and the drain region up to the layer of germanium or of germanium and silicon alloy of the first set.
- the source and drain regions can be formed by implantation of dopants which diffuse as far as part of the grid.
- spacers can be formed on two lateral and opposite sides of the grid.
- the production of such spacers is well known to those skilled in the art.
- the source and drain regions can be formed in a conventional manner by creating recesses in the stack and into the substrate along two opposite sides of the grid, filling the recesses by epitaxial growth of silicon then implantation of dopants.
- the source and drain regions are preferably produced by implanting dopants in the stack and as far as the substrate after the grid has been formed (flanked by spacers) and without creating the recesses.
- the implantation of dopants according to the invention is carried out in such a way that, by lateral diffusion, the doped zones (the source regions and drain) are underlying the spacers and part of the grid.
- the hole or holes which will be used for the lateral etching of the layer or layers of germanium or of germanium and silicon alloy can be produced by any conventional etching process such as, for example, anisotropic plasma etching.
- the selective lateral etching of the germanium or SiGe alloy layers can be carried out via the hole (s) using any conventional method such as plasma etching or by selective chemical attack using an oxidizing solution like this. is well known.
- the selective lateral etching of the layer (s) of germanium or of germanium and silicon alloy via a hole is controlled so as to form a tunnel (s) ) extending as far as the spacers, for example by adjusting parameters of the etching process, in particular the time and temperature of selective lateral etching.
- FIGS. 2 and 3 are schematic sectional views illustrating the main steps for implementing the method of manufacturing a device according to the invention, before etching the holes;
- FIGS. 4a, 4b and 4c are schematic sectional views of the main steps of an embodiment of the method of manufacturing a device according to the invention, with at least one hole through the grid;
- FIG. 5 is a simplified sectional view of a device produced according to the method of the invention illustrated by Figures 4a-4c, but with two holes etched in the grid;
- FIGS. 6a, 6b and 6c are schematic sectional views of the main steps of another embodiment of the method of manufacturing a device, with holes through the source and drain regions, according to l 'invention.
- the invention is not limited thereto, a description will now be given of the process for manufacturing a MOSFET transistor with an SON structure comprising two tunnels filled with air.
- FIG. 2 shows a silicon substrate 12, the upper part of which is surrounded by an isolation box 13 of cylindrical shape with rectangular section.
- a first assembly is formed, composed of a lower layer of an alloy of silicon and germanium SiGe 14 and an upper layer of silicon 15.
- a second set also composed of a lower layer of silicon-germanium alloy 16 and an upper layer of silicon 17.
- the silicon layers 15, 17 and of silicon-germanium alloy 14, 16 of the two sets are formed by selective epitaxy so as to ensure a transfer of the mesh continuity from the silicon substrate 12 to the consecutive layers of silicon 15, 17 and of the silicon-germanium alloy 14, 16.
- the stack thus formed completely covers the upper surface of the silicon substrate 12.
- the thin layer of silicon dioxide 18 does not cover the isolation box 13.
- the two secondary lateral sides are in a direction perpendicular to the two primary lateral sides P and P ', that is to say perpendicular to the plane of the section.
- a grid 19 of polycrystalline silicon is then formed on a central part of the thin layer of grid dielectric 18 along the primary lateral sides P and P ', and over the entire length of the thin layer of grid dielectric 18 along both sides secondary sides up to two sides of the isolation box 13.
- the grid 19 is flanked spacers 20, 21, for example made of silicon nitride Si 3 N 4 , on the two primary lateral sides P and P '.
- the source and drain regions 22, 23 are obtained by implanting dopants along the spacers 20, 21, in the layer of silicon dioxide 18, in the layers of silicon 15, 17 and of the silicon-germanium alloy. 14, 16 of the two assemblies and, optionally, in an upper part of the silicon substrate 12.
- the two source and drain regions diffuse laterally towards one another under the spacers without ever connecting.
- the region 12a under the gate not reached by the diffusion of the dopants is an active area.
- 12a consists of the stack of layers 14, 15, 16 and 17, all of them undoped.
- the implantation of dopants contains two stages:
- annealing or activating the source and drain regions, following the first, in which the device is annealed so as to allow a crystalline rearrangement of the implanted regions and to make the dopants (ions) electrically active .
- the annealing is of short duration under a high temperature of the order of 850 ° C. at most.
- the device is covered, on its upper part, with a layer 24 of a passivation material such as silicon dioxide.
- a vertical hole 25 is formed through the layer of silicon dioxide 24, the layer of polycrystalline silicon forming the grid 19, the layer of silicon dioxide 18 and through the active area, c that is to say the silicon layers 15, 17 and of the silicon-germanium alloy 14, 16 of the two sets up to an upper part of the silicon substrate 12.
- the hole 25 can be formed by anisotropic plasma etching .
- a selective lateral etching of the tunnels 26 and 27 is carried out in the respective layers of the silicon-germanium alloy 16 and 14 so that this etching extends laterally as far as the spacers.
- passivation is carried out internal of hole 25 and tunnels 26 and 27 by thermal oxidation.
- a thin layer of silicon dioxide is formed on the walls of the hole 25 and of the tunnels 26 and 27.
- the part of the undoped silicon layer 15 present in the active area constitutes the channel 29 of the transistor.
- the channel 29 is a layer in which the hole 25 is located.
- the thickness of the silicon layer 17 is such that the growth of the thin layer of gate dielectric 18 and the internal passivation of the hole 25 and of the tunnels 26 and 27 completely consume this silicon layer 17 at the tunnel 26.
- the thicknesses of the layers of the silicon-germanium alloy 14, 16 and the silicon dioxide 28 are such that the growth of the thin layer of gate dielectric 18 and the internal passivation of the hole 25 and of the tunnels 26 and 27 completely consume this silicon layer 17 at the tunnel 26.
- internal passivation material are such that the hole 25 and the tunnels 26, 27 are not blocked. However, they can be plugged with silicon dioxide 28 if necessary.
- FIG. 4c shows a transistor according to the invention in which two holes 25 and 31 have been made in the gate 19.
- the hole 31 is obtained in the same way as the hole 25 with creation of tunnels and internal passivation.
- the external passivation layer (silicon dioxide 24), the isolation box 13 as well as the spacers 20, 21 are not shown for reasons of simplification.
- FIGS. 4a and 4b have been obtained in a section plane in the direction AA- as illustrated in FIG. 4c.
- FIG. 4c also shows current lines 30 starting from the source region 22 and going towards the drain region 23 passing through the channel 29.
- FIG. 4c also shows the two primary lateral sides P and P 'and the two secondary lateral sides S and S '.
- Figure 5 is a simplified sectional view of a device obtained by the method illustrated in Figures 4a-4c in which the passivation layers (24, 28) are missing. The plane of the section is in a direction S-S 'passing through the holes 25 and 31 (FIG. 4c).
- FIGS. 6a, 6b and 6c show another embodiment in which, starting from the element of FIG. 3, that is to say once the external passivation (silicon dioxide 24) has been carried out, at least etching a hole 32 in the source region 22 and at least one hole 33 in the drain region 23 through the external passivation layer 24, the thin layer of gate dielectric 18 and the layers of silicon 15, 17 and of alloy silicon-germanium sets at least up to the layer of silicon-germanium alloy 14. The grid remains intact. Selective lateral etching is then carried out, through the holes 32 and 33, to eliminate the layers of silicon-germanium alloy 14, 16 and form tunnels 34 and 35.
- the external passivation silicon dioxide 24
- the etching of the layers of silicon-germanium alloy 16 and 14 can be performed by isotropic plasma or by wet etching using an oxidizing solution.
- an internal passivation of the walls of the tunnels 34, 35 is carried out (FIG. 6) with silicon dioxide 36 by thermal oxidation.
- the tunnels 34 and 35 can also be completely filled with silicon dioxide 36 or other dielectric material.
- Figure 6c shows a top view of such a device in which four holes are made. We also represented contacts
- the method thus described makes it possible to produce SON structures in which the tunnels are etched after the source and drain regions have been formed.
- the tunnels are therefore not subjected to high temperatures due to the activation of the source and drain regions.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9908248A FR2795554B1 (fr) | 1999-06-28 | 1999-06-28 | Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs |
FR9908248 | 1999-06-28 | ||
PCT/FR2000/001796 WO2001001477A1 (fr) | 1999-06-28 | 2000-06-27 | Procede de gravure laterale par trous pour fabriquer des dispositifs semi-conducteurs |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1192653A1 true EP1192653A1 (fr) | 2002-04-03 |
Family
ID=9547389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00946027A Withdrawn EP1192653A1 (fr) | 1999-06-28 | 2000-06-27 | Procede de gravure laterale par trous pour fabriquer des dispositifs semi-conducteurs |
Country Status (5)
Country | Link |
---|---|
US (1) | US6727186B1 (fr) |
EP (1) | EP1192653A1 (fr) |
FR (1) | FR2795554B1 (fr) |
TW (1) | TW451334B (fr) |
WO (1) | WO2001001477A1 (fr) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
FR2821483B1 (fr) * | 2001-02-28 | 2004-07-09 | St Microelectronics Sa | Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant |
FR2849269B1 (fr) | 2002-12-20 | 2005-07-29 | Soitec Silicon On Insulator | Procede de realisation de cavites dans une plaque de silicium |
ATE415703T1 (de) * | 2002-12-20 | 2008-12-15 | Soitec Silicon On Insulator | Herstellung von hohlräumen in einer siliziumscheibe |
US7078298B2 (en) * | 2003-05-20 | 2006-07-18 | Sharp Laboratories Of America, Inc. | Silicon-on-nothing fabrication process |
GB2412009B (en) * | 2004-03-11 | 2006-01-25 | Toshiba Research Europ Limited | A semiconductor device and method of its manufacture |
US7262084B2 (en) * | 2004-04-15 | 2007-08-28 | International Business Machines Corporation | Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom |
JP2005354024A (ja) * | 2004-05-11 | 2005-12-22 | Seiko Epson Corp | 半導体基板の製造方法および半導体装置の製造方法 |
FR2875947B1 (fr) * | 2004-09-30 | 2007-09-07 | Tracit Technologies | Nouvelle structure pour microelectronique et microsysteme et procede de realisation |
FR2876220B1 (fr) * | 2004-10-06 | 2007-09-28 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
FR2879820B1 (fr) * | 2004-12-16 | 2009-01-16 | Commissariat Energie Atomique | Modulateur a jonction capacitive, jonction capacitive et son procede de realisation |
JP2006278674A (ja) * | 2005-03-29 | 2006-10-12 | Nec Electronics Corp | 電界効果トランジスタとその製造方法、及び半導体装置 |
FR2884648B1 (fr) * | 2005-04-13 | 2007-09-07 | Commissariat Energie Atomique | Structure et procede de realisation d'un dispositif microelectronique dote d'un ou plusieurs fils quantiques aptes a former un canal ou plusieurs canaux de transistors |
FR2897982B1 (fr) | 2006-02-27 | 2008-07-11 | Tracit Technologies Sa | Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat |
WO2008087576A1 (fr) * | 2007-01-16 | 2008-07-24 | Nxp B.V. | Traitement d'un substrat semi-conducteur |
FR2923646A1 (fr) * | 2007-11-09 | 2009-05-15 | Commissariat Energie Atomique | Cellule memoire sram dotee de transistors a structure multi-canaux verticale |
DE102008011480B4 (de) * | 2008-02-27 | 2010-09-09 | Siemens Aktiengesellschaft | Trennsäulen-Einheit für einen Gaschromatograph und Verfahren zu ihrer Befüllung mit Trennpartikeln |
US8106468B2 (en) | 2008-06-20 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for fabricating silicon-on-nothing MOSFETs |
DE102008040597A1 (de) * | 2008-07-22 | 2010-01-28 | Robert Bosch Gmbh | Mikromechanisches Bauelement mit Rückvolumen |
US8159029B2 (en) * | 2008-10-22 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage device having reduced on-state resistance |
US9685456B2 (en) * | 2015-09-04 | 2017-06-20 | Stmicroelectronics, Inc. | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method |
DE102016119799B4 (de) * | 2016-10-18 | 2020-08-06 | Infineon Technologies Ag | Integrierte schaltung, die einen vergrabenen hohlraum enthält, und herstellungsverfahren |
JP6817895B2 (ja) * | 2017-05-24 | 2021-01-20 | 株式会社東芝 | 半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5153813A (en) * | 1991-10-31 | 1992-10-06 | International Business Machines Corporation | High area capacitor formation using dry etching |
JPH06120490A (ja) * | 1992-10-06 | 1994-04-28 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR0138317B1 (ko) * | 1994-08-31 | 1998-04-28 | 김광호 | 반도체장치 커패시터 제조방법 |
US5622882A (en) * | 1994-12-30 | 1997-04-22 | Lsi Logic Corporation | Method of making a CMOS dynamic random-access memory (DRAM) |
-
1999
- 1999-06-28 FR FR9908248A patent/FR2795554B1/fr not_active Expired - Fee Related
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2000
- 2000-06-27 US US10/019,340 patent/US6727186B1/en not_active Expired - Fee Related
- 2000-06-27 EP EP00946027A patent/EP1192653A1/fr not_active Withdrawn
- 2000-06-27 WO PCT/FR2000/001796 patent/WO2001001477A1/fr not_active Application Discontinuation
- 2000-09-11 TW TW089112696A patent/TW451334B/zh not_active IP Right Cessation
Non-Patent Citations (1)
Title |
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See references of WO0101477A1 * |
Also Published As
Publication number | Publication date |
---|---|
FR2795554A1 (fr) | 2000-12-29 |
FR2795554B1 (fr) | 2003-08-22 |
TW451334B (en) | 2001-08-21 |
US6727186B1 (en) | 2004-04-27 |
WO2001001477A1 (fr) | 2001-01-04 |
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