Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/1464—Back illuminated imager structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14643—Photodiode arrays; MOS imagers
  • H01L27/14645—Colour imagers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing

Definitions

• the invention relates mainly to the manufacture of color image sensors produced on a thinned silicon substrate.
• the thinning of the silicon on which the image sensor is made is a technique making it possible to improve the colorimetry by minimizing the interference between neighboring image points corresponding to different colors; the interference is reduced thanks to the fact that the colored filters which are used to separate the primary components of the light can be deposited on the rear face and not on the front face of a silicon wafer and they are therefore closer to the photosensitive areas formed in silicon; the front face is that on which the deposition and etching operations of the layers forming the essential part of the photodetector array and of its control circuits are made.
• a color image sensor on thinned silicon can be produced in the following manner: one starts from a semiconductor wafer (silicon in principle) on the front face of which masking operations, implantation of impurities are carried out , depositing various temporary or permanent composition layers, etchings of these layers, heat treatments, etc.
• the filters are placed below the photosensitive zones, opposite the insulating and conductive layers which are then on the other side of the photosensitive zones. This means that when using the sensor in a camera, the light will come from the rear side of the sensor, pass through the color filters and directly reach the photosensitive areas without having to pass through the stack of insulating and conductive layers. It is this proximity between the photosensitive zones and the color filters which ensures good colorimetry, provided that the thinning is very pronounced: the residual thickness of silicon after thinning is approximately 5 to 20 micrometers.
• the first problem is a problem of electrical contact between the outside of the sensor and the circuitry which has been etched on the front face of the semiconductor wafer, front face which is no longer accessible a once the semiconductor wafer has been transferred onto a transfer substrate; it is therefore necessary that manufacturing steps are provided to make this access possible despite the postponement operation and these manufacturing steps must be industrially economical and efficient;
• the second problem is a problem of alignment precision of the engravings which are made on the rear face with respect to the circuit patterns which may have been engraved, before this transfer operation, on the front face: the alignment of patterns on the successive layers of the same face is classic; aligning patterns on two different sides, one of which is no longer accessible, is a more difficult problem.
• the object of the present invention is to propose a manufacturing method which makes it possible to provide a solution to these two problems at the same time.
• This method is particularly advantageously applicable to the manufacture of color image sensors, but it is more generally applicable to the manufacture of all kinds of electronic chips produced from thinned silicon wafers.
• a method of manufacturing electronic chips is proposed from a semiconductor wafer having on its face before a thin active layer of semiconductor material, this process comprising the production of etched layers on the active layer, the transfer of the wafer by its front face on a transfer substrate, the thinning of the semiconductor wafer by its rear face, then depositing and etching layers of material on the rear face thus thinned, process characterized in that narrow vertical trenches are dug in the wafer by its front face, before the transfer operation, these trenches extending to the inside the wafer to a depth approximately equal to the residual thickness of semiconductor wafer which will remain after the thinning operation, the trenches being filled with a conductive material isolated from the material of the active layer and constituting conductive vias between the front face and the rear face of the thinned edge.
• narrow vertical trenches is meant trenches with parallel vertical sides whose width is several times smaller than the depth and the length.
• filled with a conductive material is meant the fact that the conductive material is not only deposited on the walls of the trench but that it fills the open space during the construction of the trench.
• These vertical trenches which therefore extend approximately to the future rear face of the wafer, can also serve as optical alignment marks for the photo-engravings on the rear face; in fact, they are positioned precisely with respect to the front face patterns, they are vertical, and, thanks to the differences in optical index between the semiconductor material and the materials which constitute the conductive vias, they are visible on the rear face after thinning because they lead directly to this rear face or else they approach at a very short distance from this rear face.
• the trenches which serve as alignment marks are in principle non-functional with regard to the electronic circuitry: they are located outside this circuitry, or even sometimes outside the surface reserved for the chips on the wafer.
• trenches which have a functional role of establishing electrical connections between the front face and the rear face. It is during the same photogravure operation that the trenches intended to serve as marks are engraved on the one hand and the trenches on the other hand intended to serve as conductive vias, and the operations of isolating the walls of the trenches and filling the trenches are also simultaneous for the alignment marks and the functional vias used to establish contacts between front face and rear face.
• FIG. 1 represents a semiconductor wafer, in principle entirely made of silicon although this is not necessarily the case, on which a set of individual image sensor chips will be produced.
• the wafer will be cut into individual chips at the end of the manufacturing process.
• Each sensor comprises a rectangular matrix of photosensitive zones, and the associated circuits making it possible to collect the photogenerated charges in each pixel of the matrix and to establish an electronic signal representing the image received by the sensor.
• the sensor manufacturing technology is preferably but not necessarily a CMOS (Complementary Metal Oxide Semiconductor) technology.
• the semiconductor wafer of Figure 1 is preferably constituted by a silicon substrate 10, heavily p-type doped, on the front face of which is formed an epitaxial layer 12, also p-type but much less doped.
• the epitaxial layer is the active layer in which the photosensitive areas are formed.
• the substrate has a thickness of a few hundred micrometers and the epitaxial layer only about ten micrometers (preferably between 5 and 10 micrometers but possibly up to 30 micrometers). So general, the scales are not respected in the figures for greater readability.
• Manufacturing involves on the one hand various diffusions and implantations in silicon from the upper face or front face of the wafer, in particular to form the photosensitive zones, and on the other hand successive deposits and etchings of conductive and insulating layers . Before carrying out these deposits and etching of electrically functional layers, steps specific to the present invention will be carried out.
• FIG. 2 shows by way of illustration, four openings 20,
• openings 22 and 24 are intended to form electrical contacts
• aperture 26 furthest to the right can have other functions (insulation between different silicon zones). They are carried out in the same manufacturing step.
• the openings are in principle in the form of narrow vertical trenches, that is to say essentially deeper than wide. The narrowness is necessary insofar as it will be seen that these trenches are filled later and that it is easier to fill a narrow trench than a wide opening.
• the width of the trench is for example of the order of 1 to 4 micrometers for a depth of 5 to 30 micrometers.
• the length of the trenches depends on the function of the trenches; it can typically be several tens of micrometers as required, either in terms of optical visibility (for alignment marks), either in terms of the need for contact surface (for contact openings).
• the depth of the trenches is equal to the depth of the epitaxial layer, or slightly higher or slightly lower.
• the trenches are shown as having exactly the depth of the epitaxial layer.
• the formation of the trenches at the desired location is preferably done by surface oxidation of the epitaxial layer, therefore creation of an oxide layer 27 then masking with a resin, photogravure of the resin, etching of the silicon oxide in the openings of the resin, elimination of the resin, and etching of the silicon by anisotropic reactive ion etching where the silicon is not protected by the oxide.
• the preferred solution (FIG. 3) then consists first of all in surface oxidation of the wafer so as to cover its surface and the walls of the trenches with a thin film (a few tens of nanometers thick) of insulating silicon oxide 28, then to deposit a highly doped polycrystal ⁇ n 30 silicon, therefore conductive.
• the deposit fills the narrow trenches and covers the surface of the wafer. Silicon doped polycrystalline is then eliminated over a vertical thickness which corresponds to the thickness deposited on the wafer.
• the silicon remains in the trenches ( Figure 4) and constitutes conductive vias 20 '22', 24 ', 26' between the front face of the active epitaxial layer 12 and the rear face of this layer.
• These vias will effectively have a function of conducting vias for establishing electrical contacts with regard to the openings 22 and 24 but not necessarily with regard to the openings 20 and 26.
• the steps of manufacturing the image sensor are then carried out. proper with its associated circuits, that is to say the doping stages, the implantations in the epitaxial layer, the heat treatments, the deposits of conductive and insulating layers, the photogravures necessary each time, etc. We will not go into the details of this manufacture which is now classic. FIG.
• insulating layer 31 which covers the surface of the wafer and which is open locally to ensure contacts, in particular above the conductive vias 22 'and 24';
• a conductive layer 32 of highly doped polycrystalline metal or silicon, which serves to establish interconnections in the circuit and which comes in particular, through the insulating layer 31, with the conductive vias 22 'and 24';
• a layer 34 a stack of multiple insulating and conductive layers photo-etched according to the appropriate patterns to constitute the sensor and its associated circuits.
• the trenches 20, filled with polycrystalline silicon 30 isolated by the insulating layer 28 and transformed into vias 20 ′ serve as optical alignment marks for the photogravure operations which follow the realization of these trenches. All the etching patterns made by the front face of the semiconductor wafer are therefore gradually aligned one on the other, taking the initial trenches 20 as an initial reference.
• the conductive vias 20 ′ are visible due to the differences in index between the silicon materials , polycrystalline silicon, and silicon oxide which compose them.
• the end of the deposition and etching process of the layers on the front face in principle comprises a planarization step, that is to say a layer deposition step which bridges the differences in level of relief due to the successive steps of deposition and of engraving.
• the upper part of the layer 34 is a flat surface, for example produced using a deposit of silicon oxide or planarizing polyimide.
• the processing of the front face of the semiconductor wafer is now complete.
• the wafer is then transferred onto a transfer substrate 40 (FIG. 6).
• This transfer is made by the front face of the wafer, that is to say that it is the planarized front face which is bonded to a flat face of the transfer substrate.
• the wafer 10 with its epitaxial layer 12 and its photo-etched layers 34 is therefore shown turned upside down, front face down, in FIG. 6 and the following figures.
• the transfer of the silicon wafer can be done by several means, the simplest means being bonding by molecular adhesion, the great flatness of the surfaces in contact generating very high contact forces. Bonding with bonding material is also possible.
• the optical marks formed by the bottom flush with vias 20 ′ formed in the trenches 20 This bottom is visible even if there remains a thin layer of insulator 28; it would be visible even if a thickness of 1 or 2 micrometers of epitaxial silicon remained between the bottom of the via and the rear face of the wafer.
• the optical marks thus formed are well positioned relative to the patterns on the front face since the trenches are vertical.
• an insulating layer 42 (FIG. 8) open locally at the location of the vias 22 'and 24'.
• this insulating layer When this insulating layer is opened, the insulating bottom of the vias is also opened (layer 28). If the trenches were dug to a depth slightly less than that of the epitaxial layer, additional steps of etching the epitaxial layer would be provided to complete the formation of the conductive vias.
• conductive layer 44 preferably metallic (aluminum in particular) which will be used in particular to form interconnections and to form contact pads intended to ensure the connection with the outside of the chip after the end of manufacture.
• this layer can also serve as a masking layer to protect from light the sensor areas (inside the pixel matrix or in the peripheral circuits) which, due to the fact that silicon is inherently photosensitive, can be disturbed by light.
• This interconnection layer 44 has been shown not only in the form of a contact pad 44 'which comes into direct contact with the vias 22' and 24 ', but also in the form of periodic patterns 44 "for masking inside. an area corresponding to the pixel matrix of the image sensor (left part of FIG. 8).
• the contact pad 44 ′ may serve as a solder pad for a wired connection, or else be connected by an interconnection of layer 44 has a wire connection solder pad located not above vias 22 'and 24' but at another location (the pads are in principle at the periphery of the chip); it is however easier to plan that the solder pads are located directly above the vias which are then at the periphery of the chip.
• the deposition and etching operations on the rear face include in particular the deposit and successive engraving of tr three layers of filters colors arranged in a matrix to define juxtaposed pixels corresponding to the primary colors of light.
• the process for depositing the colored filters is as follows: depositing a first planarization layer 46 above the entire rear face of the wafer. Filing and photoengraving of a first color of filters, then a second and then a third. These filter layers are symbolized in FIG. 9 by a layer 48 above an area considered to be the image taking area of the sensor. Figure 10 shows the completed section.
• the filter layer depositing a first planarization layer 46 above the entire rear face of the wafer. Filing and photoengraving of a first color of filters, then a second and then a third.
• FIGS. 11 and 12 show a detail of an external connection contact pad 44 ′ connected by conductive vias to a conductive area 32 which was produced during the manufacturing steps, before transfer to the substrate 40, on the front side of the edge.
• the pad is constituted by a rectangular surface which covers two groups of trenches: the first group is constituted by a series of parallel trenches made up of conductive vias 22 'which all come into contact at the bottom with the zone 32 and at the top with the pad 44 '; the second group is an insulation trench 26 'which surrounds the entire epitaxial layer zone located under the external connection pad 44'.
• This isolation trench is constituted exactly like the conductive vias 22 'but it is not connected to an upper conductor and a lower conductor. Its function is to electrically isolate from the rest of the epitaxial layer the entire epitaxial layer zone located under the contact pad 44 '.
• Such isolation trenches could be provided to electrically isolate from each other different epitaxial layer zones.
• a trench could isolate from the rest of the layer both a contact pad and an amplifier whose pad constitutes the output.
• the width of the trenches is here about 1 micrometer
• the thickness of the epitaxial layer therefore the depth of the trenches is about 6 micrometers
• the lateral dimensions of the stud are of the order of 100 micrometers.
• a layer of thermal silicon oxide 52 to show that the steps performed on the front face can of course include conventional thermal oxidation steps.
• An important variant of the invention can be envisaged. In fact, in what has just been described, it is considered that the image sensor chip finally produced has contact pads on the face which receives light, the face which has been called the rear face of the semiconductor wafer. .
• the wafer is again glued to another transfer substrate 60, transparent, made of glass or quartz. Light then arrives through this glass or quartz substrate.
• the transfer substrate 40 becomes superfluous, the glass or quartz substrate ensuring the mechanical strength of the wafer.
• the transfer substrate 40 is then removed or removed, by mechanical and / or chemical machining, until the upper part of the set of layers 34 is flush or almost flush.
• These layers comprise in particular interconnection layers and they may in particular comprise a final metal layer comprising contact pads for soldering connection wires. In this case, it is not the pads 44 'which are used for contact with the outside since they are no longer accessible because of the glass or quartz transfer substrate. However, these are the studs of the assembly 34.
• FIG. 13 represents the constitution of a sensor chip thus produced, on which appear, in addition to the elements already mentioned with reference to FIGS.
• the transparent substrate 60 an external solder pad 62, connected through the layers of the assembly 34 to the conductive layer 32 and therefore to the layer 44, and a passivation and protection layer 64 open at the location of the pad 62.
• the pad 62 is produced at the end of the step shown in FIG. 5 .

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
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• 2003
  • 2003-12-12 FR FR0314595A patent/FR2863773B1/fr not_active Expired - Fee Related
• 2004
  • 2004-11-18 EP EP04820955A patent/EP1700343A1/fr not_active Withdrawn
  • 2004-11-18 JP JP2006543528A patent/JP4863214B2/ja not_active Expired - Fee Related
  • 2004-11-18 WO PCT/EP2004/053003 patent/WO2005067054A1/fr active Application Filing
  • 2004-11-18 CA CA002546310A patent/CA2546310A1/fr not_active Abandoned
  • 2004-11-18 US US10/582,711 patent/US20070166956A1/en not_active Abandoned
  • 2004-11-18 CN CNA2004800370925A patent/CN1894797A/zh active Pending

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