EP1680812A2 - Halbleiterchip mit flip-chip-kontakten und verfahren zur herstellung desselben - Google Patents
Halbleiterchip mit flip-chip-kontakten und verfahren zur herstellung desselbenInfo
- Publication number
- EP1680812A2 EP1680812A2 EP04802671A EP04802671A EP1680812A2 EP 1680812 A2 EP1680812 A2 EP 1680812A2 EP 04802671 A EP04802671 A EP 04802671A EP 04802671 A EP04802671 A EP 04802671A EP 1680812 A2 EP1680812 A2 EP 1680812A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor
- chip
- semiconductor chip
- flip
- contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 173
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000008719 thickening Effects 0.000 claims abstract description 67
- 238000002161 passivation Methods 0.000 claims abstract description 43
- 239000004033 plastic Substances 0.000 claims description 30
- 229920003023 plastic Polymers 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 29
- 230000008901 benefit Effects 0.000 claims description 24
- 238000001465 metallisation Methods 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 20
- 239000011324 bead Substances 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 3
- 241001465754 Metazoa Species 0.000 claims 1
- 230000032798 delamination Effects 0.000 abstract description 13
- 238000012856 packing Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 14
- 230000000694 effects Effects 0.000 description 12
- 239000002184 metal Substances 0.000 description 8
- 238000004873 anchoring Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- GLGNXYJARSMNGJ-VKTIVEEGSA-N (1s,2s,3r,4r)-3-[[5-chloro-2-[(1-ethyl-6-methoxy-2-oxo-4,5-dihydro-3h-1-benzazepin-7-yl)amino]pyrimidin-4-yl]amino]bicyclo[2.2.1]hept-5-ene-2-carboxamide Chemical compound CCN1C(=O)CCCC2=C(OC)C(NC=3N=C(C(=CN=3)Cl)N[C@H]3[C@H]([C@@]4([H])C[C@@]3(C=C4)[H])C(N)=O)=CC=C21 GLGNXYJARSMNGJ-VKTIVEEGSA-N 0.000 description 3
- 229940125758 compound 15 Drugs 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229920002430 Fibre-reinforced plastic Polymers 0.000 description 1
- 206010027146 Melanoderma Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 1
- 241000482268 Zea mays subsp. mays Species 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011151 fibre-reinforced plastic Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000007142 ring opening reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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Definitions
- the invention relates to a semiconductor chip with flip-chip contacts, the flip-chip contacts being arranged on contact areas on the active top side of the semiconductor chip.
- the contact areas are surrounded by a passivation layer, which protects the uppermost metallization layer and only releases the contact areas for attaching flip-chip contacts.
- Such semiconductor chips have the disadvantage that after application to a circuit carrier, in particular both after the flip-chip contacts have been soldered onto contact pads of the circuit carrier and after the gap between the semiconductor chip and circuit carrier has been filled with a filled plastic compound, there is an increased risk of microcracking the solder connections and an increased
- the object of the invention is to provide a semiconductor chip in which the risk of delamination is avoided despite the formation of bubbles and cracks and the rejection rate after soldering onto a circuit carrier and after introduction of a plastic compound is reduced.
- a semiconductor chip with flip-chip contacts is created, the flip-chip contacts being arranged on contact areas on the active upper side of the semiconductor chip.
- the contact areas are surrounded by a passivation layer, which covers the active upper side while leaving the contact areas free.
- This passivation layer has thickenings that surround the contact areas.
- Such a semiconductor chip with thickenings in the passivation layer around the contact areas has the advantage that if cracks form in the interface between the passivation layer and the plastic compound to be introduced when the semiconductor chip is attached to a circuit carrier, the thickening path in this interface is extended. This removes the energy from crack propagation before complete delamination can occur.
- the thickening has the advantage that micropores are deliberately formed at the edges of the thickening, especially since the plastic mass is not able to completely fill a minimal distance between the contact surface with flip-chip contact and the thickening, so that micropores of this type, which form around the flip-chip contact in the region of the thickenings, exert a stop effect on micro-crack propagation.
- the topographical structure which form such thickenings around the contact areas, and thus around the flip-chip contacts, at the same time increases the adhesion area of the passivation layer with respect to the plastic mass, so that an additional anchoring effect between the semiconductor chip and the plastic mass is caused by the thickenings is achieved around the contact surfaces of the semiconductor chip.
- the thickenings can have the material of the passivation layer and a metallic bead.
- This metallic bead can be designed in the form of a conductor track ring around the contact surface, the ring being designed to be open when a conductor track leads to the metal contact surface.
- the metallic bead in the form of a conductor track ring can be structured with the uppermost metallization layer of the semiconductor chip.
- the ring opening is dimensioned so large that the conductor track leading to the contact area does not touch the metallic ring that forms the bead.
- the thickness of the metallic bead corresponds to the thickness of the uppermost metallization structure of the semiconductor chip.
- This construction of a thickening from the material of the passivation layer and a metallic bead has the advantage that no additional method steps are required to form such a thickening of the passivation layer. Rather, this thickening occurs automatically when the passivation layer is applied to the active top side of the semiconductor chip while leaving the contact areas free.
- the advantageous effects of these thickenings in such a way that delamination of the semiconductor chip during assembly or after assembly on the circuit carrier is prevented, regardless of whether the thickening consists of passivation layer material or metal material.
- the invention has the additional advantage that no additional process steps are required to form such thickenings around the contact areas.
- the metallic bead is arranged in the form of a metallic line to form the thickening on the passivation layer.
- This embodiment of the invention has the advantage that the metallic bead can form a closed ring as a thickening around the contact areas, since the passivation layer is an insulation to the conductor tracks that lead to the contact areas.
- Another advantage of this construction is that such metallic beads can be formed from metal rings around a contact surface with sharp edges, which increases the probability of micropores forming around a chip contact, so that crack propagation within the plastic mass is stopped.
- the effect of the thickening around a contact area can also be improved if several closed or open circular rings are formed around a contact area.
- the anchoring effect is also reinforced with several rings.
- the thickenings around a contact spot can be introduced in a targeted manner where the risk of delamination is greatest.
- Thickenings that have a polygonal, circularly curved zigzag structure have the advantage that, on the one hand, they prevent the formation of micropores. Promote interruption of crack propagation and, on the other hand, enable better anchoring compared to ring-shaped thickenings.
- Another aspect of the invention relates to a semiconductor wafer which has semiconductor chip positions arranged in rows and columns, which in turn have contact areas which are surrounded by a passivation layer which has thickenings around the contact areas.
- a semiconductor wafer of this type has the advantage that several semiconductor chips with thickenings around their contact surfaces are prepared simultaneously in the parallel process.
- flip-chip contacts can also be applied to the semiconductor wafer in the individual component positions on the contact surfaces, so that individual semiconductor chips according to the invention are present after the semiconductor wafer has been opened.
- Another aspect of the invention relates to semiconductor components which have semiconductor chips according to the invention.
- Such semiconductor components have the advantage that delamination of their semiconductor chips with flip-chip contacts from a circuit carrier arranged underneath is prevented by the special design of the semiconductor chips according to the invention.
- the semiconductor component has a plastic mass which is filled with particles and has the micropores of a few ⁇ m in diameter at the thickenings which surround the flip-chip contacts of the semiconductor chip.
- Such a semiconductor component is advantageously protected against delamination in the interface between the semiconductor material and the plastic compound.
- the de-laminating of individual flip-chip contacts is largely prevented, since micro-cracks are prevented from spreading by the micropores surrounding the flip-chip contact.
- Such a semiconductor component has a circuit carrier in addition to the semiconductor chip.
- This circuit carrier in turn has contact pads of a rewiring tion structure, wherein the flip-chip contacts of the semiconductor chip are attached to the contact connection surfaces.
- the space between the active top side of the semiconductor chip and the circuit carrier has the particle-filled plastic mass with the micropores on the thickened portions.
- Such a circuit carrier can have a plurality of surface-mounted semiconductor chips and form a semiconductor module.
- the invention in particular the advantageous effect of the thickening of the passivation layer around the contact areas, it is not necessary for the entire semiconductor chip to be embedded in a plastic mass on the circuit carrier. Rather, the invention
- Another aspect of the invention relates to a benefit which has component positions arranged in rows and columns with semiconductor components according to the invention.
- the advantageous effect of the structure of semiconductor chips according to the invention also has a positive effect on the benefit, especially since such a benefit has several semiconductor components and due to the special type of structuring of the top side of the semiconductor chips, there is a risk of delamination of individuals Semiconductor chips reduced in their component positions.
- a method for producing a semiconductor wafer with semiconductor chip positions arranged in rows and columns has the following method steps.
- a semiconductor wafer with semiconductor chip positions is manufactured.
- the uppermost metallization layer is structured with conductor tracks and contact areas for flip-chip contacts, the contact areas being surrounded by ring-shaped structures which are not in contact with the conductor tracks or the contact areas.
- the top metallization layer is coated with a passivation layer made of oxides or nitrides, covering the ring-shaped structures and the conductor tracks, leaving the contact areas free. With this coating, thickening of the passivation layer arises due to the ring-shaped metal structures around the contact surfaces, which are congruent with the ring-shaped structures in the uppermost metal layer.
- Such a method has the advantage that it is completely compatible with the method for producing semiconductor wafers and corresponding semiconductor chip positions on the semiconductor wafers of semiconductor technology.
- the special structure according to the invention in each of the semiconductor chip positions, no additional method steps are required.
- the structuring mask for the production of the top metallization has to be adapted to the structure according to the invention.
- An alternative method for producing a semiconductor wafer with semiconductor chip positions arranged in rows and columns has the following method steps.
- a semiconductor wafer with semiconductor chip positions in rows and columns is first produced and the uppermost metallization layer with contact areas for flip- Structured chip contacts.
- the top metallization layer is provided with a passivation layer made of oxides or nitrides, covering the conductor tracks and leaving the contact areas free.
- a further metallization is then applied and structured on the passivation layer to form closed circular or polygonal closed structures around the contact areas.
- the thickenings on the passivation layer consist of a metal alloy in the uppermost region.
- a method for producing a panel with a plurality of semiconductor component positions has the following method steps.
- a semiconductor chip according to the invention is manufactured using one of the manufacturing methods for a wafer.
- a circuit carrier with a plurality of semiconductor component positions can be produced in parallel, the circuit carrier having on its upper side in the semiconductor positions rewiring structures with contact connection areas for flip-chip contacts.
- the rewiring structure of the circuit carrier has rewiring lines to through contacts.
- a further rewiring structure is applied to the back of the circuit carrier, which leads to external contact areas of semiconductor components in the semiconductor positions.
- This method of producing a benefit has two advantages; on the one hand, several process steps are used simultaneously for several semiconductor components and, on the other hand, component external contacts can be applied to the back of the circuit carrier, which can be much larger than the flip-chip contacts of the semiconductor chip, since the circuit carrier is of any size for such a use and that so-called "foot print" of the customer can be customized.
- To produce semiconductor components from such a benefit only the method step of separating the benefit into individual semiconductor components is required.
- These special structures can be metal lines around the contact areas of the flip-chip contacts and can be produced with the uppermost metallization step of the semiconductor chip or additionally by adding a further structured metallization.
- the construction of these metal lines around the contact surfaces can be ring-shaped, serpentine-like, meandering or zigzag-shaped. The more complex the topographical structure, the more the reliability of the semiconductor components which are produced with such chips is improved.
- micropores along the edges of the thickened areas or around the contact areas, the micro- This is due to the fact that the distance between the thickened areas and the contact surfaces cannot be completely filled by the plastic mass filled with particles.
- the micropores act as microcrack stop areas and prevent further spreading of the microcracks and thus delamination.
- FIG. 1 shows a schematic cross section through a partial region of a semiconductor chip with a transition region from the semiconductor chip to a flip-chip contact
- FIG. 2 shows a schematic cross section through a semiconductor component with a semiconductor chip and with a circuit carrier
- FIG. 3 shows a schematic top view of a thickening structure of a first embodiment of the invention
- FIG. 4 shows a schematic top view of a thickening structure of a second embodiment of the invention
- FIG. 5 shows a schematic top view of a thickening structure of a third embodiment of the invention.
- FIG. 1 shows a schematic cross section through a partial area of a semiconductor chip 1, in the transition area from the semiconductor chip 1 to a flip-chip contact 2.
- the semiconductor chip 1 has a contact area 3 on its active top side 4, which is provided with a solderable coating 29 is coated and on which a flip-chip contact 2 is arranged.
- a passivation layer 5 is arranged around the contact area 3 and in some cases also on the edge areas 34 of the contact area 3, leaving a central area of the contact area 3 which is covered with the solderable coating 29.
- An open circular structure 10 is covered by the passivation layer 5, so that there is a thickening 6 of the passivation layer 5 over this open circular structure 10.
- the distance between the resulting thickening 6 and the edge region 34 of the contact surface 3 is so small that micropores 16 can form with a plastic compound 15 when filling the intermediate space 21 between the semiconductor chip 1 and a circuit carrier (not shown here).
- the thickness d of the open circular structure 10 corresponds to the thickness of the contact area 3, since the circular structure 10 in this embodiment of the invention, with the uppermost metallization layer, ie simultaneously with the formation and structuring of the contact area 3, on the active top side 4 of the semiconductor chip 1 is made.
- the plastic mass 15 is filled with particles 17, so that it is practically not possible to completely fill the minimal distance of a few micrometers between the thickening 6 and the edge region 34 of the contact surface 3 with plastic mass 15.
- Line 37 shows in principle a microcrack that has spread out in the boundary layer between passivation layer 5 and plastic compound 15, for example starting from a bubble (not shown). This microcrack is stopped at the micropore 16, which is illustrated by the black spot 38.
- FIG. 2 shows a schematic cross section through a semiconductor component 30 with a semiconductor chip 1 and with a circuit carrier 18.
- the advantages have the effect that delamination of the semiconductor chip 1 and the plastic mass 15 in the boundary region between the active top 4 of the semiconductor chip 1 and the plastic mass 15 is prevented.
- the semiconductor device ⁇ 1 30 shown here which represents an example of a surface-mounted halloconductor chip 1
- the semiconductor device ⁇ 1 30 shown here which represents an example of a surface-mounted halloconductor chip 1
- FIG. 2 shows that thickenings 6 are arranged around the flip-chip contacts 2 of the semiconductor chip 1, in which the active top side 4 of the semiconductor chip 1 is in one Plastic mass 15 is embedded. Cracking, as usually occurs in the critical boundary layer between the semiconductor chip 1 and the plastic compound 15, is absorbed energetically by the thickenings 6 of the semiconductor chip 1 or stopped by the formation of micropores in the thickenings, since the voltage peaks at the micropores are reduced.
- the semiconductor chip 1 is fixed on the circuit carrier 18 via the flip-chip contacts 2, in that the flip-chip contacts 2 are soldered onto corresponding contact connection areas 19 of the circuit carrier.
- the circuit carrier 18 is a fiber-reinforced plastic plate, which has a rewiring structure 20 on its upper side 23, the rewiring structure 20 having rewiring lines 24 which are electrically connected to through contacts 25 to the rear side 26 of the circuit carrier 18.
- a further rewiring structure 27 is arranged on the rear side 26 of the circuit carrier 18, which has rewiring lines 24, before the through contacts 25 connect to external contact areas 28, on which external contacts 9 of the semiconductor component 30 are arranged.
- the external contacts 9 of the semiconductor component 30 can be made substantially larger than the flip-chip contacts 2 of the semiconductor chip 1, especially since the circuit carrier 18 can be enlarged as desired in relation to the size of the semiconductor chip 1.
- Both the upper side 23 of the circuit carrier 18 and the rear side 26 are coated with solder resist layers 35 and 36, respectively, leaving the contact connection areas 19 and the outer contact surfaces 28 free, in order to electrically isolate the rewiring structures 20 and 27 and to protect them from damage.
- the solder resist layers 35 and 36 for the fact that the material of the flip-chip contacts 2 and. of the external contacts 9 does not spread out on the rewiring lines 24 when soldering.
- FIG. 3 shows a schematic top view of a thickening structure 31 of a first embodiment of the invention.
- the passivation layer is omitted to clarify the structure on the active top side 4 of the semiconductor chip. Only the top metallization layer 8 can be seen, which has a conductor track 12 and a contact area 3, which are electrically connected to one another. Arranged around the contact area 3 are two open circular structures 10 which do not touch the conductor track 12, the opening 11 in the open circular structures 10 ensuring that these do not make electrical contact with the conductor track 12.
- these structures 10 have the same thickness as the conductor track 12 and, after applying a passivation layer, for example made of silicon nitride or silicon oxide, to the active top side 4 of the semiconductor chip underneath
- FIG. 4 shows a schematic top view of a thickening structure 32 of a second embodiment of the invention.
- the thickening structure 32 consists of closed circular metal rings 13, which, however, only after a passivation layer 5 has been applied to the active top side of a semiconductor chip by means of a further metallization
- This closed circular structure which here comprises two rings, forms two rings 13 which have no opening and consequently one in each direction Prevent microcracks from spreading when a plastic compound is applied to these semiconductor chips.
- FIG. 5 shows a schematic top view of a thickening structure 33 of a third embodiment of the invention.
- This thickening structure 33 differs from the thickening structure 31 according to FIG. 3 in that it has a polygonal, circularly curved zigzag structure 14.
- the passivation layer is omitted in order to make the structure, both of the conductor track 12 and the contact area 3, and the polygonal circularly curved zigzag structure 14 visible.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10352349A DE10352349B4 (de) | 2003-11-06 | 2003-11-06 | Halbleiterchip mit Flip-Chip-Kontakten und Verfahren zur Herstellung desselben |
PCT/DE2004/002440 WO2005045931A2 (de) | 2003-11-06 | 2004-11-03 | Halbleiterchip mit flip-chip-kontakten und verfahren zur herstellung desselben |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1680812A2 true EP1680812A2 (de) | 2006-07-19 |
Family
ID=34559528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04802671A Withdrawn EP1680812A2 (de) | 2003-11-06 | 2004-11-03 | Halbleiterchip mit flip-chip-kontakten und verfahren zur herstellung desselben |
Country Status (4)
Country | Link |
---|---|
US (1) | US7768137B2 (de) |
EP (1) | EP1680812A2 (de) |
DE (1) | DE10352349B4 (de) |
WO (1) | WO2005045931A2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102005005749A1 (de) | 2005-02-07 | 2006-08-17 | Infineon Technologies Ag | Halbleiterbauteil mit oberflächenmontierbaren Aussenkontakten und Verfahren zur Herstellung desselben |
US20080169555A1 (en) * | 2007-01-16 | 2008-07-17 | Ati Technologies Ulc | Anchor structure for an integrated circuit |
JP2011146513A (ja) * | 2010-01-14 | 2011-07-28 | Renesas Electronics Corp | 半導体装置 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0312671B1 (de) | 1987-10-19 | 1993-01-27 | International Business Machines Corporation | Prädiktive Taktwiedergewinnungsschaltung |
JPH05226339A (ja) * | 1992-01-28 | 1993-09-03 | Nec Corp | 樹脂封止半導体装置 |
JP2546472B2 (ja) | 1992-09-28 | 1996-10-23 | 株式会社日立製作所 | 半導体装置 |
JP3353508B2 (ja) * | 1994-12-20 | 2002-12-03 | ソニー株式会社 | プリント配線板とこれを用いた電子装置 |
US6022792A (en) | 1996-03-13 | 2000-02-08 | Seiko Instruments, Inc. | Semiconductor dicing and assembling method |
US5874356A (en) * | 1997-02-28 | 1999-02-23 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method for forming zig-zag bordered openings in semiconductor structures |
JPH11233544A (ja) * | 1998-02-18 | 1999-08-27 | Matsushita Electron Corp | 半導体装置 |
US5943597A (en) * | 1998-06-15 | 1999-08-24 | Motorola, Inc. | Bumped semiconductor device having a trench for stress relief |
TW441050B (en) | 1999-04-16 | 2001-06-16 | Advanced Semiconductor Eng | Flip-chip packaging structure and instilling method |
US6313541B1 (en) | 1999-06-08 | 2001-11-06 | Winbond Electronics Corp. | Bone-pad with pad edge strengthening structure |
US6551916B2 (en) | 1999-06-08 | 2003-04-22 | Winbond Electronics Corp. | Bond-pad with pad edge strengthening structure |
JP3446826B2 (ja) | 2000-04-06 | 2003-09-16 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
DE10031204A1 (de) * | 2000-06-27 | 2002-01-17 | Infineon Technologies Ag | Systemträger für Halbleiterchips und elektronische Bauteile sowie Herstellungsverfahren für einen Systemträger und für elektronische Bauteile |
JP2002151551A (ja) * | 2000-11-10 | 2002-05-24 | Hitachi Ltd | フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法 |
US6459144B1 (en) * | 2001-03-02 | 2002-10-01 | Siliconware Precision Industries Co., Ltd. | Flip chip semiconductor package |
JP2002280401A (ja) * | 2001-03-21 | 2002-09-27 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6586843B2 (en) * | 2001-11-08 | 2003-07-01 | Intel Corporation | Integrated circuit device with covalently bonded connection structure |
JP2003158141A (ja) * | 2001-11-26 | 2003-05-30 | Shindo Denshi Kogyo Kk | 半導体装置 |
TW586207B (en) * | 2002-01-29 | 2004-05-01 | Via Tech Inc | Flip-chip die |
TWI291210B (en) * | 2002-09-10 | 2007-12-11 | Advanced Semiconductor Eng | Under-bump-metallurgy layer |
KR100659527B1 (ko) * | 2003-10-22 | 2006-12-20 | 삼성전자주식회사 | 3차원 범프 하부 금속층을 갖는 플립 칩 본딩용 반도체칩과 그 실장 구조 |
-
2003
- 2003-11-06 DE DE10352349A patent/DE10352349B4/de not_active Expired - Fee Related
-
2004
- 2004-11-03 EP EP04802671A patent/EP1680812A2/de not_active Withdrawn
- 2004-11-03 WO PCT/DE2004/002440 patent/WO2005045931A2/de active Search and Examination
-
2006
- 2006-05-08 US US11/429,433 patent/US7768137B2/en not_active Expired - Fee Related
Non-Patent Citations (2)
Title |
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None * |
See also references of WO2005045931A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2005045931A2 (de) | 2005-05-19 |
DE10352349A1 (de) | 2005-06-23 |
WO2005045931A3 (de) | 2005-08-11 |
DE10352349B4 (de) | 2006-11-16 |
US20060270163A1 (en) | 2006-11-30 |
US7768137B2 (en) | 2010-08-03 |
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