EP1678074A1 - Procede et dispositif pour assembler solidement, de maniere isolante et electroconductrice, des plaquettes de semiconducteurs traitees - Google Patents

Procede et dispositif pour assembler solidement, de maniere isolante et electroconductrice, des plaquettes de semiconducteurs traitees

Info

Publication number
EP1678074A1
EP1678074A1 EP04802660A EP04802660A EP1678074A1 EP 1678074 A1 EP1678074 A1 EP 1678074A1 EP 04802660 A EP04802660 A EP 04802660A EP 04802660 A EP04802660 A EP 04802660A EP 1678074 A1 EP1678074 A1 EP 1678074A1
Authority
EP
European Patent Office
Prior art keywords
glass
conductive
electrically
electrically conductive
disks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04802660A
Other languages
German (de)
English (en)
Inventor
Roy Knechtel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Publication of EP1678074A1 publication Critical patent/EP1678074A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/093—Conductive package seal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts

Definitions

  • the invention relates to a method for connecting processed semiconductor wafers by means of electrically conductive and electrically insulating structured connection intermediate layers. A pane arrangement that can be produced with the method is also affected.
  • connection of processed semiconductor wafers is used in the production of microelectronic and microelectromechanical systems in order to cover certain structures with a cap already in the wafer process. This step is necessary on the one hand to protect sensitive mechanical structures during subsequent processing steps or to actually encapsulate the individual elements, e.g. optical components to be made in the pane structure and thus to enable special structures.
  • Usual methods for connecting e.g. System and cover disks are anodic and direct bonding, as well as bonding using low-melting glass interlayers (glass frit bonding).
  • the mechanically or electrically active elements are usually located on the system disk.
  • the cover disk on the other hand, mostly serves only as a covering protection (cap) and has no or only little electrical structures according to the prior art.
  • the bonding methods listed above have the property that the wafers are not connected to one another in a conductive manner.
  • One reason for this is that the cover plate itself is not conductive (anodic bonding).
  • intermediate layers created during bonding are not conductive (bond oxide with direct bonding, intermediate glass layer with glass frit bonding).
  • An electrical connection of the entire cover is sometimes necessary in order to connect it to a certain potential, eg ground.
  • evaluation electrodes on the cover are necessary, which must be contacted to the system pane in order to enable wire bonding during the assembly and connection process on one level.
  • the invention is based on the technical problem of designing a connection method in such a way that there is a firm and tightly sealed connection of at least two semiconductor wafers with simultaneous electrical connection of the wafers.
  • the combination of conductive and insulating glass structures in glass-frit bonding reaches areas of the cover plate in order to be electrically connected.
  • the invention is particularly suitable for microelectromechanical structures that are integrated with structures of the evaluation electronics.
  • more than two semiconductor wafers can be connected to one another in a stack. There are also middle areas in this stack, whereby the cover disk and the system disk can be present at the same time.
  • FIG. 1 is a system pane 1, which was connected to a cover pane 2 according to an example of a method, in a schematic sectional illustration along the line / plane A-A of FIG. 2.
  • FIG. 2 is a top view of an arrangement as shown in FIG. 1.
  • FIG. 3 is a variant of the conductive connection between the system pane and the cover pane.
  • FIG. 4 is a further variant of the conductive connection between the system pane and the cover pane analogous to FIG. 3.
  • low-melting structured insulating glass intermediate layers 6, 6a, 6b and the electrically conductive solder 5 based on glass (glass paste) connect the system pane 1 to the cover pane 2, while at the same time a selective contacting of the cover pane 2 to the system pane 1 or is produced between electrically active structures 3 of both disks (as a product) or is produced (as a method).
  • the application and premelting of the two glass solders 6, 5 can be carried out separately and in succession.
  • the first glass solder 6 is applied and premelted (as a structured layer), separated and the second glass solder 5 is applied and premelted at a distance therefrom.
  • the glass pastes are conditioned to the usual extent and extent, just like the common processes in semiconductor technology.
  • the conductive and non-conductive window connections are formed simultaneously.
  • the processing temperatures of the two glasses used are in the same range.
  • the mainly mechanically load-bearing pane connection 6, 6a, 6b can be realized using the one glass solder. Its thermal expansion is very well matched to that of silicon. The electrical contact areas must be kept small in order to minimize mechanical stress.
  • section line A is drawn, which, provided with a step, results in the section view of FIG. 1.
  • the cover 2 is shown only symbolically as a cover disk, actually removed, in order to be able to see the structures underneath.
  • the pane 2 is covered with a check pattern, is clearly assigned to FIG. 1 with regard to its edge regions and hides or covers the structure 3 to be protected, but at the same time leaves the hermetic seal and the mechanical support by the frame-shaped insulator layer (the structured layer 6a, 6b, 6) recognize.
  • the bond pads and the conductor tracks 4 can also be seen in this picture, outside and below the cover plate 2.
  • SOI panes 8 silicon-on-insulator
  • FIG. 3 it is possible to electrically connect the substrate 11 of the SOI pane via the conductive glass solder 5.
  • the active layer 9 of the SOI substrate and the buried oxide 10 have to be opened at the corresponding point, so that the electrically conductive glass solder 5 can flow into the opening and thus contact the carrier disk.
  • the semiconductor layer 9 is insulated on the hole walls.
  • An intermediate insulator 7, see FIG. 1, is not shown in FIG. 3. Since the current SOI-based technologies contain these sub-steps, there is no additional effort.
  • the intermediate insulator 7a is defined in terms of area within the opening which is occupied by the conductive glass solder 5, but which does not extend to the semiconductor layer 9 touching after one in particular cylindrical insulator layer 7a is provided, which on top of the semiconductor layer 9 can also have a peripheral edge, round, angular or otherwise shaped.
  • the conductor track 4 is only provided above this edge and the semiconductor layer 9.
  • the embodiment according to FIG. 4 is designed in the same way as that in FIG. 3, so that reference is made to the description there.
  • the glasses or glass pastes can also be applied in the reverse order or on the system pane 1, with correspondingly adapted further method steps, as shown above. LIST OF REFERENCE NUMBERS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)

Abstract

L'invention concerne un procédé et un dispositif pour assembler des plaquettes de semiconducteurs traitées (1,2), permettant de réaliser non seulement un assemblage solide, mais aussi une connexion électrique (5) entre les plaquettes de semiconducteur ou entre les structures électroniques (3) comportant ces dernières. Selon l'invention, l'assemblage solide est réalisé au moyen de couches intermédiaires en verre (6; 6a), structurées, à bas point de fusion, servant de couches isolantes, et la connexion électrique est réalisée au moyen d'un verre de scellement électroconducteur (5).
EP04802660A 2003-10-29 2004-10-29 Procede et dispositif pour assembler solidement, de maniere isolante et electroconductrice, des plaquettes de semiconducteurs traitees Withdrawn EP1678074A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10350460A DE10350460B4 (de) 2003-10-29 2003-10-29 Verfahren zur Herstellung von mikromechanische und/ oder mikroelektronische Strukturen aufweisenden Halbleiterbauelementen, die durch das feste Verbinden von mindestens zwei Halbleiterscheiben entstehen, und entsprechende Anordnung
PCT/DE2004/002413 WO2005042401A1 (fr) 2003-10-29 2004-10-29 Procede et dispositif pour assembler solidement, de maniere isolante et electroconductrice, des plaquettes de semiconducteurs traitees

Publications (1)

Publication Number Publication Date
EP1678074A1 true EP1678074A1 (fr) 2006-07-12

Family

ID=34529872

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04802660A Withdrawn EP1678074A1 (fr) 2003-10-29 2004-10-29 Procede et dispositif pour assembler solidement, de maniere isolante et electroconductrice, des plaquettes de semiconducteurs traitees

Country Status (7)

Country Link
US (1) US8129255B2 (fr)
EP (1) EP1678074A1 (fr)
JP (1) JP2007510295A (fr)
CN (1) CN1874956A (fr)
CA (1) CA2543736A1 (fr)
DE (2) DE10350460B4 (fr)
WO (1) WO2005042401A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7253495B2 (en) 2002-10-15 2007-08-07 Marvell World Trade Ltd. Integrated circuit package with air gap
US7791424B2 (en) * 2002-10-15 2010-09-07 Marvell World Trade Ltd. Crystal oscillator emulator
US7760039B2 (en) * 2002-10-15 2010-07-20 Marvell World Trade Ltd. Crystal oscillator emulator
US20060113639A1 (en) * 2002-10-15 2006-06-01 Sehat Sutardja Integrated circuit including silicon wafer with annealed glass paste
US7768360B2 (en) * 2002-10-15 2010-08-03 Marvell World Trade Ltd. Crystal oscillator emulator
DE102006040115A1 (de) * 2006-08-26 2008-03-20 X-Fab Semiconductor Foundries Ag Verfahren und Anordnung zur hermetisch dichten vertikalen elektrischen Durchkontaktierung von Deckscheiben der Mikrosystemtechnik
US8138062B2 (en) * 2009-12-15 2012-03-20 Freescale Semiconductor, Inc. Electrical coupling of wafer structures
EP3101805B1 (fr) * 2015-06-01 2019-04-03 Aros Electronics AB Réduction d'ondulation de bus cc

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DE3837300A1 (de) * 1988-11-03 1990-05-23 Messerschmitt Boelkow Blohm Verfahren zur herstellung von mikroelektronischen schaltungen und hybriden
US5094969A (en) * 1989-09-14 1992-03-10 Litton Systems, Inc. Method for making a stackable multilayer substrate for mounting integrated circuits
DE4006108A1 (de) * 1990-02-27 1991-08-29 Bosch Gmbh Robert Verfahren zum aufbau von mikromechanischen bauelementen in dickschichttechnik
US5164328A (en) * 1990-06-25 1992-11-17 Motorola, Inc. Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip
US5545912A (en) * 1994-10-27 1996-08-13 Motorola, Inc. Electronic device enclosure including a conductive cap and substrate
JP3514349B2 (ja) 1996-02-13 2004-03-31 株式会社日立国際電気 マイクロパッケージ構造
DE19616014B4 (de) 1996-04-23 2006-04-20 Robert Bosch Gmbh Verfahren zur Herstellung von mikromechanische Strukturen aufweisenden Halbleiterbauelementen
EP0877003B1 (fr) 1997-05-09 2002-09-18 JSR Corporation Composition de pâte de verre
EP0886144B1 (fr) 1997-06-19 2006-09-06 STMicroelectronics S.r.l. Capteur scellé hermétiquement avec microstructure mobile
GB9713831D0 (en) * 1997-06-30 1997-09-03 Fry Metals Inc Sealing glass paste for cathode ray tubes
US5955771A (en) * 1997-11-12 1999-09-21 Kulite Semiconductor Products, Inc. Sensors for use in high vibrational applications and methods for fabricating same
US6020646A (en) * 1997-12-05 2000-02-01 The Charles Stark Draper Laboratory, Inc. Intergrated circuit die assembly
JP3689598B2 (ja) * 1998-09-21 2005-08-31 キヤノン株式会社 スペーサの製造方法および前記スペーサを用いた画像形成装置の製造方法
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See references of WO2005042401A1 *

Also Published As

Publication number Publication date
DE112004002626D2 (de) 2006-09-21
CA2543736A1 (fr) 2005-05-12
DE10350460A1 (de) 2005-06-30
JP2007510295A (ja) 2007-04-19
US20080029878A1 (en) 2008-02-07
CN1874956A (zh) 2006-12-06
US8129255B2 (en) 2012-03-06
DE10350460B4 (de) 2006-07-13
WO2005042401A1 (fr) 2005-05-12

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