EP1642370B1 - Circuit de protection pour un dispositif a circuit integre - Google Patents

Circuit de protection pour un dispositif a circuit integre Download PDF

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Publication number
EP1642370B1
EP1642370B1 EP04744381A EP04744381A EP1642370B1 EP 1642370 B1 EP1642370 B1 EP 1642370B1 EP 04744381 A EP04744381 A EP 04744381A EP 04744381 A EP04744381 A EP 04744381A EP 1642370 B1 EP1642370 B1 EP 1642370B1
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EP
European Patent Office
Prior art keywords
transistor
protection circuit
pad
esd
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP04744381A
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German (de)
English (en)
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EP1642370A1 (fr
Inventor
Wolfgang Kemper
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NXP BV
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NXP BV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits

Definitions

  • the invention relates to an integrated circuit for protecting a circuit device from damage resulting from electrostatic discharge.
  • CMOS complementary metal oxide semiconductor
  • ESD electrostatic discharge
  • An ESD can have the consequence of a voltage breaking through a dielectric between two surfaces, in the end resulting in a short circuit, damaging the gate oxide/diffusion, the metal layers, or the contacts of the integrated circuit.
  • the electrostatic charge existing prior to the sudden discharge of the circuit usually results from contact with an electrostatically charged object, e. g. a person or a machine.
  • one or more specially designed protection circuits are usually integrated on the substrate of the circuit to be protected.
  • Such a protection circuit is activated when a dangerous current or voltage discharge occurs and switches into a low-impedance state to keep the sensitive areas of the circuit safeguarded.
  • the ESD protection circuits are one of several area-limiting devices, especially with regard to input/output (I/O) pads. It is thus advantageous or even necessary to reduce the chip area consumed by the protection circuit and still achieve sufficient protection. Furthermore, for high speed radio frequency (RF) I/O designs, the capacitance of the ESD protection circuit must be as low as possible, whereby the capacitance depends on the chip area used for the ESD protection.
  • I/O input/output
  • ESD protection usually relies on the breakthrough mechanism of the P-N junction of an ESD protection transistor. Curve 11 in the current voltage diagram in Fig. 1 illustrates this.
  • the limitation in ESD robustness consists in the fact that the ESD clamp has a differential resistance during an ESD event. The voltage drop during an ESD event reaches a value where the integrated circuit is no longer protected.
  • Typical failures are drain damages of small N-MOS transistors or gate oxide breakdowns.
  • an electrostatic discharge protection device having a modulated control input terminal is described.
  • the protection circuit guarding an associated integrated circuit from damage due to electrostatic discharge, includes a N-MOS transistor serving as clamping device and a gate modulation circuit.
  • the source and the drain of the N-MOS transistor clamp are connected between an input/output pad of the integrated circuit and a ground reference voltage.
  • the gate modulation circuit disables the N-MOS transistor clamp by connecting its gate terminal to a ground reference voltage.
  • the gate modulation circuit connects the gate to the input/output pad, which enables the N-MOS transistor clamp, causing any ESD voltages and resulting currents to be shunted through the N-MOS transistor clamp to ground.
  • EOS electrostatic overstress
  • the voltage caused by an ESD or electrostatic overstress cannot be shunted through the N- MOS transistor clamp to ground because the N-MOS transistor clamp is disabled. Therefore, in this case an ESD or electrostatic overstress can damage the gate oxide, the metal layers or the contacts of the integrated circuit.
  • US2003/0043523 describes an ESD protection circuit, arranged between a first and second potential terminals, comprises a RC branch, a voltage adjuster circuit, and an ESD discharge transistor.
  • the RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal.
  • the voltage adjuster circuit has a plurality of inputs connected to the RC branch, and the first and second potential terminals, and an output connected to a gate of the ESD discharge transistor to adjust the gate voltage thereof for obtaining a uniform turn on and optimal ESD robustness.
  • the voltage adjuster circuit mainly includes a plurality of transistors that enable to effectively adjust the gate voltage with respect to high level of ESD stress.
  • US 6,078,487 describes a circuit which protects an integrated circuit device from damage due to electrostatic discharge (ESD).
  • the protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit.
  • MOSFET metal oxide semiconductor field effect transistor
  • the source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage.
  • US 6,522,511 describes an electrostatic discharge (ESD) protection circuit for use in an integrated circuit including a transistor, an inverter, and an ESD detector.
  • the transistor is coupled to clamp a non-power supply pad of the integrated circuit to a power supply pad of the integrated circuit when an ESD event is detected.
  • the ESD detector is operably coupled to detect an ESD event on the non-power supply pad and to provide an indication of the ESD event to the inverter.
  • the inverter provides an amplified signal to the gate of the transistor such that the transistor is driven quickly into low impedance conduction.
  • An object of the invention is to provide an integrated protection circuit which protects an integrated circuit having a pad, e. g. an I/O pad or a power supply pad, from electrostatic discharge or electrostatic overstress during different stress conditions.
  • a pad e. g. an I/O pad or a power supply pad
  • chip area can be saved without diminishing the protection from electrostatic discharge or electrostatic overstress.
  • the protection from electrostatic discharge or electrostatic overstress can be improved considerably without consuming more chip area.
  • the integrated protection circuit according to the preamble of claim 1 comprises a first transistor whose control outputs are connected between the pad and the control input of a clamping device, wherein the control outputs of the clamping device are connected between the pad and a reference voltage terminal.
  • the protection circuit further comprises a second transistor whose control outputs are connected between one control output of the first transistor and the reference voltage terminal.
  • the protection circuit also includes a time-delay element connected between a supply voltage terminal and the control inputs of the first transistor and the second transistor.
  • the pad of the integrated protection circuit is a signal input/output pad or a power supply pad.
  • the time-delay element of the integrated protection circuit comprises a series connection of a resistor and a capacitance.
  • the time-delay element of the integrated protection circuit comprises a third transistor, wherein the resistor is connected between the supply voltage terminal and the third transistor, and wherein the third transistor forms the capacitance.
  • the integrated protection circuit comprises a fourth transistor whose control outputs are connected between the reference voltage terminal and the control output of the third transistor and wherein the control input of the fourth transistor is also connected to the reference voltage terminal.
  • the first transistor of the integrated protection circuit can be a p-channel MOS transistor.
  • the second, third and fourth transistor of the integrated protection circuit can be formed as n-channel MOS transistors.
  • the clamping device of the integrated protection circuit according to the invention is a n-channel MOS transistor layouted for ESD protection.
  • the clamping device of the integrated protection circuit according to the invention can be a parasitic npn transistor.
  • the clamping device of the integrated protection circuit according to the invention can also be formed as a thyristor.
  • the integrated protection circuit for protecting a circuit device can comprise a diode connected between the pad and the supply voltage terminal.
  • the idea of the invention is to have a robust element which handles the ESD current during an ESD event before more sensitive internal devices can be damaged.
  • Most common elements are diodes, N-MOS transistors and low-voltage-triggered silicone rectifiers (LVTSCR). All these devices have breakdown values higher than the operating voltage of the integrated circuitry which has to be protected.
  • Fig. 1 shows, beside the curve 11 illustrating the current voltage course for an ESD protection circuit according to the prior art, also a curve 12 illustrating the current voltage course for an ESD protection circuit according to the invention.
  • the ESD detection circuit clamps the voltage caused by the ESD event much earlier than a conventional ESD clamp.
  • the ESD test is carried out on a non operating integrated circuit (IC). During the ESD test any pulse, regardless of the voltage level, must be prevented. Therefore, it is not necessary to have an ESD protection with a trigger voltage higher than the operating voltage of the IC.
  • One idea of the invention is to clamp every pulse at the lowest possible voltage level. This is in common CMOS technology the threshold voltage Utr of a transistor, which is about 0.6V. During the normal operating mode of the IC this behavior is switched off and the protection circuit operates like a common voltage clamp.
  • a supply terminal 1 for a supply voltage VDD is connected over a resistor R to the drain and gate terminals of a first n-channel metal oxide field effect transistor (N-MOSFET) MNI.
  • the source terminal of the first N-MOS transistor NM1 is connected to the drain terminal of a second N-MOS transistor MN2.
  • the gate terminal and the source terminal in turn are connected at the reference voltage terminal 4 to a reference potential VSS, which is the ground of the complete circuit.
  • a p-channel MOS transistor MP1 and a third N-MOS transistor MN3 form an inverter INV whose input NET 1 is connected to the source of the first N-MOS transistor NM1 and the drain terminal of the second N-MOS transistor MN2.
  • the output NET2 of the inverter INV is connected to the gate terminal of a fourth N-MOS transistor NM4 which works as main clamp of the ESD protection circuit.
  • the part of the ESD protection circuit inside of the doted line is called in the following active trigger control AC, while the transistor MN4 is called clamp transistor.
  • the protection circuit shown in Fig. 1 can be brought in two different operating modes, a normal operating mode and an event driven mode. Both modes are explained in the following.
  • the supply terminal 1 of protection circuit is powered up and the ground terminal 4 is connected to ground.
  • the circuit is not stressed with ESD or EOS.
  • the protection circuit now operates as follows. At first, the first N-MOS transistor MN1 is turned on, this means it is conducting. Secondly, the second N-MOS transistor MN2 is turned off and gets nonconducting. Therefore, in the next step the input NET 1 of the inverter INV gets high and its output NET 2 low. Finally, the main clamp MN4 is switched off. The consequence is, that the I/O pad 2 is not connected to ground but can be used as I/O pad 2.
  • main clamp MN4 will act like a common used gate grounded NMOS transistor (GGNMOST) and will protect the complete circuit.
  • GGNMOST common used gate grounded NMOS transistor
  • the event driven mode there are four different operating conditions. In all operating conditions all nodes or pads of the circuit are floating during an ESD test except the pin to be tested and the corresponding grounded pin.
  • An I/O pad 2 shall be tested with a test voltage Vpad wherein the test voltage Vpad is positive versus the reference potential VSS.
  • the circuitry works as follows.
  • the supply voltage VDD at the supply terminal 1 is floating. Due to the capacitance formed by the gate and drain of the P-MOS transistor MP 1 the transistor MP1 of the inverter INV is conducting. Therefore, the voltage at the node NET2 follows the positive test voltage Vpad at the I/O pad 2.
  • the fourth N-MOS transistor MN4 is conducting and clamps the I/O pad 2 to the reference potential VSS.
  • the I/O pad 2 shall be tested with a test voltage Vpad2 wherein the test voltage Vpad2 is positive versus the supply potential VDD. Now, the supply terminal 1 is grounded and the reference potential VSS is floating
  • a parasitic diode can be for example a n-well diode of a PMOS transistor connected between the supply potential VSS and the reference potential VDD.
  • the I/O pad 2 shall be tested with a test voltage Vpad3 wherein the test voltage Vpad3 is negative versus the reference potential VSS.
  • the voltage VDD at the supply terminal 1 is grounded and the reference potential VSS is floating.
  • the clamp transistor MN4 is conducting and forces the ESD current to the substrate of the integrated circuit.
  • the parasitic N+ diode D2 leads the current towards the I/O pad 2.
  • N+/substrate diodes connected to the I/O pad 2 are driven in forward direction.
  • a N+/substrate diode can be for example a N+ transistor diffusion.
  • the ESD current flows from the reference node VSS to the I/O pad 2.
  • the I/O pad 2 shall be tested with a test voltage Vpad4 wherein the test voltage Vpad4 is negative versus the reference potential VSS.
  • the voltage VDD at the supply terminal 1 is floating and the reference potential VSS is grounded.
  • Either the optional diode D is forward BIASed or the transistor MP 1 will conduct as described in the 1th operating condition and clamp MN4 force the ESD current to ground. Thenafter as described in 3th operating condition the current will be forced via the parasitic diodes towards VDD.
  • the invention combines the robustness of the state of the art GGNMOST concept together with the advantage of an active clamping.
  • the protection circuit can also be used for protecting the power pin or power supply pad 3 against electrostatic discharge or electrostatic overstress.
  • the power supply pad 3 is connected to the drain terminal of the P- MOS transistor MP1, the drain terminal of the fourth N-MOS transistor MN4 and the resistor R of the protection circuit.
  • the protection circuit itself has not to be modified.
  • Fig. 4 shows a block diagram of the ESD protection circuit according to the invention used for an I/O pad.
  • the active trigger circuit AC controls the clamp transistor MN4.
  • Fig. 5 shows a block diagram of the ESD protection circuit according to the invention used for a power pad.
  • the active trigger circuit AC controls the clamp transistor MN4.
  • each kind ofN-MOS transistor clamp MN4 can be driven.
  • a N-MOS transistor layouted for protection against ESD can be used as transistor clamp NM4.
  • the pull down N-MOS transistor can be designed as a normal N-MOS transistor or as a N- MOS transistor with special ESD constrains.
  • Fig. 6 shows how a parasitic diode is arranged in the integrated circuit. In normal operating mode the parasitic diode or parasitic diodes respectively are nonconducting.
  • the dimension refers to the ratio channel width to channel length, wherein both are given in ⁇ m.
  • Element Dimension Description R 100 Ohm Protects the transistor MN1; MN1 3/0.34 Drives the node NET1 as fast as possible; MN2 3/0.34
  • close mode The node NET can easily rise the potential
  • In open mode Acts like the transistor MN1; MP1 8/0.34 Drives the node NET2 as fast as possible; MN3 1/0.34 Weak pull down;
  • In normal mode Pulls the node NET2 down;
  • In event driven mode Allows the node NET2 to drive up easy; MN4 100/0.34 Main clamp; Layout with ESD layout properties (i. e. siprot)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)

Claims (7)

  1. Circuit de protection intégré pour un dispositif à circuit intégré, comportant :
    - un premier transistor (MP1) dont les sorties de commande sont connectées entre un plot (2, 3) et une entrée de commande d'un dispositif de blocage (MN4),
    - les sorties de commande dudit dispositif de blocage (MN4) étant connectées entre ledit plot (2, 3) et une borne de tension de référence (4),
    - un deuxième transistor (MN3) dont les sorties de commande sont connectées entre la sortie de commande dudit premier transistor (MP1) et ladite borne de tension de référence (4), et
    - des moyens de temporisation (R, MN1) connectés entre une borne de tension d'alimentation (1) et les entrées de commande du premier transistor (MP1) et du deuxième transistor (MN3), comprenant une connexion en série d'une résistance R et d'une capacité, la résistance (R) étant connectée entre la borne de tension d'alimentation (1) et un dit troisième transistor (MN1), ledit troisième transistor (MN1) constituant la capacité,
    caractérisé par un quatrième transistor (MN2) dont les sorties de commande sont connectées entre la borne de tension de référence (4) et la sortie de commande du troisième transistor (MN1) et dont l'entrée de commande est connectée à ladite borne de tension de référence (4).
  2. Circuit de protection selon la revendication 1, dans lequel le premier transistor (MP1) est un transistor MOS à canal p.
  3. Circuit de protection selon l'une quelconque des revendications précédentes, dans lequel les deuxième, troisième et quatrième transistors (MN1, MN2, MN3) sont des transistors MOS à canal n.
  4. Circuit de protection selon l'une quelconque des revendications précédentes, dans lequel le dispositif de blocage (MN4) est un transistor MOS à canal n disposé pour une protection ESD.
  5. Circuit de protection selon l'une quelconque des revendications précédentes 1 à 3, dans lequel le dispositif de blocage (MN4) est un transistor npn parasite.
  6. Circuit de protection selon l'une quelconque des revendications précédentes 1 à 3, dans lequel le dispositif de blocage (MN4) est un thyristor.
  7. Circuit de protection selon l'une quelconque des revendications précédentes, dans lequel une diode (D) est connectée entre le plot (2) et la borne de tension d'alimentation (1).
EP04744381A 2003-06-30 2004-06-23 Circuit de protection pour un dispositif a circuit integre Expired - Lifetime EP1642370B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04744381A EP1642370B1 (fr) 2003-06-30 2004-06-23 Circuit de protection pour un dispositif a circuit integre

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03101950 2003-06-30
EP04744381A EP1642370B1 (fr) 2003-06-30 2004-06-23 Circuit de protection pour un dispositif a circuit integre
PCT/IB2004/050973 WO2005002019A1 (fr) 2003-06-30 2004-06-23 Circuit de protection pour un dispositif a circuit integre

Publications (2)

Publication Number Publication Date
EP1642370A1 EP1642370A1 (fr) 2006-04-05
EP1642370B1 true EP1642370B1 (fr) 2009-09-23

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EP04744381A Expired - Lifetime EP1642370B1 (fr) 2003-06-30 2004-06-23 Circuit de protection pour un dispositif a circuit integre

Country Status (7)

Country Link
US (1) US7787224B2 (fr)
EP (1) EP1642370B1 (fr)
JP (1) JP2007527188A (fr)
CN (1) CN100508322C (fr)
AT (1) ATE443937T1 (fr)
DE (1) DE602004023293D1 (fr)
WO (1) WO2005002019A1 (fr)

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KR20140129159A (ko) * 2012-02-15 2014-11-06 퀄컴 인코포레이티드 차동 입력/출력 인터페이스들에 대한 서지 보호
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CN104821312B (zh) * 2015-05-19 2017-12-15 中国兵器工业集团第二一四研究所苏州研发中心 一种开漏输出端口的esd保护电路
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Also Published As

Publication number Publication date
WO2005002019A1 (fr) 2005-01-06
CN1816955A (zh) 2006-08-09
ATE443937T1 (de) 2009-10-15
CN100508322C (zh) 2009-07-01
US7787224B2 (en) 2010-08-31
DE602004023293D1 (de) 2009-11-05
EP1642370A1 (fr) 2006-04-05
US20060268473A1 (en) 2006-11-30
JP2007527188A (ja) 2007-09-20

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