Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/90—Thermal treatments, e.g. annealing or sintering
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

• the present invention relates generally to the processing of wafers of materials intended for use in microelectronic, optical and optoelectronic applications.
• the invention thus relates to the wafers of materials chosen from semiconductor materials.
• the invention relates to a high temperature heat treatment (or annealing) process for a wafer made from one or more material (s) chosen from semiconductor materials and placed on a support, the process including a slow rise in temperature to a temperature at the end of treatment.
• a particularly advantageous application of the invention relates to a heat treatment for stabilizing a bonding interface.
• high temperature annealing is understood to mean annealing, at least certain phases of which take place at temperatures above a value of the order of 800 ° C.
• the high temperature anneals concerned by the invention thus typically involve temperatures of the order of 800 to 1200 ° C. These temperatures can in particular be temperatures at the end of treatment.
• slow rise in temperature is understood to mean a change in temperature in which the phase or phases of temperature progression takes place (or take place) according to a slope of at least 10 ° C./min.
• the wafers concerned by the invention can be monolayer wafers, or multilayer wafers (for example of the SOI type - for Silicon On Insulator; Silicium Sur Isolant in French).
• the different layers of the wafer can be combined together by bonding.
• bonding is understood to mean the intimate contact of two surfaces, in order to establish between these two surfaces bonds of the hydrogen bond type or of Van der Waals.
• Such bonding can also be designated by the term “bonding by molecular adhesion”.
• This type of bonding is commonly used in the field of the invention, to secure two slices of material.
• This type of process involves a layer transfer, with detachment at the level of a weakening zone which has been generated by implantation in the thickness of a donor substrate.
• the layer to be detached Prior to detachment, the layer to be detached is bonded to a support.
• Preliminary phase corresponding to an oxidation step on the surface of the wafer.
• the purpose of this phase is to create an oxide layer, which will be eliminated later.
• the temperature is around 950 ° C.
• the temperature rise is carried out according to a straight ramp, corresponding to a linear temperature progression.
• This slope is typically 5 ° C / minute. This corresponds to a slow rise in temperature within the meaning of this text.
• a problem linked to the second phase (and more generally, to the stabilization annealing of a multilayer wafer or even of a single wafer) is that such a rise in temperature generates type defects
• slip lines are likely to appear over the entire surface of the wafer, in particular at the periphery of the wafer and of the elements supporting the wafer in the annealing furnace.
• FIG. 1 thus illustrates two different views of slip lines 10 observed with an electron microscope (SEM) on an SOI.
• SEM electron microscope
• FIG. 2 thus illustrates another type of observation of an SOI comprising slip lines following a stabilization annealing. This observation is made using KLA Tencor SPI type equipment (registered trademark). In this figure, the slip lines are surrounded. It can be seen that they are distributed close to the periphery of the wafer.
• Figure 3 is another representation of an observation of the type of that of Figure 2, made on a bare silicon wafer having undergone a high temperature stabilization annealing of the same type as that undergone by SOI.
• This figure also illustrates slip lines (here again surrounded) at the edge of the edge.
• the object of the invention is to allow this drawback to be overcome at least to a certain extent.
• the invention proposes a method of heat treatment of a. wafer made from one or more material (s) chosen from semiconductor materials and placed on a support, the process comprising a slow rise in temperature to a end of treatment temperature, characterized in that said rise in temperature is carried out with at least one level to decrease the temperature gradients on the wafer and between the wafer and its support, in order to minimize the appearance of sliding lines in the slice.
• material chosen from semiconductor materials and placed on a support
• the wafer is a multilayer wafer comprising at least two layers joined together via a bonding interface, and said heat treatment is a stabilization annealing of said bonding interface,
• the two stages are carried out at respective temperatures of approximately 1050 ° C. and 1075 ° C.,
• the duration of the plateau, or the cumulative duration of the plateau is defined so as to homogenize and minimize the temperature gradients on the wafer and between the wafer and its support
• the rise in temperature includes:> An initial rise, linear, with a constant slope of the order of
• FIG. 4 is a graph illustrating a rise in temperature of a process according to the invention.
• FIGS. 5 and 6 are graphs illustrating the decrease in slip lines in the implementation of the invention, respectively on a silicon wafer and on an SOI,
• Figures 7 and 8 illustrate the slip lines generated by a heat treatment with a uniform slope, carried out in a longer time than in the prior art.
• This figure represents on the ordinate the evolution of the temperature (in 0 C), as a function of time (which is indicated in hours / minutes).
• a plateau was made at a temperature of the order of 950 ° C. This may correspond to a prior oxidation phase, as mentioned previously.
• the invention can in fact be implemented on a multilayer wafer, for a stabilization annealing of a bonding interface, and this following a first heat treatment phase at a temperature of the order of 950 ° C., in view of oxidizing the slice.
• this rise thus comprises, after the plateau at 950 ° C. which corresponds to an initial oxidation phase:
• the Applicant has determined that the fact of implementing “soft” transitions, with a continuous temperature change, makes it possible to further improve the performances obtained.
• the third rise is not linear, but sees its slope gradually decreasing to approach in an "asymptotic” way the temperature of end of treatment.
• “asymptotic” approach is meant in this text an approach which (unlike a “true” asymptote) allows actually reach the final value (end of treatment temperature), but with a continuously decreasing slope.
• the two levels each have a duration which can be of the order of around ten minutes. It is specified that by "level” is meant a step during which the temperature is maintained at a substantially constant value, for a determined time.
• the duration of the steps (of which the indicative value of ten minutes mentioned above is not limiting) must correspond to a sufficient waiting time for the temperature gradients on the wafer (and between the wafer and its support in the annealing device) can homogenize, and beyond cancel each other as far as possible.
• the duration of the level can therefore vary depending on the value of the temperature ramps, and the temperature difference between the levels: the closer the levels are to the temperature, the shorter they can be.
• the stages are (is) thus preferably located (s) in the upper part of the temperature range traversed in the rise in temperature. In the case of a rise from 950 ° C. to 1100 ° C., the steps will thus preferably be carried out above 1050 ° C.
• the fact of introducing at least one level in the rise in temperature of the stabilization heat treatment makes it possible to reduce the thermal and / or mechanical stresses undergone by the wafer undergoing the treatment.
• the slip lines are indeed due:
• thermal constraints By this is meant the fact that different parts of the wafer, although heated overall together in the same oven, may not all be at the same temperature at a given time, and / or to mechanical stresses. These are the constraints resulting from physical contact between the wafer and the mechanical elements which support it in the oven.
• This mechanical element is commonly a nacelle (typically made of SiC) which supports the wafer.
• the invention therefore proposes a solution allowing, as we will see, to significantly reduce the number of slip lines, while remaining compatible with the requirements of industrial efficiency.
• FIG. 5 presents the results obtained in terms of length and number of slip lines, for different temperature rise conditions between 950 and 1100 ° C. This figure thus presents:
• FIG. 6 likewise illustrates the results obtained in terms of length of slip lines on identical SOI wafers, having undergone a stabilization heat treatment carried out:
• the invention makes it possible to very significantly reduce the number of slip lines generated by a stabilization heat treatment (reduction from 207 to 69 slip lines for SOI identical elsewhere).
• the invention thus generally applies to any high temperature annealing including a slow rise in temperature to a temperature at the end of treatment. And it is specified that preferably, the phase or phases of temperature progression of the slow rise takes place (or take place) according to a slope of 5 ° C / min maximum
• the invention involves a slow rise in temperature comprising at least one level, that is to say that on either side of said one or more level (s) the rates of temperature rise are slow
• the solution proposed by the invention which consists in introducing at least one plateau in the rise in temperature, clearly offers the best results in terms of reduction in the number and length of the slip lines, compared to a linear ramp without temperature rise plateau, for the same values of start and end of rise. And this is achieved with an overall duration of temperature rise which is only very slightly increased.
• the Applicant has carried out tests by subjecting identical wafers to a linear rise in temperature along a constant slope, taking for this rise in temperature the same overall time as for the rise in temperature in FIG. 4. in fact that, compared with a stabilization annealing of the state of the art, the implementation of the invention involves slightly lengthening the time of the stabilization heat treatment.
• slip lines typically correspond to the ends of the fingers of the mechanical element forming a support and supporting the wafer in the heat treatment oven.

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• Element Separation (AREA)
• Laminated Bodies (AREA)
• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

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Family Cites Families (9)

• 2003
  • 2003-06-10 FR FR0306920A patent/FR2856194B1/fr not_active Expired - Lifetime
• 2004
  • 2004-06-10 EP EP04767314A patent/EP1639633A2/de not_active Withdrawn
  • 2004-06-10 JP JP2006516283A patent/JP4949021B2/ja not_active Expired - Lifetime
  • 2004-06-10 WO PCT/FR2004/001449 patent/WO2004112124A2/fr not_active Ceased

Non-Patent Citations (1)

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